1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __IPMI_OCP_H 4 #define __IPMI_OCP_H 5 6 #include <commonlib/bsd/cb_err.h> 7 #include <device/pci_type.h> 8 9 #define IPMI_NETFN_OEM 0x30 10 #define IPMI_OEM_SET_PPIN 0x77 11 #define IPMI_BMC_SET_POST_START 0x73 12 #define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 13 #define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 14 #define IPMI_OEM_GET_BOARD_ID 0x37 15 16 #define CMOS_BIT (1 << 1) 17 #define VALID_BIT (1 << 7) 18 #define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= ~(CMOS_BIT | VALID_BIT)) 19 #define SET_CMOS_AND_VALID_BIT(x) ((x) |= (CMOS_BIT | VALID_BIT)) 20 #define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) 21 22 struct ppin_req { 23 uint32_t cpu0_lo; 24 uint32_t cpu0_hi; 25 uint32_t cpu1_lo; 26 uint32_t cpu1_hi; 27 } __packed; 28 29 struct boot_order { 30 uint8_t boot_mode; 31 uint8_t boot_dev0; 32 uint8_t boot_dev1; 33 uint8_t boot_dev2; 34 uint8_t boot_dev3; 35 uint8_t boot_dev4; 36 } __packed; 37 38 struct pci_dev_fn { 39 u32 func:15; 40 u32 dev:5; 41 u32 bus:12; 42 }; 43 44 struct ipmi_pci_dev_fn { 45 uint16_t func:3; 46 uint16_t dev:5; 47 uint16_t bus:8; 48 }; 49 50 struct ipmi_sel_pcie_dev_err { 51 uint16_t record_id; 52 uint8_t record_type; 53 uint8_t general_info; 54 uint32_t timestamp; 55 uint16_t aux_loc; 56 struct ipmi_pci_dev_fn bdf; 57 uint16_t primary_err_count; 58 uint8_t secondary_id; 59 uint8_t primary_id; 60 } __packed; 61 62 struct iio_port_location { 63 uint8_t socket:4; 64 uint8_t sled:2; 65 uint8_t rsvd:2; 66 }; 67 68 struct ipmi_sel_iio_err { 69 uint16_t record_id; 70 uint8_t record_type; 71 uint8_t general_info; 72 uint32_t timestamp; 73 struct iio_port_location loc; 74 uint8_t iio_stack_num; 75 uint8_t rsvd0; 76 uint8_t rsvd1; 77 uint8_t iio_err_id; 78 uint8_t rsvd2; 79 uint8_t rsvd3; 80 uint8_t rsvd4; 81 } __packed; 82 83 enum fail_type { 84 PCIE_DPC_EVNT = 0, 85 PCIE_LER_EVNT = 1, 86 PCIE_LRTRN_REC = 2, 87 PCIE_CRC_RETRY = 3, 88 PCIE_CRPT_DATA_CONTMT = 4, 89 PCIE_ECRC_EVNT = 5, 90 }; 91 92 enum sel_err_type { 93 MEM_TRAINING_ERR = 0, 94 MEM_CORR_ERR = 1, 95 MEM_UNCORR_ERR = 2, 96 MEM_CORR_ERR_PATROL = 3, 97 MEM_UNCORR_ERR_PATROL = 4, 98 MEM_PARITY_ERR = 5, 99 MEM_UNDEFINED = 0xF, 100 }; 101 102 struct ipmi_sel_pcie_dev_fail { 103 uint16_t record_id; 104 uint8_t record_type; 105 uint8_t general_info; 106 uint32_t timestamp; 107 enum fail_type type; 108 uint8_t rsvd0; 109 uint16_t failure_details1; /* if DPC, DPC sts reg of root port */ 110 uint16_t failure_details2; /* if DPC, source ID of root port */ 111 uint8_t rsvd1; 112 uint8_t rsvd2; 113 } __packed; 114 115 struct ipmi_sel_mem_err { 116 uint16_t record_id; 117 uint8_t record_type; 118 uint8_t general_info; 119 uint32_t timestamp; 120 uint8_t socket; 121 uint8_t channel; 122 uint8_t dimm_slot; 123 uint8_t rsvd1; 124 uint8_t dimm_failure_type; 125 uint8_t major_code; 126 uint8_t minor_code; 127 uint8_t rsvd2; 128 } __packed; 129 130 struct ipmi_config_rsp { 131 uint8_t board_sku_id; 132 uint8_t board_rev_id; 133 uint8_t slot_id; 134 uint8_t slot_config_id; 135 } __packed; 136 137 #define SEL_RECORD_ID 0x01 138 #define SEL_PCIE_DEV_ERR 0x20 139 #define SEL_INTEL_MEMORY_ERROR 0x21 140 #define SEL_PCIE_IIO_ERR 0x23 141 #define SEL_PCIE_DEV_FAIL_ID 0x29 142 143 /* PCIE Unified Messages */ 144 145 /* PCIE CE */ 146 #define RECEIVER_ERROR 0x00 147 #define BAD_TLP 0x01 148 #define BAD_DLLP 0x02 149 #define REPLAY_TIME_OUT 0x03 150 #define REPLAY_NUMBER_ROLLOVER 0x04 151 #define ADVISORY_NONFATAL_ERROR_STATUS 0x05 152 #define CORRECTED_INTERNAL_ERROR_STATUS 0x06 153 #define HEADER_LOG_OVERFLOW_STATUS 0x07 154 155 /* PCIE UCE */ 156 #define PCI_EXPRESS_DATA_LINK_PROTOCOL_ERROR 0x20 157 #define SURPRISE_DOWN_ERROR 0x21 158 #define RECEIVED_PCI_EXPRESS_POISONED_TLP 0x22 159 #define PCI_EXPRESS_FLOW_CONTROL_PROTOCOL_ERROR 0x23 160 #define COMPLETION_TIMEOUT_ON_NP_TRANSACTIONS_OUTSTANDING_ON_PCI_EXPRESS_DMI 0x24 161 #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_TO_BE_COMPLETER_ABORTED 0x25 162 #define RECEIVED_PCI_EXPRESS_UNEXPECTED_COMPLETION 0x26 163 #define PCI_EXPRESS_RECEIVER_OVERFLOW 0x27 164 #define PCI_EXPRESS_MALFORMED_TLP 0x28 165 #define ECRC_ERROR_STATUS 0x29 166 #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_UNSUPPORTED 0x2A 167 #define ACS_VIOLATION 0x2B 168 #define UNCORRECTABLE_INTERNAL_ERROR_STATUS 0x2C 169 #define MC_BLOCKED_TLP 0x2D 170 #define ATOMICOP_EGRESS_BLOCKED_STATUS 0x2E 171 #define TLP_PREFIX_BLOCKED_ERROR_STATUS 0x2F 172 #define POISONED_TLP_EGRESS_BLOCKED 0x30 173 174 /* Root error status (from PCIE spec) */ 175 #define RECEIVED_ERR_COR_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x50 176 #define RECEIVED_ERR_NONFATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x51 177 #define RECEIVED_ERR_FATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x52 178 179 /* DPC Trigger Reason */ 180 #define DPC_WAS_TRIGGERED_DUE_TO_AN_UNMASKED_UNCORRECTABLE_ERROR 0x53 181 #define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_NONFATAL 0x54 182 #define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_FATAL 0x55 183 #define DPC_WAS_TRIGGERED_DUE_TO_RP_PIO_ERROR 0x56 184 #define DPC_WAS_TRIGGERED_DUE_TO_THE_DPC_SOFTWARE_TRIGGER_BIT 0x57 185 186 #define OUTBOUND_SWITCH_FIFO_DATA_PARITY_ERROR_DETECTED 0x80 187 #define SENT_A_PCI_EXPRESS_COMPLETER_ABORT 0x81 188 #define SENT_A_PCI_EXPRESS_UNSUPPORTED_REQUEST 0x82 189 #define RECEIVED_COMPLETER_ABORT 0x83 190 #define RECEIVED_UNSUPPORTED_REQUEST_COMPLETION_STATUS_FROM_DOWNSTREAM_DEVICE 0x84 191 #define RECEIVED_MSI_WRITES_GREATER_THAN_A_DWORD 0x85 192 #define OUTBOUND_POISONED_DATA 0x86 193 #define PERR_NON_AER 0xA0 194 #define SERR_NON_AER 0xA1 195 196 enum cb_err ipmi_set_post_start(const int port); 197 enum cb_err ipmi_set_cmos_clear(void); 198 199 void ipmi_send_to_bmc(unsigned char *data, size_t size); 200 void ipmi_send_sel_pcie_dev_err(pci_devfn_t bdf, uint16_t prmry_cnt, uint8_t sec_id, 201 uint8_t prmry_id); 202 void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code); 203 void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id); 204 205 enum cb_err ipmi_get_board_config(const int port, struct ipmi_config_rsp *config); 206 uint8_t get_blade_id(void); 207 #endif 208