1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices Generic AXI DAC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
5 *
6 * Copyright 2016-2024 Analog Devices Inc.
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/limits.h>
15 #include <linux/kstrtox.h>
16 #include <linux/math.h>
17 #include <linux/math64.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/mutex.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/units.h>
25
26 #include <linux/fpga/adi-axi-common.h>
27 #include <linux/iio/backend.h>
28 #include <linux/iio/buffer-dmaengine.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/iio.h>
31
32 #include "ad3552r-hs.h"
33
34 /*
35 * Register definitions:
36 * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map
37 */
38
39 /* Base controls */
40 #define AXI_DAC_CONFIG_REG 0x0c
41 #define AXI_DAC_CONFIG_DDS_DISABLE BIT(6)
42
43 /* DAC controls */
44 #define AXI_DAC_RSTN_REG 0x0040
45 #define AXI_DAC_RSTN_CE_N BIT(2)
46 #define AXI_DAC_RSTN_MMCM_RSTN BIT(1)
47 #define AXI_DAC_RSTN_RSTN BIT(0)
48 #define AXI_DAC_CNTRL_1_REG 0x0044
49 #define AXI_DAC_CNTRL_1_SYNC BIT(0)
50 #define AXI_DAC_CNTRL_2_REG 0x0048
51 #define AXI_DAC_CNTRL_2_SDR_DDR_N BIT(16)
52 #define AXI_DAC_CNTRL_2_SYMB_8B BIT(14)
53 #define ADI_DAC_CNTRL_2_R1_MODE BIT(5)
54 #define AXI_DAC_CNTRL_2_UNSIGNED_DATA BIT(4)
55 #define AXI_DAC_STATUS_1_REG 0x0054
56 #define AXI_DAC_STATUS_2_REG 0x0058
57 #define AXI_DAC_DRP_STATUS_REG 0x0074
58 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)
59 #define AXI_DAC_CUSTOM_RD_REG 0x0080
60 #define AXI_DAC_CUSTOM_WR_REG 0x0084
61 #define AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16)
62 #define AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8)
63 #define AXI_DAC_UI_STATUS_REG 0x0088
64 #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4)
65 #define AXI_DAC_CUSTOM_CTRL_REG 0x008C
66 #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24)
67 #define AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER BIT(2)
68 #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1)
69 #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0)
70
71 #define AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE (AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \
72 AXI_DAC_CUSTOM_CTRL_STREAM)
73
74 /* DAC Channel controls */
75 #define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40)
76 #define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40)
77 #define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15)
78 #define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14)
79 #define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0)
80 #define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40)
81 #define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16)
82 #define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0)
83 #define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40)
84 #define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40)
85 #define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0)
86
87 #define AXI_DAC_RD_ADDR(x) (BIT(7) | (x))
88
89 /* 360 degrees in rad */
90 #define AXI_DAC_2_PI_MEGA 6283190
91
92 enum {
93 AXI_DAC_DATA_INTERNAL_TONE,
94 AXI_DAC_DATA_DMA = 2,
95 AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11,
96 };
97
98 struct axi_dac_info {
99 unsigned int version;
100 const struct iio_backend_info *backend_info;
101 bool has_dac_clk;
102 bool has_child_nodes;
103 };
104
105 struct axi_dac_state {
106 struct regmap *regmap;
107 struct device *dev;
108 /*
109 * lock to protect multiple accesses to the device registers and global
110 * data/variables.
111 */
112 struct mutex lock;
113 const struct axi_dac_info *info;
114 u64 dac_clk;
115 u32 reg_config;
116 bool int_tone;
117 int dac_clk_rate;
118 };
119
axi_dac_enable(struct iio_backend * back)120 static int axi_dac_enable(struct iio_backend *back)
121 {
122 struct axi_dac_state *st = iio_backend_get_priv(back);
123 unsigned int __val;
124 int ret;
125
126 guard(mutex)(&st->lock);
127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
128 AXI_DAC_RSTN_MMCM_RSTN);
129 if (ret)
130 return ret;
131 /*
132 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
133 * designs really use it but if they don't we still get the lock bit
134 * set. So let's do it all the time so the code is generic.
135 */
136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG,
137 __val,
138 __val & AXI_DAC_DRP_STATUS_DRP_LOCKED,
139 100, 1000);
140 if (ret)
141 return ret;
142
143 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
144 AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN);
145 }
146
axi_dac_disable(struct iio_backend * back)147 static void axi_dac_disable(struct iio_backend *back)
148 {
149 struct axi_dac_state *st = iio_backend_get_priv(back);
150
151 guard(mutex)(&st->lock);
152 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
153 }
154
axi_dac_request_buffer(struct iio_backend * back,struct iio_dev * indio_dev)155 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back,
156 struct iio_dev *indio_dev)
157 {
158 struct axi_dac_state *st = iio_backend_get_priv(back);
159 const char *dma_name;
160
161 if (device_property_read_string(st->dev, "dma-names", &dma_name))
162 dma_name = "tx";
163
164 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name,
165 IIO_BUFFER_DIRECTION_OUT);
166 }
167
axi_dac_free_buffer(struct iio_backend * back,struct iio_buffer * buffer)168 static void axi_dac_free_buffer(struct iio_backend *back,
169 struct iio_buffer *buffer)
170 {
171 iio_dmaengine_buffer_free(buffer);
172 }
173
174 enum {
175 AXI_DAC_FREQ_TONE_1,
176 AXI_DAC_FREQ_TONE_2,
177 AXI_DAC_SCALE_TONE_1,
178 AXI_DAC_SCALE_TONE_2,
179 AXI_DAC_PHASE_TONE_1,
180 AXI_DAC_PHASE_TONE_2,
181 };
182
__axi_dac_frequency_get(struct axi_dac_state * st,unsigned int chan,unsigned int tone_2,unsigned int * freq)183 static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan,
184 unsigned int tone_2, unsigned int *freq)
185 {
186 u32 reg, raw;
187 int ret;
188
189 if (!st->dac_clk) {
190 dev_err(st->dev, "Sampling rate is 0...\n");
191 return -EINVAL;
192 }
193
194 if (tone_2)
195 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
196 else
197 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
198
199 ret = regmap_read(st->regmap, reg, &raw);
200 if (ret)
201 return ret;
202
203 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
204 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16));
205
206 return 0;
207 }
208
axi_dac_frequency_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)209 static int axi_dac_frequency_get(struct axi_dac_state *st,
210 const struct iio_chan_spec *chan, char *buf,
211 unsigned int tone_2)
212 {
213 unsigned int freq;
214 int ret;
215
216 scoped_guard(mutex, &st->lock) {
217 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq);
218 if (ret)
219 return ret;
220 }
221
222 return sysfs_emit(buf, "%u\n", freq);
223 }
224
axi_dac_scale_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)225 static int axi_dac_scale_get(struct axi_dac_state *st,
226 const struct iio_chan_spec *chan, char *buf,
227 unsigned int tone_2)
228 {
229 unsigned int scale, sign;
230 int ret, vals[2];
231 u32 reg, raw;
232
233 if (tone_2)
234 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
235 else
236 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
237
238 ret = regmap_read(st->regmap, reg, &raw);
239 if (ret)
240 return ret;
241
242 sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw);
243 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw);
244 scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA,
245 AXI_DAC_CHAN_CNTRL_3_SCALE_INT);
246
247 vals[0] = scale / MEGA;
248 vals[1] = scale % MEGA;
249
250 if (sign) {
251 vals[0] *= -1;
252 if (!vals[0])
253 vals[1] *= -1;
254 }
255
256 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
257 vals);
258 }
259
axi_dac_phase_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)260 static int axi_dac_phase_get(struct axi_dac_state *st,
261 const struct iio_chan_spec *chan, char *buf,
262 unsigned int tone_2)
263 {
264 u32 reg, raw, phase;
265 int ret, vals[2];
266
267 if (tone_2)
268 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
269 else
270 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
271
272 ret = regmap_read(st->regmap, reg, &raw);
273 if (ret)
274 return ret;
275
276 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw);
277 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
278
279 vals[0] = phase / MEGA;
280 vals[1] = phase % MEGA;
281
282 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
283 vals);
284 }
285
__axi_dac_frequency_set(struct axi_dac_state * st,unsigned int chan,u64 sample_rate,unsigned int freq,unsigned int tone_2)286 static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan,
287 u64 sample_rate, unsigned int freq,
288 unsigned int tone_2)
289 {
290 u32 reg;
291 u16 raw;
292 int ret;
293
294 if (!sample_rate || freq > sample_rate / 2) {
295 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n",
296 freq, sample_rate);
297 return -EINVAL;
298 }
299
300 if (tone_2)
301 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
302 else
303 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
304
305 raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate);
306
307 ret = regmap_update_bits(st->regmap, reg,
308 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
309 if (ret)
310 return ret;
311
312 /* synchronize channels */
313 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
314 AXI_DAC_CNTRL_1_SYNC);
315 }
316
axi_dac_frequency_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)317 static int axi_dac_frequency_set(struct axi_dac_state *st,
318 const struct iio_chan_spec *chan,
319 const char *buf, size_t len, unsigned int tone_2)
320 {
321 unsigned int freq;
322 int ret;
323
324 ret = kstrtou32(buf, 10, &freq);
325 if (ret)
326 return ret;
327
328 guard(mutex)(&st->lock);
329 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq,
330 tone_2);
331 if (ret)
332 return ret;
333
334 return len;
335 }
336
axi_dac_scale_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)337 static int axi_dac_scale_set(struct axi_dac_state *st,
338 const struct iio_chan_spec *chan,
339 const char *buf, size_t len, unsigned int tone_2)
340 {
341 int integer, frac, scale;
342 u32 raw = 0, reg;
343 int ret;
344
345 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
346 if (ret)
347 return ret;
348
349 scale = integer * MEGA + frac;
350 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA)
351 return -EINVAL;
352
353 /* format is 1.1.14 (sign, integer and fractional bits) */
354 if (scale < 0) {
355 raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1);
356 scale *= -1;
357 }
358
359 raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA);
360
361 if (tone_2)
362 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
363 else
364 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
365
366 guard(mutex)(&st->lock);
367 ret = regmap_write(st->regmap, reg, raw);
368 if (ret)
369 return ret;
370
371 /* synchronize channels */
372 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
373 AXI_DAC_CNTRL_1_SYNC);
374 if (ret)
375 return ret;
376
377 return len;
378 }
379
axi_dac_phase_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)380 static int axi_dac_phase_set(struct axi_dac_state *st,
381 const struct iio_chan_spec *chan,
382 const char *buf, size_t len, unsigned int tone_2)
383 {
384 int integer, frac, phase;
385 u32 raw, reg;
386 int ret;
387
388 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
389 if (ret)
390 return ret;
391
392 phase = integer * MEGA + frac;
393 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA)
394 return -EINVAL;
395
396 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
397
398 if (tone_2)
399 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
400 else
401 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
402
403 guard(mutex)(&st->lock);
404 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE,
405 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw));
406 if (ret)
407 return ret;
408
409 /* synchronize channels */
410 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
411 AXI_DAC_CNTRL_1_SYNC);
412 if (ret)
413 return ret;
414
415 return len;
416 }
417
axi_dac_ext_info_set(struct iio_backend * back,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)418 static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private,
419 const struct iio_chan_spec *chan,
420 const char *buf, size_t len)
421 {
422 struct axi_dac_state *st = iio_backend_get_priv(back);
423
424 switch (private) {
425 case AXI_DAC_FREQ_TONE_1:
426 case AXI_DAC_FREQ_TONE_2:
427 return axi_dac_frequency_set(st, chan, buf, len,
428 private == AXI_DAC_FREQ_TONE_2);
429 case AXI_DAC_SCALE_TONE_1:
430 case AXI_DAC_SCALE_TONE_2:
431 return axi_dac_scale_set(st, chan, buf, len,
432 private == AXI_DAC_SCALE_TONE_2);
433 case AXI_DAC_PHASE_TONE_1:
434 case AXI_DAC_PHASE_TONE_2:
435 return axi_dac_phase_set(st, chan, buf, len,
436 private == AXI_DAC_PHASE_TONE_2);
437 default:
438 return -EOPNOTSUPP;
439 }
440 }
441
axi_dac_ext_info_get(struct iio_backend * back,uintptr_t private,const struct iio_chan_spec * chan,char * buf)442 static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private,
443 const struct iio_chan_spec *chan, char *buf)
444 {
445 struct axi_dac_state *st = iio_backend_get_priv(back);
446
447 switch (private) {
448 case AXI_DAC_FREQ_TONE_1:
449 case AXI_DAC_FREQ_TONE_2:
450 return axi_dac_frequency_get(st, chan, buf,
451 private - AXI_DAC_FREQ_TONE_1);
452 case AXI_DAC_SCALE_TONE_1:
453 case AXI_DAC_SCALE_TONE_2:
454 return axi_dac_scale_get(st, chan, buf,
455 private - AXI_DAC_SCALE_TONE_1);
456 case AXI_DAC_PHASE_TONE_1:
457 case AXI_DAC_PHASE_TONE_2:
458 return axi_dac_phase_get(st, chan, buf,
459 private - AXI_DAC_PHASE_TONE_1);
460 default:
461 return -EOPNOTSUPP;
462 }
463 }
464
465 static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = {
466 IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1),
467 IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2),
468 IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1),
469 IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2),
470 IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1),
471 IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2),
472 {}
473 };
474
axi_dac_extend_chan(struct iio_backend * back,struct iio_chan_spec * chan)475 static int axi_dac_extend_chan(struct iio_backend *back,
476 struct iio_chan_spec *chan)
477 {
478 struct axi_dac_state *st = iio_backend_get_priv(back);
479
480 if (chan->type != IIO_ALTVOLTAGE)
481 return -EINVAL;
482 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
483 /* nothing to extend */
484 return 0;
485
486 chan->ext_info = axi_dac_ext_info;
487
488 return 0;
489 }
490
axi_dac_data_source_set(struct iio_backend * back,unsigned int chan,enum iio_backend_data_source data)491 static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan,
492 enum iio_backend_data_source data)
493 {
494 struct axi_dac_state *st = iio_backend_get_priv(back);
495
496 switch (data) {
497 case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE:
498 return regmap_update_bits(st->regmap,
499 AXI_DAC_CHAN_CNTRL_7_REG(chan),
500 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
501 AXI_DAC_DATA_INTERNAL_TONE);
502 case IIO_BACKEND_EXTERNAL:
503 return regmap_update_bits(st->regmap,
504 AXI_DAC_CHAN_CNTRL_7_REG(chan),
505 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
506 AXI_DAC_DATA_DMA);
507 case IIO_BACKEND_INTERNAL_RAMP_16BIT:
508 return regmap_update_bits(st->regmap,
509 AXI_DAC_CHAN_CNTRL_7_REG(chan),
510 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
511 AXI_DAC_DATA_INTERNAL_RAMP_16BIT);
512 default:
513 return -EINVAL;
514 }
515 }
516
axi_dac_set_sample_rate(struct iio_backend * back,unsigned int chan,u64 sample_rate)517 static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan,
518 u64 sample_rate)
519 {
520 struct axi_dac_state *st = iio_backend_get_priv(back);
521 unsigned int freq;
522 int ret, tone;
523
524 if (!sample_rate)
525 return -EINVAL;
526 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
527 /* sample_rate has no meaning if DDS is disabled */
528 return 0;
529
530 guard(mutex)(&st->lock);
531 /*
532 * If dac_clk is 0 then this must be the first time we're being notified
533 * about the interface sample rate. Hence, just update our internal
534 * variable and bail... If it's not 0, then we get the current DDS
535 * frequency (for the old rate) and update the registers for the new
536 * sample rate.
537 */
538 if (!st->dac_clk) {
539 st->dac_clk = sample_rate;
540 return 0;
541 }
542
543 for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) {
544 ret = __axi_dac_frequency_get(st, chan, tone, &freq);
545 if (ret)
546 return ret;
547
548 ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq);
549 if (ret)
550 return ret;
551 }
552
553 st->dac_clk = sample_rate;
554
555 return 0;
556 }
557
axi_dac_reg_access(struct iio_backend * back,unsigned int reg,unsigned int writeval,unsigned int * readval)558 static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg,
559 unsigned int writeval, unsigned int *readval)
560 {
561 struct axi_dac_state *st = iio_backend_get_priv(back);
562
563 if (readval)
564 return regmap_read(st->regmap, reg, readval);
565
566 return regmap_write(st->regmap, reg, writeval);
567 }
568
axi_dac_ddr_enable(struct iio_backend * back)569 static int axi_dac_ddr_enable(struct iio_backend *back)
570 {
571 struct axi_dac_state *st = iio_backend_get_priv(back);
572
573 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
574 AXI_DAC_CNTRL_2_SDR_DDR_N);
575 }
576
axi_dac_ddr_disable(struct iio_backend * back)577 static int axi_dac_ddr_disable(struct iio_backend *back)
578 {
579 struct axi_dac_state *st = iio_backend_get_priv(back);
580
581 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
582 AXI_DAC_CNTRL_2_SDR_DDR_N);
583 }
584
axi_dac_data_stream_enable(struct iio_backend * back)585 static int axi_dac_data_stream_enable(struct iio_backend *back)
586 {
587 struct axi_dac_state *st = iio_backend_get_priv(back);
588 int ret, val;
589
590 ret = regmap_read_poll_timeout(st->regmap,
591 AXI_DAC_UI_STATUS_REG, val,
592 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0,
593 10, 100 * KILO);
594 if (ret)
595 return ret;
596
597 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
598 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
599 }
600
axi_dac_data_stream_disable(struct iio_backend * back)601 static int axi_dac_data_stream_disable(struct iio_backend *back)
602 {
603 struct axi_dac_state *st = iio_backend_get_priv(back);
604
605 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
606 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
607 }
608
axi_dac_data_transfer_addr(struct iio_backend * back,u32 address)609 static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address)
610 {
611 struct axi_dac_state *st = iio_backend_get_priv(back);
612
613 if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS))
614 return -EINVAL;
615
616 /*
617 * Sample register address, when the DAC is configured, or stream
618 * start address when the FSM is in stream state.
619 */
620 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
621 AXI_DAC_CUSTOM_CTRL_ADDRESS,
622 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS,
623 address));
624 }
625
axi_dac_data_format_set(struct iio_backend * back,unsigned int ch,const struct iio_backend_data_fmt * data)626 static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch,
627 const struct iio_backend_data_fmt *data)
628 {
629 struct axi_dac_state *st = iio_backend_get_priv(back);
630
631 switch (data->type) {
632 case IIO_BACKEND_DATA_UNSIGNED:
633 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
634 AXI_DAC_CNTRL_2_UNSIGNED_DATA);
635 default:
636 return -EINVAL;
637 }
638 }
639
__axi_dac_bus_reg_write(struct iio_backend * back,u32 reg,u32 val,size_t data_size)640 static int __axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
641 u32 val, size_t data_size)
642 {
643 struct axi_dac_state *st = iio_backend_get_priv(back);
644 int ret;
645 u32 ival;
646
647 /*
648 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know
649 * the data size. So keeping data size control here only,
650 * since data size is mandatory for the current transfer.
651 * DDR state handled separately by specific backend calls,
652 * generally all raw register writes are SDR.
653 */
654 if (data_size == sizeof(u16))
655 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val);
656 else
657 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val);
658
659 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival);
660 if (ret)
661 return ret;
662
663 if (data_size == sizeof(u8))
664 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
665 AXI_DAC_CNTRL_2_SYMB_8B);
666 else
667 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
668 AXI_DAC_CNTRL_2_SYMB_8B);
669 if (ret)
670 return ret;
671
672 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
673 AXI_DAC_CUSTOM_CTRL_ADDRESS,
674 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg));
675 if (ret)
676 return ret;
677
678 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
679 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA,
680 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
681 if (ret)
682 return ret;
683
684 ret = regmap_read_poll_timeout(st->regmap,
685 AXI_DAC_UI_STATUS_REG, ival,
686 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0,
687 10, 100 * KILO);
688 if (ret == -ETIMEDOUT)
689 dev_err(st->dev, "AXI read timeout\n");
690
691 /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */
692 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
693 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
694 }
695
axi_dac_bus_reg_write(struct iio_backend * back,u32 reg,u32 val,size_t data_size)696 static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
697 u32 val, size_t data_size)
698 {
699 struct axi_dac_state *st = iio_backend_get_priv(back);
700
701 guard(mutex)(&st->lock);
702 return __axi_dac_bus_reg_write(back, reg, val, data_size);
703 }
704
axi_dac_bus_reg_read(struct iio_backend * back,u32 reg,u32 * val,size_t data_size)705 static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val,
706 size_t data_size)
707 {
708 struct axi_dac_state *st = iio_backend_get_priv(back);
709 int ret;
710
711 guard(mutex)(&st->lock);
712
713 /*
714 * SPI, we write with read flag, then we read just at the AXI
715 * io address space to get data read.
716 */
717 ret = __axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0,
718 data_size);
719 if (ret)
720 return ret;
721
722 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val);
723 }
724
axi_dac_child_remove(void * data)725 static void axi_dac_child_remove(void *data)
726 {
727 platform_device_unregister(data);
728 }
729
axi_dac_create_platform_device(struct axi_dac_state * st,struct fwnode_handle * child)730 static int axi_dac_create_platform_device(struct axi_dac_state *st,
731 struct fwnode_handle *child)
732 {
733 struct ad3552r_hs_platform_data pdata = {
734 .bus_reg_read = axi_dac_bus_reg_read,
735 .bus_reg_write = axi_dac_bus_reg_write,
736 .bus_sample_data_clock_hz = st->dac_clk_rate,
737 };
738 struct platform_device_info pi = {
739 .parent = st->dev,
740 .name = fwnode_get_name(child),
741 .id = PLATFORM_DEVID_AUTO,
742 .fwnode = child,
743 .data = &pdata,
744 .size_data = sizeof(pdata),
745 };
746 struct platform_device *pdev;
747
748 pdev = platform_device_register_full(&pi);
749 if (IS_ERR(pdev))
750 return PTR_ERR(pdev);
751
752 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev);
753 }
754
755 static const struct iio_backend_ops axi_dac_generic_ops = {
756 .enable = axi_dac_enable,
757 .disable = axi_dac_disable,
758 .request_buffer = axi_dac_request_buffer,
759 .free_buffer = axi_dac_free_buffer,
760 .extend_chan_spec = axi_dac_extend_chan,
761 .ext_info_set = axi_dac_ext_info_set,
762 .ext_info_get = axi_dac_ext_info_get,
763 .data_source_set = axi_dac_data_source_set,
764 .set_sample_rate = axi_dac_set_sample_rate,
765 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access),
766 };
767
768 static const struct iio_backend_ops axi_ad3552r_ops = {
769 .enable = axi_dac_enable,
770 .disable = axi_dac_disable,
771 .request_buffer = axi_dac_request_buffer,
772 .free_buffer = axi_dac_free_buffer,
773 .data_source_set = axi_dac_data_source_set,
774 .ddr_enable = axi_dac_ddr_enable,
775 .ddr_disable = axi_dac_ddr_disable,
776 .data_stream_enable = axi_dac_data_stream_enable,
777 .data_stream_disable = axi_dac_data_stream_disable,
778 .data_format_set = axi_dac_data_format_set,
779 .data_transfer_addr = axi_dac_data_transfer_addr,
780 };
781
782 static const struct iio_backend_info axi_dac_generic = {
783 .name = "axi-dac",
784 .ops = &axi_dac_generic_ops,
785 };
786
787 static const struct iio_backend_info axi_ad3552r = {
788 .name = "axi-ad3552r",
789 .ops = &axi_ad3552r_ops,
790 };
791
792 static const struct regmap_config axi_dac_regmap_config = {
793 .val_bits = 32,
794 .reg_bits = 32,
795 .reg_stride = 4,
796 .max_register = 0x0800,
797 };
798
axi_dac_probe(struct platform_device * pdev)799 static int axi_dac_probe(struct platform_device *pdev)
800 {
801 struct axi_dac_state *st;
802 void __iomem *base;
803 unsigned int ver;
804 struct clk *clk;
805 int ret;
806
807 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
808 if (!st)
809 return -ENOMEM;
810
811 st->info = device_get_match_data(&pdev->dev);
812 if (!st->info)
813 return -ENODEV;
814 clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
815 if (IS_ERR(clk)) {
816 /* Backward compat., old fdt versions without clock-names. */
817 clk = devm_clk_get_enabled(&pdev->dev, NULL);
818 if (IS_ERR(clk))
819 return dev_err_probe(&pdev->dev, PTR_ERR(clk),
820 "failed to get clock\n");
821 }
822
823 if (st->info->has_dac_clk) {
824 struct clk *dac_clk;
825
826 dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk");
827 if (IS_ERR(dac_clk))
828 return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk),
829 "failed to get dac_clk clock\n");
830
831 /* We only care about the streaming mode rate */
832 st->dac_clk_rate = clk_get_rate(dac_clk) / 2;
833 }
834
835 base = devm_platform_ioremap_resource(pdev, 0);
836 if (IS_ERR(base))
837 return PTR_ERR(base);
838
839 st->dev = &pdev->dev;
840 st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
841 &axi_dac_regmap_config);
842 if (IS_ERR(st->regmap))
843 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap),
844 "failed to init register map\n");
845
846 /*
847 * Force disable the core. Up to the frontend to enable us. And we can
848 * still read/write registers...
849 */
850 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
851 if (ret)
852 return ret;
853
854 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
855 if (ret)
856 return ret;
857
858 if (ADI_AXI_PCORE_VER_MAJOR(ver) !=
859 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) {
860 dev_err(&pdev->dev,
861 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
862 ADI_AXI_PCORE_VER_MAJOR(st->info->version),
863 ADI_AXI_PCORE_VER_MINOR(st->info->version),
864 ADI_AXI_PCORE_VER_PATCH(st->info->version),
865 ADI_AXI_PCORE_VER_MAJOR(ver),
866 ADI_AXI_PCORE_VER_MINOR(ver),
867 ADI_AXI_PCORE_VER_PATCH(ver));
868 return -ENODEV;
869 }
870
871 /* Let's get the core read only configuration */
872 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config);
873 if (ret)
874 return ret;
875
876 /*
877 * In some designs, setting the R1_MODE bit to 0 (which is the default
878 * value) causes all channels of the frontend to be routed to the same
879 * DMA (so they are sampled together). This is for things like
880 * Multiple-Input and Multiple-Output (MIMO). As most of the times we
881 * want independent channels let's override the core's default value and
882 * set the R1_MODE bit.
883 */
884 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
885 ADI_DAC_CNTRL_2_R1_MODE);
886 if (ret)
887 return ret;
888
889 mutex_init(&st->lock);
890
891 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st);
892 if (ret)
893 return dev_err_probe(&pdev->dev, ret,
894 "failed to register iio backend\n");
895
896 device_for_each_child_node_scoped(&pdev->dev, child) {
897 int val;
898
899 if (!st->info->has_child_nodes)
900 return dev_err_probe(&pdev->dev, -EINVAL,
901 "invalid fdt axi-dac compatible.");
902
903 /* Processing only reg 0 node */
904 ret = fwnode_property_read_u32(child, "reg", &val);
905 if (ret)
906 return dev_err_probe(&pdev->dev, ret,
907 "invalid reg property.");
908 if (val != 0)
909 return dev_err_probe(&pdev->dev, -EINVAL,
910 "invalid node address.");
911
912 ret = axi_dac_create_platform_device(st, child);
913 if (ret)
914 return dev_err_probe(&pdev->dev, -EINVAL,
915 "cannot create device.");
916 }
917
918 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
919 ADI_AXI_PCORE_VER_MAJOR(ver),
920 ADI_AXI_PCORE_VER_MINOR(ver),
921 ADI_AXI_PCORE_VER_PATCH(ver));
922
923 return 0;
924 }
925
926 static const struct axi_dac_info dac_generic = {
927 .version = ADI_AXI_PCORE_VER(9, 1, 'b'),
928 .backend_info = &axi_dac_generic,
929 };
930
931 static const struct axi_dac_info dac_ad3552r = {
932 .version = ADI_AXI_PCORE_VER(9, 1, 'b'),
933 .backend_info = &axi_ad3552r,
934 .has_dac_clk = true,
935 .has_child_nodes = true,
936 };
937
938 static const struct of_device_id axi_dac_of_match[] = {
939 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic },
940 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r },
941 {}
942 };
943 MODULE_DEVICE_TABLE(of, axi_dac_of_match);
944
945 static struct platform_driver axi_dac_driver = {
946 .driver = {
947 .name = "adi-axi-dac",
948 .of_match_table = axi_dac_of_match,
949 },
950 .probe = axi_dac_probe,
951 };
952 module_platform_driver(axi_dac_driver);
953
954 MODULE_AUTHOR("Nuno Sa <[email protected]>");
955 MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver");
956 MODULE_LICENSE("GPL");
957 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
958 MODULE_IMPORT_NS("IIO_BACKEND");
959