1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <[email protected]>
5 */
6
7 #include <linux/unaligned.h>
8 #include <linux/bitfield.h>
9 #include <linux/cleanup.h>
10 #include <linux/crc8.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/trigger.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/interrupt.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spi/spi.h>
27
28 #include <dt-bindings/iio/addac/adi,ad74413r.h>
29
30 #define AD74413R_CRC_POLYNOMIAL 0x7
31 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
32
33 #define AD74413R_CHANNEL_MAX 4
34
35 #define AD74413R_FRAME_SIZE 4
36
37 struct ad74413r_chip_info {
38 const char *name;
39 bool hart_support;
40 };
41
42 struct ad74413r_channel_config {
43 u32 func;
44 u32 drive_strength;
45 bool gpo_comparator;
46 bool initialized;
47 };
48
49 struct ad74413r_channels {
50 const struct iio_chan_spec *channels;
51 unsigned int num_channels;
52 };
53
54 struct ad74413r_state {
55 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX];
56 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
57 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX];
58 struct gpio_chip gpo_gpiochip;
59 struct gpio_chip comp_gpiochip;
60 struct completion adc_data_completion;
61 unsigned int num_gpo_gpios;
62 unsigned int num_comparator_gpios;
63 u32 sense_resistor_ohms;
64 int refin_reg_uv;
65 /*
66 * Synchronize consecutive operations when doing a one-shot
67 * conversion and when updating the ADC samples SPI message.
68 */
69 struct mutex lock;
70
71 const struct ad74413r_chip_info *chip_info;
72 struct spi_device *spi;
73 struct regmap *regmap;
74 struct device *dev;
75 struct iio_trigger *trig;
76
77 size_t adc_active_channels;
78 struct spi_message adc_samples_msg;
79 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
80
81 /*
82 * DMA (thus cache coherency maintenance) may require the
83 * transfer buffers to live in their own cache lines.
84 */
85 struct {
86 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
87 s64 timestamp;
88 } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
89
90 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
91 u8 reg_tx_buf[AD74413R_FRAME_SIZE];
92 u8 reg_rx_buf[AD74413R_FRAME_SIZE];
93 };
94
95 #define AD74413R_REG_NOP 0x00
96
97 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
98 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
99
100 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
101 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5)
102 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3)
103 #define AD74413R_ADC_CONFIG_CH_200K_TO_GND BIT(2)
104 #define AD74413R_ADC_RANGE_10V 0b000
105 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
106 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
107 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
108 #define AD74413R_ADC_REJECTION_50_60 0b00
109 #define AD74413R_ADC_REJECTION_NONE 0b01
110 #define AD74413R_ADC_REJECTION_50_60_HART 0b10
111 #define AD74413R_ADC_REJECTION_HART 0b11
112
113 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x))
114 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0)
115 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5)
116 #define AD74413R_DIN_SINK_MASK GENMASK(9, 6)
117
118 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x))
119 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0)
120 #define AD74413R_DAC_VOLTAGE_MAX 11000
121
122 #define AD74413R_REG_GPO_PAR_DATA 0x0d
123 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x))
124 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3)
125 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0)
126 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000
127 #define AD74413R_GPO_CONFIG_LOGIC 0b001
128 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010
129 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011
130 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100
131
132 #define AD74413R_REG_ADC_CONV_CTRL 0x23
133 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8)
134 #define AD74413R_CONV_SEQ_ON 0b00
135 #define AD74413R_CONV_SEQ_SINGLE 0b01
136 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10
137 #define AD74413R_CONV_SEQ_OFF 0b11
138 #define AD74413R_CH_EN_MASK(x) BIT(x)
139
140 #define AD74413R_REG_DIN_COMP_OUT 0x25
141
142 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x))
143 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0)
144
145 #define AD74413R_REG_READ_SELECT 0x41
146
147 #define AD74413R_REG_CMD_KEY 0x44
148 #define AD74413R_CMD_KEY_LDAC 0x953a
149 #define AD74413R_CMD_KEY_RESET1 0x15fa
150 #define AD74413R_CMD_KEY_RESET2 0xaf51
151
152 static const int ad74413r_adc_sampling_rates[] = {
153 20, 4800,
154 };
155
156 static const int ad74413r_adc_sampling_rates_hart[] = {
157 10, 20, 1200, 4800,
158 };
159
ad74413r_crc(u8 * buf)160 static int ad74413r_crc(u8 *buf)
161 {
162 return crc8(ad74413r_crc8_table, buf, 3, 0);
163 }
164
ad74413r_format_reg_write(u8 reg,u16 val,u8 * buf)165 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
166 {
167 buf[0] = reg;
168 put_unaligned_be16(val, &buf[1]);
169 buf[3] = ad74413r_crc(buf);
170 }
171
ad74413r_reg_write(void * context,unsigned int reg,unsigned int val)172 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
173 {
174 struct ad74413r_state *st = context;
175
176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
177
178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
179 }
180
ad74413r_crc_check(struct ad74413r_state * st,u8 * buf)181 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
182 {
183 u8 expected_crc = ad74413r_crc(buf);
184
185 if (buf[3] != expected_crc) {
186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
187 buf[3], buf[0], buf[1], buf[2]);
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
ad74413r_reg_read(void * context,unsigned int reg,unsigned int * val)194 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
195 {
196 struct ad74413r_state *st = context;
197 struct spi_transfer reg_read_xfer[] = {
198 {
199 .tx_buf = st->reg_tx_buf,
200 .len = AD74413R_FRAME_SIZE,
201 .cs_change = 1,
202 },
203 {
204 .rx_buf = st->reg_rx_buf,
205 .len = AD74413R_FRAME_SIZE,
206 },
207 };
208 int ret;
209
210 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
211 st->reg_tx_buf);
212
213 ret = spi_sync_transfer(st->spi, reg_read_xfer,
214 ARRAY_SIZE(reg_read_xfer));
215 if (ret)
216 return ret;
217
218 ret = ad74413r_crc_check(st, st->reg_rx_buf);
219 if (ret)
220 return ret;
221
222 *val = get_unaligned_be16(&st->reg_rx_buf[1]);
223
224 return 0;
225 }
226
227 static const struct regmap_config ad74413r_regmap_config = {
228 .reg_bits = 8,
229 .val_bits = 16,
230 .reg_read = ad74413r_reg_read,
231 .reg_write = ad74413r_reg_write,
232 };
233
ad74413r_set_gpo_config(struct ad74413r_state * st,unsigned int offset,u8 mode)234 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
235 unsigned int offset, u8 mode)
236 {
237 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
238 AD74413R_GPO_CONFIG_SELECT_MASK, mode);
239 }
240
241 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
242 0, 13, 18, 24, 32, 42, 56, 75,
243 100, 130, 180, 240, 320, 420, 560, 750,
244 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500,
245 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
246 };
247
ad74413r_set_comp_debounce(struct ad74413r_state * st,unsigned int offset,unsigned int debounce)248 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
249 unsigned int offset,
250 unsigned int debounce)
251 {
252 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
253 unsigned int i;
254
255 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
256 if (debounce <= ad74413r_debounce_map[i]) {
257 val = i;
258 break;
259 }
260
261 return regmap_update_bits(st->regmap,
262 AD74413R_REG_DIN_CONFIG_X(offset),
263 AD74413R_DIN_DEBOUNCE_MASK,
264 val);
265 }
266
ad74413r_set_comp_drive_strength(struct ad74413r_state * st,unsigned int offset,unsigned int strength)267 static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st,
268 unsigned int offset,
269 unsigned int strength)
270 {
271 strength = min(strength, 1800U);
272
273 return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset),
274 AD74413R_DIN_SINK_MASK,
275 FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120));
276 }
277
278
ad74413r_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)279 static void ad74413r_gpio_set(struct gpio_chip *chip,
280 unsigned int offset, int val)
281 {
282 struct ad74413r_state *st = gpiochip_get_data(chip);
283 unsigned int real_offset = st->gpo_gpio_offsets[offset];
284 int ret;
285
286 ret = ad74413r_set_gpo_config(st, real_offset,
287 AD74413R_GPO_CONFIG_LOGIC);
288 if (ret)
289 return;
290
291 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset),
292 AD74413R_GPO_CONFIG_DATA_MASK,
293 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
294 }
295
ad74413r_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)296 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip,
297 unsigned long *mask,
298 unsigned long *bits)
299 {
300 struct ad74413r_state *st = gpiochip_get_data(chip);
301 unsigned long real_mask = 0;
302 unsigned long real_bits = 0;
303 unsigned int offset;
304 int ret;
305
306 for_each_set_bit(offset, mask, chip->ngpio) {
307 unsigned int real_offset = st->gpo_gpio_offsets[offset];
308
309 ret = ad74413r_set_gpo_config(st, real_offset,
310 AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
311 if (ret)
312 return;
313
314 real_mask |= BIT(real_offset);
315 if (*bits & offset)
316 real_bits |= BIT(real_offset);
317 }
318
319 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
320 real_mask, real_bits);
321 }
322
ad74413r_gpio_get(struct gpio_chip * chip,unsigned int offset)323 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
324 {
325 struct ad74413r_state *st = gpiochip_get_data(chip);
326 unsigned int real_offset = st->comp_gpio_offsets[offset];
327 unsigned int status;
328 int ret;
329
330 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
331 if (ret)
332 return ret;
333
334 status &= BIT(real_offset);
335
336 return status ? 1 : 0;
337 }
338
ad74413r_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)339 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
340 unsigned long *mask,
341 unsigned long *bits)
342 {
343 struct ad74413r_state *st = gpiochip_get_data(chip);
344 unsigned int offset;
345 unsigned int val;
346 int ret;
347
348 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
349 if (ret)
350 return ret;
351
352 for_each_set_bit(offset, mask, chip->ngpio) {
353 unsigned int real_offset = st->comp_gpio_offsets[offset];
354
355 __assign_bit(offset, bits, val & BIT(real_offset));
356 }
357
358 return ret;
359 }
360
ad74413r_gpio_get_gpo_direction(struct gpio_chip * chip,unsigned int offset)361 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
362 unsigned int offset)
363 {
364 return GPIO_LINE_DIRECTION_OUT;
365 }
366
ad74413r_gpio_get_comp_direction(struct gpio_chip * chip,unsigned int offset)367 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
368 unsigned int offset)
369 {
370 return GPIO_LINE_DIRECTION_IN;
371 }
372
ad74413r_gpio_set_gpo_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)373 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
374 unsigned int offset,
375 unsigned long config)
376 {
377 struct ad74413r_state *st = gpiochip_get_data(chip);
378 unsigned int real_offset = st->gpo_gpio_offsets[offset];
379
380 switch (pinconf_to_config_param(config)) {
381 case PIN_CONFIG_BIAS_PULL_DOWN:
382 return ad74413r_set_gpo_config(st, real_offset,
383 AD74413R_GPO_CONFIG_100K_PULL_DOWN);
384 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
385 return ad74413r_set_gpo_config(st, real_offset,
386 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
387 default:
388 return -ENOTSUPP;
389 }
390 }
391
ad74413r_gpio_set_comp_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)392 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
393 unsigned int offset,
394 unsigned long config)
395 {
396 struct ad74413r_state *st = gpiochip_get_data(chip);
397 unsigned int real_offset = st->comp_gpio_offsets[offset];
398
399 switch (pinconf_to_config_param(config)) {
400 case PIN_CONFIG_INPUT_DEBOUNCE:
401 return ad74413r_set_comp_debounce(st, real_offset,
402 pinconf_to_config_argument(config));
403 default:
404 return -ENOTSUPP;
405 }
406 }
407
ad74413r_reset(struct ad74413r_state * st)408 static int ad74413r_reset(struct ad74413r_state *st)
409 {
410 struct gpio_desc *reset_gpio;
411 int ret;
412
413 reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_HIGH);
414 if (IS_ERR(reset_gpio))
415 return PTR_ERR(reset_gpio);
416
417 if (reset_gpio) {
418 fsleep(50);
419 gpiod_set_value_cansleep(reset_gpio, 0);
420 return 0;
421 }
422
423 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
424 AD74413R_CMD_KEY_RESET1);
425 if (ret)
426 return ret;
427
428 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
429 AD74413R_CMD_KEY_RESET2);
430 }
431
ad74413r_set_channel_dac_code(struct ad74413r_state * st,unsigned int channel,int dac_code)432 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
433 unsigned int channel, int dac_code)
434 {
435 struct reg_sequence reg_seq[2] = {
436 { AD74413R_REG_DAC_CODE_X(channel), dac_code },
437 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
438 };
439
440 return regmap_multi_reg_write(st->regmap, reg_seq, 2);
441 }
442
ad74413r_set_channel_function(struct ad74413r_state * st,unsigned int channel,u8 func)443 static int ad74413r_set_channel_function(struct ad74413r_state *st,
444 unsigned int channel, u8 func)
445 {
446 int ret;
447
448 ret = regmap_update_bits(st->regmap,
449 AD74413R_REG_CH_FUNC_SETUP_X(channel),
450 AD74413R_CH_FUNC_SETUP_MASK,
451 CH_FUNC_HIGH_IMPEDANCE);
452 if (ret)
453 return ret;
454
455 /* Set DAC code to 0 prior to changing channel function */
456 ret = ad74413r_set_channel_dac_code(st, channel, 0);
457 if (ret)
458 return ret;
459
460 /* Delay required before transition to new desired mode */
461 usleep_range(130, 150);
462
463 ret = regmap_update_bits(st->regmap,
464 AD74413R_REG_CH_FUNC_SETUP_X(channel),
465 AD74413R_CH_FUNC_SETUP_MASK, func);
466 if (ret)
467 return ret;
468
469 /* Delay required before updating the new DAC code */
470 usleep_range(150, 170);
471
472 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER)
473 ret = regmap_set_bits(st->regmap,
474 AD74413R_REG_ADC_CONFIG_X(channel),
475 AD74413R_ADC_CONFIG_CH_200K_TO_GND);
476
477 return ret;
478 }
479
ad74413r_set_adc_conv_seq(struct ad74413r_state * st,unsigned int status)480 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
481 unsigned int status)
482 {
483 int ret;
484
485 /*
486 * These bits do not clear when a conversion completes.
487 * To enable a subsequent conversion, repeat the write.
488 */
489 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
490 AD74413R_CONV_SEQ_MASK,
491 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
492 if (ret)
493 return ret;
494
495 /*
496 * Wait 100us before starting conversions.
497 */
498 usleep_range(100, 120);
499
500 return 0;
501 }
502
ad74413r_set_adc_channel_enable(struct ad74413r_state * st,unsigned int channel,bool status)503 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
504 unsigned int channel,
505 bool status)
506 {
507 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
508 AD74413R_CH_EN_MASK(channel),
509 status ? AD74413R_CH_EN_MASK(channel) : 0);
510 }
511
ad74413r_get_adc_range(struct ad74413r_state * st,unsigned int channel,unsigned int * val)512 static int ad74413r_get_adc_range(struct ad74413r_state *st,
513 unsigned int channel,
514 unsigned int *val)
515 {
516 int ret;
517
518 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
519 if (ret)
520 return ret;
521
522 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
523
524 return 0;
525 }
526
ad74413r_get_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int * val)527 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
528 unsigned int channel,
529 unsigned int *val)
530 {
531 int ret;
532
533 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
534 if (ret)
535 return ret;
536
537 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
538
539 return 0;
540 }
541
ad74413r_set_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int val)542 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
543 unsigned int channel,
544 unsigned int val)
545 {
546 return regmap_update_bits(st->regmap,
547 AD74413R_REG_ADC_CONFIG_X(channel),
548 AD74413R_ADC_CONFIG_REJECTION_MASK,
549 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
550 val));
551 }
552
ad74413r_rejection_to_rate(struct ad74413r_state * st,unsigned int rej,int * val)553 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
554 unsigned int rej, int *val)
555 {
556 switch (rej) {
557 case AD74413R_ADC_REJECTION_50_60:
558 *val = 20;
559 return 0;
560 case AD74413R_ADC_REJECTION_NONE:
561 *val = 4800;
562 return 0;
563 case AD74413R_ADC_REJECTION_50_60_HART:
564 *val = 10;
565 return 0;
566 case AD74413R_ADC_REJECTION_HART:
567 *val = 1200;
568 return 0;
569 default:
570 dev_err(st->dev, "ADC rejection invalid\n");
571 return -EINVAL;
572 }
573 }
574
ad74413r_rate_to_rejection(struct ad74413r_state * st,int rate,unsigned int * val)575 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
576 int rate, unsigned int *val)
577 {
578 switch (rate) {
579 case 20:
580 *val = AD74413R_ADC_REJECTION_50_60;
581 return 0;
582 case 4800:
583 *val = AD74413R_ADC_REJECTION_NONE;
584 return 0;
585 case 10:
586 *val = AD74413R_ADC_REJECTION_50_60_HART;
587 return 0;
588 case 1200:
589 *val = AD74413R_ADC_REJECTION_HART;
590 return 0;
591 default:
592 dev_err(st->dev, "ADC rate invalid\n");
593 return -EINVAL;
594 }
595 }
596
ad74413r_range_to_voltage_range(struct ad74413r_state * st,unsigned int range,int * val)597 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
598 unsigned int range, int *val)
599 {
600 switch (range) {
601 case AD74413R_ADC_RANGE_10V:
602 *val = 10000;
603 return 0;
604 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
605 case AD74413R_ADC_RANGE_2P5V_INT_POW:
606 *val = 2500;
607 return 0;
608 case AD74413R_ADC_RANGE_5V_BI_DIR:
609 *val = 5000;
610 return 0;
611 default:
612 dev_err(st->dev, "ADC range invalid\n");
613 return -EINVAL;
614 }
615 }
616
ad74413r_range_to_voltage_offset(struct ad74413r_state * st,unsigned int range,int * val)617 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
618 unsigned int range, int *val)
619 {
620 switch (range) {
621 case AD74413R_ADC_RANGE_10V:
622 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
623 *val = 0;
624 return 0;
625 case AD74413R_ADC_RANGE_2P5V_INT_POW:
626 case AD74413R_ADC_RANGE_5V_BI_DIR:
627 *val = -2500;
628 return 0;
629 default:
630 dev_err(st->dev, "ADC range invalid\n");
631 return -EINVAL;
632 }
633 }
634
ad74413r_range_to_voltage_offset_raw(struct ad74413r_state * st,unsigned int range,int * val)635 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
636 unsigned int range, int *val)
637 {
638 switch (range) {
639 case AD74413R_ADC_RANGE_10V:
640 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
641 *val = 0;
642 return 0;
643 case AD74413R_ADC_RANGE_2P5V_INT_POW:
644 *val = -((int)AD74413R_ADC_RESULT_MAX);
645 return 0;
646 case AD74413R_ADC_RANGE_5V_BI_DIR:
647 *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
648 return 0;
649 default:
650 dev_err(st->dev, "ADC range invalid\n");
651 return -EINVAL;
652 }
653 }
654
ad74413r_get_output_voltage_scale(struct ad74413r_state * st,int * val,int * val2)655 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
656 int *val, int *val2)
657 {
658 *val = AD74413R_DAC_VOLTAGE_MAX;
659 *val2 = AD74413R_DAC_CODE_MAX;
660
661 return IIO_VAL_FRACTIONAL;
662 }
663
ad74413r_get_output_current_scale(struct ad74413r_state * st,int * val,int * val2)664 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
665 int *val, int *val2)
666 {
667 *val = st->refin_reg_uv;
668 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
669
670 return IIO_VAL_FRACTIONAL;
671 }
672
ad74413r_get_input_voltage_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)673 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
674 unsigned int channel,
675 int *val, int *val2)
676 {
677 unsigned int range;
678 int ret;
679
680 ret = ad74413r_get_adc_range(st, channel, &range);
681 if (ret)
682 return ret;
683
684 ret = ad74413r_range_to_voltage_range(st, range, val);
685 if (ret)
686 return ret;
687
688 *val2 = AD74413R_ADC_RESULT_MAX;
689
690 return IIO_VAL_FRACTIONAL;
691 }
692
ad74413r_get_input_voltage_offset(struct ad74413r_state * st,unsigned int channel,int * val)693 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
694 unsigned int channel, int *val)
695 {
696 unsigned int range;
697 int ret;
698
699 ret = ad74413r_get_adc_range(st, channel, &range);
700 if (ret)
701 return ret;
702
703 ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
704 if (ret)
705 return ret;
706
707 return IIO_VAL_INT;
708 }
709
ad74413r_get_input_current_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)710 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
711 unsigned int channel, int *val,
712 int *val2)
713 {
714 unsigned int range;
715 int ret;
716
717 ret = ad74413r_get_adc_range(st, channel, &range);
718 if (ret)
719 return ret;
720
721 ret = ad74413r_range_to_voltage_range(st, range, val);
722 if (ret)
723 return ret;
724
725 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
726
727 return IIO_VAL_FRACTIONAL;
728 }
729
ad74413r_get_input_current_offset(struct ad74413r_state * st,unsigned int channel,int * val)730 static int ad74413r_get_input_current_offset(struct ad74413r_state *st,
731 unsigned int channel, int *val)
732 {
733 unsigned int range;
734 int voltage_range;
735 int voltage_offset;
736 int ret;
737
738 ret = ad74413r_get_adc_range(st, channel, &range);
739 if (ret)
740 return ret;
741
742 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
743 if (ret)
744 return ret;
745
746 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
747 if (ret)
748 return ret;
749
750 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range;
751
752 return IIO_VAL_INT;
753 }
754
ad74413r_get_adc_rate(struct ad74413r_state * st,unsigned int channel,int * val)755 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
756 unsigned int channel, int *val)
757 {
758 unsigned int rejection;
759 int ret;
760
761 ret = ad74413r_get_adc_rejection(st, channel, &rejection);
762 if (ret)
763 return ret;
764
765 ret = ad74413r_rejection_to_rate(st, rejection, val);
766 if (ret)
767 return ret;
768
769 return IIO_VAL_INT;
770 }
771
ad74413r_set_adc_rate(struct ad74413r_state * st,unsigned int channel,int val)772 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
773 unsigned int channel, int val)
774 {
775 unsigned int rejection;
776 int ret;
777
778 ret = ad74413r_rate_to_rejection(st, val, &rejection);
779 if (ret)
780 return ret;
781
782 return ad74413r_set_adc_rejection(st, channel, rejection);
783 }
784
ad74413r_trigger_handler(int irq,void * p)785 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
786 {
787 struct iio_poll_func *pf = p;
788 struct iio_dev *indio_dev = pf->indio_dev;
789 struct ad74413r_state *st = iio_priv(indio_dev);
790 u8 *rx_buf = st->adc_samples_buf.rx_buf;
791 unsigned int i;
792 int ret;
793
794 ret = spi_sync(st->spi, &st->adc_samples_msg);
795 if (ret)
796 goto out;
797
798 for (i = 0; i < st->adc_active_channels; i++)
799 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
800
801 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
802 iio_get_time_ns(indio_dev));
803
804 out:
805 iio_trigger_notify_done(indio_dev->trig);
806
807 return IRQ_HANDLED;
808 }
809
ad74413r_adc_data_interrupt(int irq,void * data)810 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
811 {
812 struct iio_dev *indio_dev = data;
813 struct ad74413r_state *st = iio_priv(indio_dev);
814
815 if (iio_buffer_enabled(indio_dev))
816 iio_trigger_poll(st->trig);
817 else
818 complete(&st->adc_data_completion);
819
820 return IRQ_HANDLED;
821 }
822
_ad74413r_get_single_adc_result(struct ad74413r_state * st,unsigned int channel,int * val)823 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
824 unsigned int channel, int *val)
825 {
826 unsigned int uval;
827 int ret;
828
829 reinit_completion(&st->adc_data_completion);
830
831 ret = ad74413r_set_adc_channel_enable(st, channel, true);
832 if (ret)
833 return ret;
834
835 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
836 if (ret)
837 return ret;
838
839 ret = wait_for_completion_timeout(&st->adc_data_completion,
840 msecs_to_jiffies(1000));
841 if (!ret) {
842 ret = -ETIMEDOUT;
843 return ret;
844 }
845
846 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
847 &uval);
848 if (ret)
849 return ret;
850
851 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
852 if (ret)
853 return ret;
854
855 ret = ad74413r_set_adc_channel_enable(st, channel, false);
856 if (ret)
857 return ret;
858
859 *val = uval;
860
861 return IIO_VAL_INT;
862 }
863
ad74413r_get_single_adc_result(struct iio_dev * indio_dev,unsigned int channel,int * val)864 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
865 unsigned int channel, int *val)
866 {
867 struct ad74413r_state *st = iio_priv(indio_dev);
868
869 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
870 guard(mutex)(&st->lock);
871 return _ad74413r_get_single_adc_result(st, channel, val);
872 }
873 unreachable();
874 }
875
ad74413r_adc_to_resistance_result(int adc_result,int * val)876 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
877 {
878 if (adc_result == AD74413R_ADC_RESULT_MAX)
879 adc_result = AD74413R_ADC_RESULT_MAX - 1;
880
881 *val = DIV_ROUND_CLOSEST(adc_result * 2100,
882 AD74413R_ADC_RESULT_MAX - adc_result);
883 }
884
ad74413r_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)885 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
886 const unsigned long *active_scan_mask)
887 {
888 struct ad74413r_state *st = iio_priv(indio_dev);
889 struct spi_transfer *xfer = st->adc_samples_xfer;
890 u8 *rx_buf = st->adc_samples_buf.rx_buf;
891 u8 *tx_buf = st->adc_samples_tx_buf;
892 unsigned int channel;
893 int ret = -EINVAL;
894
895 guard(mutex)(&st->lock);
896
897 spi_message_init(&st->adc_samples_msg);
898 st->adc_active_channels = 0;
899
900 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
901 ret = ad74413r_set_adc_channel_enable(st, channel, false);
902 if (ret)
903 return ret;
904 }
905
906 if (*active_scan_mask == 0)
907 return ret;
908
909 /*
910 * The read select register is used to select which register's value
911 * will be sent by the slave on the next SPI frame.
912 *
913 * Create an SPI message that, on each step, writes to the read select
914 * register to select the ADC result of the next enabled channel, and
915 * reads the ADC result of the previous enabled channel.
916 *
917 * Example:
918 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ]
919 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4]
920 */
921
922 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
923 ret = ad74413r_set_adc_channel_enable(st, channel, true);
924 if (ret)
925 return ret;
926
927 st->adc_active_channels++;
928
929 if (xfer == st->adc_samples_xfer)
930 xfer->rx_buf = NULL;
931 else
932 xfer->rx_buf = rx_buf;
933
934 xfer->tx_buf = tx_buf;
935 xfer->len = AD74413R_FRAME_SIZE;
936 xfer->cs_change = 1;
937
938 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
939 AD74413R_REG_ADC_RESULT_X(channel),
940 tx_buf);
941
942 spi_message_add_tail(xfer, &st->adc_samples_msg);
943
944 tx_buf += AD74413R_FRAME_SIZE;
945 if (xfer != st->adc_samples_xfer)
946 rx_buf += AD74413R_FRAME_SIZE;
947 xfer++;
948 }
949
950 xfer->rx_buf = rx_buf;
951 xfer->tx_buf = NULL;
952 xfer->len = AD74413R_FRAME_SIZE;
953 xfer->cs_change = 0;
954
955 spi_message_add_tail(xfer, &st->adc_samples_msg);
956 return 0;
957 }
958
ad74413r_buffer_postenable(struct iio_dev * indio_dev)959 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
960 {
961 struct ad74413r_state *st = iio_priv(indio_dev);
962
963 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
964 }
965
ad74413r_buffer_predisable(struct iio_dev * indio_dev)966 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
967 {
968 struct ad74413r_state *st = iio_priv(indio_dev);
969
970 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
971 }
972
ad74413r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)973 static int ad74413r_read_raw(struct iio_dev *indio_dev,
974 struct iio_chan_spec const *chan,
975 int *val, int *val2, long info)
976 {
977 struct ad74413r_state *st = iio_priv(indio_dev);
978
979 switch (info) {
980 case IIO_CHAN_INFO_SCALE:
981 switch (chan->type) {
982 case IIO_VOLTAGE:
983 if (chan->output)
984 return ad74413r_get_output_voltage_scale(st,
985 val, val2);
986 else
987 return ad74413r_get_input_voltage_scale(st,
988 chan->channel, val, val2);
989 case IIO_CURRENT:
990 if (chan->output)
991 return ad74413r_get_output_current_scale(st,
992 val, val2);
993 else
994 return ad74413r_get_input_current_scale(st,
995 chan->channel, val, val2);
996 default:
997 return -EINVAL;
998 }
999 case IIO_CHAN_INFO_OFFSET:
1000 switch (chan->type) {
1001 case IIO_VOLTAGE:
1002 return ad74413r_get_input_voltage_offset(st,
1003 chan->channel, val);
1004 case IIO_CURRENT:
1005 return ad74413r_get_input_current_offset(st,
1006 chan->channel, val);
1007 default:
1008 return -EINVAL;
1009 }
1010 case IIO_CHAN_INFO_RAW:
1011 if (chan->output)
1012 return -EINVAL;
1013
1014 return ad74413r_get_single_adc_result(indio_dev, chan->channel,
1015 val);
1016 case IIO_CHAN_INFO_PROCESSED: {
1017 int ret;
1018
1019 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
1020 val);
1021 if (ret < 0)
1022 return ret;
1023
1024 ad74413r_adc_to_resistance_result(*val, val);
1025
1026 return ret;
1027 }
1028 case IIO_CHAN_INFO_SAMP_FREQ:
1029 return ad74413r_get_adc_rate(st, chan->channel, val);
1030 default:
1031 return -EINVAL;
1032 }
1033 }
1034
ad74413r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1035 static int ad74413r_write_raw(struct iio_dev *indio_dev,
1036 struct iio_chan_spec const *chan,
1037 int val, int val2, long info)
1038 {
1039 struct ad74413r_state *st = iio_priv(indio_dev);
1040
1041 switch (info) {
1042 case IIO_CHAN_INFO_RAW:
1043 if (!chan->output)
1044 return -EINVAL;
1045
1046 if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1047 dev_err(st->dev, "Invalid DAC code\n");
1048 return -EINVAL;
1049 }
1050
1051 return ad74413r_set_channel_dac_code(st, chan->channel, val);
1052 case IIO_CHAN_INFO_SAMP_FREQ:
1053 return ad74413r_set_adc_rate(st, chan->channel, val);
1054 default:
1055 return -EINVAL;
1056 }
1057 }
1058
ad74413r_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1059 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1060 struct iio_chan_spec const *chan,
1061 const int **vals, int *type, int *length,
1062 long info)
1063 {
1064 struct ad74413r_state *st = iio_priv(indio_dev);
1065
1066 switch (info) {
1067 case IIO_CHAN_INFO_SAMP_FREQ:
1068 if (st->chip_info->hart_support) {
1069 *vals = ad74413r_adc_sampling_rates_hart;
1070 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1071 } else {
1072 *vals = ad74413r_adc_sampling_rates;
1073 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1074 }
1075 *type = IIO_VAL_INT;
1076 return IIO_AVAIL_LIST;
1077 default:
1078 return -EINVAL;
1079 }
1080 }
1081
1082 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1083 .postenable = &ad74413r_buffer_postenable,
1084 .predisable = &ad74413r_buffer_predisable,
1085 };
1086
1087 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1088 .validate_device = iio_trigger_validate_own_device,
1089 };
1090
1091 static const struct iio_info ad74413r_info = {
1092 .read_raw = &ad74413r_read_raw,
1093 .write_raw = &ad74413r_write_raw,
1094 .read_avail = &ad74413r_read_avail,
1095 .update_scan_mode = &ad74413r_update_scan_mode,
1096 };
1097
1098 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \
1099 { \
1100 .type = (_type), \
1101 .indexed = 1, \
1102 .output = 1, \
1103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1104 | (extra_mask_separate), \
1105 }
1106
1107 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \
1108 { \
1109 .type = (_type), \
1110 .indexed = 1, \
1111 .output = 0, \
1112 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1113 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
1114 | (extra_mask_separate), \
1115 .info_mask_separate_available = \
1116 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1117 .scan_type = { \
1118 .sign = 'u', \
1119 .realbits = 16, \
1120 .storagebits = 32, \
1121 .shift = 8, \
1122 .endianness = IIO_BE, \
1123 }, \
1124 }
1125
1126 #define AD74413R_ADC_VOLTAGE_CHANNEL \
1127 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \
1128 | BIT(IIO_CHAN_INFO_OFFSET))
1129
1130 #define AD74413R_ADC_CURRENT_CHANNEL \
1131 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \
1132 | BIT(IIO_CHAN_INFO_OFFSET))
1133
1134 static const struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1135 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1136 AD74413R_ADC_CURRENT_CHANNEL,
1137 };
1138
1139 static const struct iio_chan_spec ad74413r_current_output_channels[] = {
1140 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1141 AD74413R_ADC_VOLTAGE_CHANNEL,
1142 };
1143
1144 static const struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1145 AD74413R_ADC_VOLTAGE_CHANNEL,
1146 };
1147
1148 static const struct iio_chan_spec ad74413r_current_input_channels[] = {
1149 AD74413R_ADC_CURRENT_CHANNEL,
1150 };
1151
1152 static const struct iio_chan_spec ad74413r_current_input_loop_channels[] = {
1153 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1154 AD74413R_ADC_CURRENT_CHANNEL,
1155 };
1156
1157 static const struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1158 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1159 };
1160
1161 static const struct iio_chan_spec ad74413r_digital_input_channels[] = {
1162 AD74413R_ADC_VOLTAGE_CHANNEL,
1163 };
1164
1165 #define _AD74413R_CHANNELS(_channels) \
1166 { \
1167 .channels = _channels, \
1168 .num_channels = ARRAY_SIZE(_channels), \
1169 }
1170
1171 #define AD74413R_CHANNELS(name) \
1172 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1173
1174 static const struct ad74413r_channels ad74413r_channels_map[] = {
1175 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1176 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1177 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1178 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1179 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1180 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop),
1181 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1182 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1183 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1184 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1185 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1186 };
1187
ad74413r_parse_channel_config(struct iio_dev * indio_dev,struct fwnode_handle * channel_node)1188 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1189 struct fwnode_handle *channel_node)
1190 {
1191 struct ad74413r_state *st = iio_priv(indio_dev);
1192 struct ad74413r_channel_config *config;
1193 u32 index;
1194 int ret;
1195
1196 ret = fwnode_property_read_u32(channel_node, "reg", &index);
1197 if (ret) {
1198 dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1199 return ret;
1200 }
1201
1202 if (index >= AD74413R_CHANNEL_MAX) {
1203 dev_err(st->dev, "Channel index %u is too large\n", index);
1204 return -EINVAL;
1205 }
1206
1207 config = &st->channel_configs[index];
1208 if (config->initialized) {
1209 dev_err(st->dev, "Channel %u already initialized\n", index);
1210 return -EINVAL;
1211 }
1212
1213 config->func = CH_FUNC_HIGH_IMPEDANCE;
1214 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1215
1216 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1217 dev_err(st->dev, "Invalid channel function %u\n", config->func);
1218 return -EINVAL;
1219 }
1220
1221 if (!st->chip_info->hart_support &&
1222 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1223 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1224 dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1225 return -EINVAL;
1226 }
1227
1228 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1229 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1230 st->num_comparator_gpios++;
1231
1232 config->gpo_comparator = fwnode_property_read_bool(channel_node,
1233 "adi,gpo-comparator");
1234
1235 fwnode_property_read_u32(channel_node, "drive-strength-microamp",
1236 &config->drive_strength);
1237
1238 if (!config->gpo_comparator)
1239 st->num_gpo_gpios++;
1240
1241 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1242
1243 config->initialized = true;
1244
1245 return 0;
1246 }
1247
ad74413r_parse_channel_configs(struct iio_dev * indio_dev)1248 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1249 {
1250 struct ad74413r_state *st = iio_priv(indio_dev);
1251 int ret;
1252
1253 device_for_each_child_node_scoped(st->dev, channel_node) {
1254 ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1255 if (ret)
1256 return ret;
1257 }
1258
1259 return 0;
1260 }
1261
ad74413r_setup_channels(struct iio_dev * indio_dev)1262 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1263 {
1264 struct ad74413r_state *st = iio_priv(indio_dev);
1265 struct ad74413r_channel_config *config;
1266 const struct iio_chan_spec *chans;
1267 struct iio_chan_spec *channels;
1268 unsigned int i, num_chans, chan_i;
1269 int ret;
1270
1271 channels = devm_kcalloc(st->dev, sizeof(*channels),
1272 indio_dev->num_channels, GFP_KERNEL);
1273 if (!channels)
1274 return -ENOMEM;
1275
1276 indio_dev->channels = channels;
1277
1278 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1279 config = &st->channel_configs[i];
1280 chans = ad74413r_channels_map[config->func].channels;
1281 num_chans = ad74413r_channels_map[config->func].num_channels;
1282
1283 memcpy(channels, chans, num_chans * sizeof(*chans));
1284
1285 for (chan_i = 0; chan_i < num_chans; chan_i++) {
1286 struct iio_chan_spec *chan = &channels[chan_i];
1287
1288 chan->channel = i;
1289 if (chan->output)
1290 chan->scan_index = -1;
1291 else
1292 chan->scan_index = i;
1293 }
1294
1295 ret = ad74413r_set_channel_function(st, i, config->func);
1296 if (ret)
1297 return ret;
1298
1299 channels += num_chans;
1300 }
1301
1302 return 0;
1303 }
1304
ad74413r_setup_gpios(struct ad74413r_state * st)1305 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1306 {
1307 struct ad74413r_channel_config *config;
1308 unsigned int comp_gpio_i = 0;
1309 unsigned int gpo_gpio_i = 0;
1310 unsigned int i;
1311 u8 gpo_config;
1312 u32 strength;
1313 int ret;
1314
1315 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1316 config = &st->channel_configs[i];
1317
1318 if (config->gpo_comparator) {
1319 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1320 } else {
1321 gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1322 st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1323 }
1324
1325 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1326 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1327 st->comp_gpio_offsets[comp_gpio_i++] = i;
1328
1329 strength = config->drive_strength;
1330 ret = ad74413r_set_comp_drive_strength(st, i, strength);
1331 if (ret)
1332 return ret;
1333 }
1334
1335 ret = ad74413r_set_gpo_config(st, i, gpo_config);
1336 if (ret)
1337 return ret;
1338 }
1339
1340 return 0;
1341 }
1342
ad74413r_probe(struct spi_device * spi)1343 static int ad74413r_probe(struct spi_device *spi)
1344 {
1345 struct ad74413r_state *st;
1346 struct iio_dev *indio_dev;
1347 int ret;
1348
1349 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1350 if (!indio_dev)
1351 return -ENOMEM;
1352
1353 st = iio_priv(indio_dev);
1354
1355 st->spi = spi;
1356 st->dev = &spi->dev;
1357 st->chip_info = spi_get_device_match_data(spi);
1358 if (!st->chip_info)
1359 return -EINVAL;
1360
1361 ret = devm_mutex_init(st->dev, &st->lock);
1362 if (ret)
1363 return ret;
1364
1365 init_completion(&st->adc_data_completion);
1366
1367 st->regmap = devm_regmap_init(st->dev, NULL, st,
1368 &ad74413r_regmap_config);
1369 if (IS_ERR(st->regmap))
1370 return PTR_ERR(st->regmap);
1371
1372 ret = devm_regulator_get_enable_read_voltage(st->dev, "refin");
1373 if (ret < 0)
1374 return dev_err_probe(st->dev, ret,
1375 "Failed to get refin regulator voltage\n");
1376 st->refin_reg_uv = ret;
1377
1378 st->sense_resistor_ohms = 100000000;
1379 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1380 &st->sense_resistor_ohms);
1381 st->sense_resistor_ohms /= 1000000;
1382
1383 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1384 st->chip_info->name, iio_device_id(indio_dev));
1385 if (!st->trig)
1386 return -ENOMEM;
1387
1388 st->trig->ops = &ad74413r_trigger_ops;
1389 iio_trigger_set_drvdata(st->trig, st);
1390
1391 ret = devm_iio_trigger_register(st->dev, st->trig);
1392 if (ret)
1393 return ret;
1394
1395 indio_dev->name = st->chip_info->name;
1396 indio_dev->modes = INDIO_DIRECT_MODE;
1397 indio_dev->info = &ad74413r_info;
1398 indio_dev->trig = iio_trigger_get(st->trig);
1399
1400 ret = ad74413r_reset(st);
1401 if (ret)
1402 return ret;
1403
1404 ret = ad74413r_parse_channel_configs(indio_dev);
1405 if (ret)
1406 return ret;
1407
1408 ret = ad74413r_setup_channels(indio_dev);
1409 if (ret)
1410 return ret;
1411
1412 ret = ad74413r_setup_gpios(st);
1413 if (ret)
1414 return ret;
1415
1416 if (st->num_gpo_gpios) {
1417 st->gpo_gpiochip.owner = THIS_MODULE;
1418 st->gpo_gpiochip.label = st->chip_info->name;
1419 st->gpo_gpiochip.base = -1;
1420 st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1421 st->gpo_gpiochip.parent = st->dev;
1422 st->gpo_gpiochip.can_sleep = true;
1423 st->gpo_gpiochip.set = ad74413r_gpio_set;
1424 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1425 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1426 st->gpo_gpiochip.get_direction =
1427 ad74413r_gpio_get_gpo_direction;
1428
1429 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1430 if (ret)
1431 return ret;
1432 }
1433
1434 if (st->num_comparator_gpios) {
1435 st->comp_gpiochip.owner = THIS_MODULE;
1436 st->comp_gpiochip.label = st->chip_info->name;
1437 st->comp_gpiochip.base = -1;
1438 st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1439 st->comp_gpiochip.parent = st->dev;
1440 st->comp_gpiochip.can_sleep = true;
1441 st->comp_gpiochip.get = ad74413r_gpio_get;
1442 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1443 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1444 st->comp_gpiochip.get_direction =
1445 ad74413r_gpio_get_comp_direction;
1446
1447 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1448 if (ret)
1449 return ret;
1450 }
1451
1452 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1453 if (ret)
1454 return ret;
1455
1456 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1457 0, st->chip_info->name, indio_dev);
1458 if (ret)
1459 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1460
1461 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1462 &iio_pollfunc_store_time,
1463 &ad74413r_trigger_handler,
1464 &ad74413r_buffer_ops);
1465 if (ret)
1466 return ret;
1467
1468 return devm_iio_device_register(st->dev, indio_dev);
1469 }
1470
ad74413r_unregister_driver(struct spi_driver * spi)1471 static int ad74413r_unregister_driver(struct spi_driver *spi)
1472 {
1473 spi_unregister_driver(spi);
1474
1475 return 0;
1476 }
1477
ad74413r_register_driver(struct spi_driver * spi)1478 static int __init ad74413r_register_driver(struct spi_driver *spi)
1479 {
1480 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1481
1482 return spi_register_driver(spi);
1483 }
1484
1485 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1486 .hart_support = false,
1487 .name = "ad74412r",
1488 };
1489
1490 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1491 .hart_support = true,
1492 .name = "ad74413r",
1493 };
1494
1495 static const struct of_device_id ad74413r_dt_id[] = {
1496 {
1497 .compatible = "adi,ad74412r",
1498 .data = &ad74412r_chip_info_data,
1499 },
1500 {
1501 .compatible = "adi,ad74413r",
1502 .data = &ad74413r_chip_info_data,
1503 },
1504 {},
1505 };
1506 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1507
1508 static const struct spi_device_id ad74413r_spi_id[] = {
1509 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data },
1510 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data },
1511 {}
1512 };
1513 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id);
1514
1515 static struct spi_driver ad74413r_driver = {
1516 .driver = {
1517 .name = "ad74413r",
1518 .of_match_table = ad74413r_dt_id,
1519 },
1520 .probe = ad74413r_probe,
1521 .id_table = ad74413r_spi_id,
1522 };
1523
1524 module_driver(ad74413r_driver,
1525 ad74413r_register_driver,
1526 ad74413r_unregister_driver);
1527
1528 MODULE_AUTHOR("Cosmin Tanislav <[email protected]>");
1529 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1530 MODULE_LICENSE("GPL v2");
1531