1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7192 and similar SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/sysfs.h>
16 #include <linux/spi/spi.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/err.h>
19 #include <linux/sched.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/units.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/trigger.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/adc/ad_sigma_delta.h>
33
34 /* Registers */
35 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
36 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
38 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
39 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
40 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
41 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
42 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
43 /* (AD7792)/24-bit (AD7192)) */
44 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
45 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
46
47 /* Communications Register Bit Designations (AD7192_REG_COMM) */
48 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
49 #define AD7192_COMM_WRITE 0 /* Write Operation */
50 #define AD7192_COMM_READ BIT(6) /* Read Operation */
51 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */
52 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
53
54 /* Status Register Bit Designations (AD7192_REG_STAT) */
55 #define AD7192_STAT_RDY BIT(7) /* Ready */
56 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
57 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
58 #define AD7192_STAT_PARITY BIT(4) /* Parity */
59 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
60 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
61 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
62
63 /* Mode Register Bit Designations (AD7192_REG_MODE) */
64 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */
65 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
66 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */
67 #define AD7192_MODE_AVG_MASK GENMASK(17, 16)
68 /* Fast Settling Filter Average Select Mask (AD7193 only) */
69 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
70 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
71 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
72 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
73 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
74 /* Filter Update Rate Select Mask */
75 #define AD7192_MODE_RATE_MASK GENMASK(9, 0)
76
77 /* Mode Register: AD7192_MODE_SEL options */
78 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
79 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
80 #define AD7192_MODE_IDLE 2 /* Idle Mode */
81 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
82 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
83 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
84 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
85 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
86
87 /* Mode Register: AD7192_MODE_CLKSRC options */
88 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
89 /* from MCLK1 to MCLK2 */
90 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
91 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
92 /* available at the MCLK2 pin */
93 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
94 /* at the MCLK2 pin */
95
96 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
97
98 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
99 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
100 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
101 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */
102 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
103 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
104 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
105 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
106 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */
107
108 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
110 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
111 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
112 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
113 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
114 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
115 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
116
117 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
118 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
119 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
120 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
121 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
122 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
123 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
124 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
125 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
126 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
127 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
128 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
129 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
130 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
131 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
132
133 #define AD7194_CH_POS(x) (((x) - 1) << 4)
134 #define AD7194_CH_NEG(x) ((x) - 1)
135
136 /* 10th bit corresponds to CON18(Pseudo) */
137 #define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p))
138
139 #define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n))
140 #define AD7194_CH_TEMP 0x100
141 #define AD7194_CH_BASE_NR 2
142 #define AD7194_CH_AIN_START 1
143 #define AD7194_CH_AIN_NR 16
144 #define AD7194_CH_MAX_NR 272
145
146 /* ID Register Bit Designations (AD7192_REG_ID) */
147 #define CHIPID_AD7190 0x4
148 #define CHIPID_AD7192 0x0
149 #define CHIPID_AD7193 0x2
150 #define CHIPID_AD7194 0x3
151 #define CHIPID_AD7195 0x6
152 #define AD7192_ID_MASK GENMASK(3, 0)
153
154 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
155 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
156 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
157 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
158 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
159 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
160 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
161 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
162
163 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
164 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
165 #define AD7192_INT_FREQ_MHZ 4915200
166
167 #define AD7192_NO_SYNC_FILTER 1
168 #define AD7192_SYNC3_FILTER 3
169 #define AD7192_SYNC4_FILTER 4
170
171 /* NOTE:
172 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
173 * In order to avoid contentions on the SPI bus, it's therefore necessary
174 * to use spi bus locking.
175 *
176 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
177 */
178
179 enum {
180 AD7192_SYSCALIB_ZERO_SCALE,
181 AD7192_SYSCALIB_FULL_SCALE,
182 };
183
184 enum {
185 ID_AD7190,
186 ID_AD7192,
187 ID_AD7193,
188 ID_AD7194,
189 ID_AD7195,
190 };
191
192 struct ad7192_chip_info {
193 unsigned int chip_id;
194 const char *name;
195 const struct iio_chan_spec *channels;
196 u8 num_channels;
197 const struct ad_sigma_delta_info *sigma_delta_info;
198 const struct iio_info *info;
199 int (*parse_channels)(struct iio_dev *indio_dev);
200 };
201
202 struct ad7192_state {
203 const struct ad7192_chip_info *chip_info;
204 struct clk *mclk;
205 struct clk_hw int_clk_hw;
206 u16 int_vref_mv;
207 u32 aincom_mv;
208 u32 fclk;
209 u32 mode;
210 u32 conf;
211 u32 scale_avail[8][2];
212 u32 filter_freq_avail[4][2];
213 u32 oversampling_ratio_avail[4];
214 u8 gpocon;
215 u8 clock_sel;
216 struct mutex lock; /* protect sensor state */
217 u8 syscalib_mode[8];
218
219 struct ad_sigma_delta sd;
220 };
221
222 static const char * const ad7192_syscalib_modes[] = {
223 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
224 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
225 };
226
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)227 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
228 const struct iio_chan_spec *chan,
229 unsigned int mode)
230 {
231 struct ad7192_state *st = iio_priv(indio_dev);
232
233 st->syscalib_mode[chan->channel] = mode;
234
235 return 0;
236 }
237
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)238 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
239 const struct iio_chan_spec *chan)
240 {
241 struct ad7192_state *st = iio_priv(indio_dev);
242
243 return st->syscalib_mode[chan->channel];
244 }
245
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)246 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
247 uintptr_t private,
248 const struct iio_chan_spec *chan,
249 const char *buf, size_t len)
250 {
251 struct ad7192_state *st = iio_priv(indio_dev);
252 bool sys_calib;
253 int ret, temp;
254
255 ret = kstrtobool(buf, &sys_calib);
256 if (ret)
257 return ret;
258
259 if (!iio_device_claim_direct(indio_dev))
260 return -EBUSY;
261
262 temp = st->syscalib_mode[chan->channel];
263 if (sys_calib) {
264 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
266 chan->address);
267 else
268 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
269 chan->address);
270 }
271
272 iio_device_release_direct(indio_dev);
273
274 return ret ? ret : len;
275 }
276
277 static const struct iio_enum ad7192_syscalib_mode_enum = {
278 .items = ad7192_syscalib_modes,
279 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
280 .set = ad7192_set_syscalib_mode,
281 .get = ad7192_get_syscalib_mode
282 };
283
284 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
285 {
286 .name = "sys_calibration",
287 .write = ad7192_write_syscalib,
288 .shared = IIO_SEPARATE,
289 },
290 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
291 &ad7192_syscalib_mode_enum),
292 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
293 &ad7192_syscalib_mode_enum),
294 { }
295 };
296
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)297 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
298 {
299 return container_of(sd, struct ad7192_state, sd);
300 }
301
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)302 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
303 {
304 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
305
306 st->conf &= ~AD7192_CONF_CHAN_MASK;
307 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);
308
309 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
310 }
311
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)312 static int ad7192_set_mode(struct ad_sigma_delta *sd,
313 enum ad_sigma_delta_mode mode)
314 {
315 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
316
317 st->mode &= ~AD7192_MODE_SEL_MASK;
318 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);
319
320 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
321 }
322
ad7192_append_status(struct ad_sigma_delta * sd,bool append)323 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
324 {
325 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
326 unsigned int mode = st->mode;
327 int ret;
328
329 mode &= ~AD7192_MODE_STA_MASK;
330 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);
331
332 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
333 if (ret < 0)
334 return ret;
335
336 st->mode = mode;
337
338 return 0;
339 }
340
ad7192_disable_all(struct ad_sigma_delta * sd)341 static int ad7192_disable_all(struct ad_sigma_delta *sd)
342 {
343 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
344 u32 conf = st->conf;
345 int ret;
346
347 conf &= ~AD7192_CONF_CHAN_MASK;
348
349 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
350 if (ret < 0)
351 return ret;
352
353 st->conf = conf;
354
355 return 0;
356 }
357
358 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
359 .set_channel = ad7192_set_channel,
360 .append_status = ad7192_append_status,
361 .disable_all = ad7192_disable_all,
362 .set_mode = ad7192_set_mode,
363 .has_registers = true,
364 .addr_shift = 3,
365 .read_mask = BIT(6),
366 .status_ch_mask = GENMASK(3, 0),
367 .num_slots = 4,
368 .irq_flags = IRQF_TRIGGER_FALLING,
369 .num_resetclks = 40,
370 };
371
372 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = {
373 .set_channel = ad7192_set_channel,
374 .append_status = ad7192_append_status,
375 .disable_all = ad7192_disable_all,
376 .set_mode = ad7192_set_mode,
377 .has_registers = true,
378 .addr_shift = 3,
379 .read_mask = BIT(6),
380 .status_ch_mask = GENMASK(3, 0),
381 .irq_flags = IRQF_TRIGGER_FALLING,
382 .num_resetclks = 40,
383 };
384
385 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
386 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
387 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
388 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
389 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
390 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
391 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
392 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
393 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
394 };
395
ad7192_calibrate_all(struct ad7192_state * st)396 static int ad7192_calibrate_all(struct ad7192_state *st)
397 {
398 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
399 ARRAY_SIZE(ad7192_calib_arr));
400 }
401
ad7192_valid_external_frequency(u32 freq)402 static inline bool ad7192_valid_external_frequency(u32 freq)
403 {
404 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
405 freq <= AD7192_EXT_FREQ_MHZ_MAX);
406 }
407
408 /*
409 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source
410 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to
411 * AD7192_CLK_EXT_MCLK2
412 */
413 static const char *const ad7192_clock_names[] = {
414 "xtal",
415 "mclk"
416 };
417
clk_hw_to_ad7192(struct clk_hw * hw)418 static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw)
419 {
420 return container_of(hw, struct ad7192_state, int_clk_hw);
421 }
422
ad7192_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)423 static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw,
424 unsigned long parent_rate)
425 {
426 return AD7192_INT_FREQ_MHZ;
427 }
428
ad7192_clk_output_is_enabled(struct clk_hw * hw)429 static int ad7192_clk_output_is_enabled(struct clk_hw *hw)
430 {
431 struct ad7192_state *st = clk_hw_to_ad7192(hw);
432
433 return st->clock_sel == AD7192_CLK_INT_CO;
434 }
435
ad7192_clk_prepare(struct clk_hw * hw)436 static int ad7192_clk_prepare(struct clk_hw *hw)
437 {
438 struct ad7192_state *st = clk_hw_to_ad7192(hw);
439 int ret;
440
441 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
442 st->mode |= AD7192_CLK_INT_CO;
443
444 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
445 if (ret)
446 return ret;
447
448 st->clock_sel = AD7192_CLK_INT_CO;
449
450 return 0;
451 }
452
ad7192_clk_unprepare(struct clk_hw * hw)453 static void ad7192_clk_unprepare(struct clk_hw *hw)
454 {
455 struct ad7192_state *st = clk_hw_to_ad7192(hw);
456 int ret;
457
458 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
459 st->mode |= AD7192_CLK_INT;
460
461 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
462 if (ret)
463 return;
464
465 st->clock_sel = AD7192_CLK_INT;
466 }
467
468 static const struct clk_ops ad7192_int_clk_ops = {
469 .recalc_rate = ad7192_clk_recalc_rate,
470 .is_enabled = ad7192_clk_output_is_enabled,
471 .prepare = ad7192_clk_prepare,
472 .unprepare = ad7192_clk_unprepare,
473 };
474
ad7192_register_clk_provider(struct ad7192_state * st)475 static int ad7192_register_clk_provider(struct ad7192_state *st)
476 {
477 struct device *dev = &st->sd.spi->dev;
478 struct clk_init_data init = {};
479 int ret;
480
481 if (!IS_ENABLED(CONFIG_COMMON_CLK))
482 return 0;
483
484 if (!device_property_present(dev, "#clock-cells"))
485 return 0;
486
487 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
488 fwnode_get_name(dev_fwnode(dev)));
489 if (!init.name)
490 return -ENOMEM;
491
492 init.ops = &ad7192_int_clk_ops;
493
494 st->int_clk_hw.init = &init;
495 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
496 if (ret)
497 return ret;
498
499 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
500 &st->int_clk_hw);
501 }
502
ad7192_clock_setup(struct ad7192_state * st)503 static int ad7192_clock_setup(struct ad7192_state *st)
504 {
505 struct device *dev = &st->sd.spi->dev;
506 int ret;
507
508 /*
509 * The following two if branches are kept for backward compatibility but
510 * the use of the two devicetree properties is highly discouraged. Clock
511 * configuration should be done according to the bindings.
512 */
513
514 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) {
515 st->clock_sel = AD7192_CLK_INT_CO;
516 st->fclk = AD7192_INT_FREQ_MHZ;
517 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n");
518 return 0;
519 }
520
521 if (device_property_read_bool(dev, "adi,clock-xtal")) {
522 st->clock_sel = AD7192_CLK_EXT_MCLK1_2;
523 st->mclk = devm_clk_get_enabled(dev, "mclk");
524 if (IS_ERR(st->mclk))
525 return dev_err_probe(dev, PTR_ERR(st->mclk),
526 "Failed to get mclk\n");
527
528 st->fclk = clk_get_rate(st->mclk);
529 if (!ad7192_valid_external_frequency(st->fclk))
530 return dev_err_probe(dev, -EINVAL,
531 "External clock frequency out of bounds\n");
532
533 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n");
534 return 0;
535 }
536
537 ret = device_property_match_property_string(dev, "clock-names",
538 ad7192_clock_names,
539 ARRAY_SIZE(ad7192_clock_names));
540 if (ret < 0) {
541 st->clock_sel = AD7192_CLK_INT;
542 st->fclk = AD7192_INT_FREQ_MHZ;
543
544 ret = ad7192_register_clk_provider(st);
545 if (ret)
546 return dev_err_probe(dev, ret,
547 "Failed to register clock provider\n");
548 return 0;
549 }
550
551 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;
552
553 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);
554 if (IS_ERR(st->mclk))
555 return dev_err_probe(dev, PTR_ERR(st->mclk),
556 "Failed to get clock source\n");
557
558 st->fclk = clk_get_rate(st->mclk);
559 if (!ad7192_valid_external_frequency(st->fclk))
560 return dev_err_probe(dev, -EINVAL,
561 "External clock frequency out of bounds\n");
562
563 return 0;
564 }
565
ad7192_setup(struct iio_dev * indio_dev,struct device * dev)566 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)
567 {
568 struct ad7192_state *st = iio_priv(indio_dev);
569 bool rej60_en, refin2_en;
570 bool buf_en, bipolar, burnout_curr_en;
571 unsigned long long scale_uv;
572 int i, ret, id;
573
574 /* reset the serial interface */
575 ret = ad_sd_reset(&st->sd);
576 if (ret < 0)
577 return ret;
578 usleep_range(500, 1000); /* Wait for at least 500us */
579
580 /* write/read test for device presence */
581 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
582 if (ret)
583 return ret;
584
585 id = FIELD_GET(AD7192_ID_MASK, id);
586
587 if (id != st->chip_info->chip_id)
588 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",
589 id, st->chip_info->chip_id);
590
591 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |
592 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |
593 FIELD_PREP(AD7192_MODE_RATE_MASK, 480);
594
595 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);
596
597 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");
598 if (rej60_en)
599 st->mode |= AD7192_MODE_REJ60;
600
601 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");
602 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
603 st->conf |= AD7192_CONF_REFSEL;
604
605 st->conf &= ~AD7192_CONF_CHOP;
606
607 buf_en = device_property_read_bool(dev, "adi,buffer-enable");
608 if (buf_en)
609 st->conf |= AD7192_CONF_BUF;
610
611 bipolar = device_property_read_bool(dev, "bipolar");
612 if (!bipolar)
613 st->conf |= AD7192_CONF_UNIPOLAR;
614
615 burnout_curr_en = device_property_read_bool(dev,
616 "adi,burnout-currents-enable");
617 if (burnout_curr_en && buf_en) {
618 st->conf |= AD7192_CONF_BURN;
619 } else if (burnout_curr_en) {
620 dev_warn(dev,
621 "Can't enable burnout currents: see CHOP or buffer\n");
622 }
623
624 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
625 if (ret)
626 return ret;
627
628 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
629 if (ret)
630 return ret;
631
632 ret = ad7192_calibrate_all(st);
633 if (ret)
634 return ret;
635
636 /* Populate available ADC input ranges */
637 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
638 scale_uv = ((u64)st->int_vref_mv * 100000000)
639 >> (indio_dev->channels[0].scan_type.realbits -
640 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));
641 scale_uv >>= i;
642
643 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
644 st->scale_avail[i][0] = scale_uv;
645 }
646
647 st->oversampling_ratio_avail[0] = 1;
648 st->oversampling_ratio_avail[1] = 2;
649 st->oversampling_ratio_avail[2] = 8;
650 st->oversampling_ratio_avail[3] = 16;
651
652 st->filter_freq_avail[0][0] = 600;
653 st->filter_freq_avail[1][0] = 800;
654 st->filter_freq_avail[2][0] = 2300;
655 st->filter_freq_avail[3][0] = 2720;
656
657 st->filter_freq_avail[0][1] = 1000;
658 st->filter_freq_avail[1][1] = 1000;
659 st->filter_freq_avail[2][1] = 1000;
660 st->filter_freq_avail[3][1] = 1000;
661
662 return 0;
663 }
664
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)665 static ssize_t ad7192_show_ac_excitation(struct device *dev,
666 struct device_attribute *attr,
667 char *buf)
668 {
669 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
670 struct ad7192_state *st = iio_priv(indio_dev);
671
672 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));
673 }
674
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)675 static ssize_t ad7192_show_bridge_switch(struct device *dev,
676 struct device_attribute *attr,
677 char *buf)
678 {
679 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
680 struct ad7192_state *st = iio_priv(indio_dev);
681
682 return sysfs_emit(buf, "%ld\n",
683 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));
684 }
685
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)686 static ssize_t ad7192_set(struct device *dev,
687 struct device_attribute *attr,
688 const char *buf,
689 size_t len)
690 {
691 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
692 struct ad7192_state *st = iio_priv(indio_dev);
693 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
694 int ret;
695 bool val;
696
697 ret = kstrtobool(buf, &val);
698 if (ret < 0)
699 return ret;
700
701 ret = iio_device_claim_direct_mode(indio_dev);
702 if (ret)
703 return ret;
704
705 switch ((u32)this_attr->address) {
706 case AD7192_REG_GPOCON:
707 if (val)
708 st->gpocon |= AD7192_GPOCON_BPDSW;
709 else
710 st->gpocon &= ~AD7192_GPOCON_BPDSW;
711
712 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
713 break;
714 case AD7192_REG_CONF:
715 if (val)
716 st->conf |= AD7192_CONF_ACX;
717 else
718 st->conf &= ~AD7192_CONF_ACX;
719
720 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
721 break;
722 default:
723 ret = -EINVAL;
724 }
725
726 iio_device_release_direct_mode(indio_dev);
727
728 return ret ? ret : len;
729 }
730
ad7192_compute_f_order(struct ad7192_state * st,bool sinc3_en,bool chop_en)731 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)
732 {
733 u8 avg_factor_selected, oversampling_ratio;
734
735 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);
736
737 if (!avg_factor_selected && !chop_en)
738 return 1;
739
740 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];
741
742 if (sinc3_en)
743 return AD7192_SYNC3_FILTER + oversampling_ratio - 1;
744
745 return AD7192_SYNC4_FILTER + oversampling_ratio - 1;
746 }
747
ad7192_get_f_order(struct ad7192_state * st)748 static int ad7192_get_f_order(struct ad7192_state *st)
749 {
750 bool sinc3_en, chop_en;
751
752 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);
753 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);
754
755 return ad7192_compute_f_order(st, sinc3_en, chop_en);
756 }
757
ad7192_compute_f_adc(struct ad7192_state * st,bool sinc3_en,bool chop_en)758 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,
759 bool chop_en)
760 {
761 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);
762
763 return DIV_ROUND_CLOSEST(st->fclk,
764 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
765 }
766
ad7192_get_f_adc(struct ad7192_state * st)767 static int ad7192_get_f_adc(struct ad7192_state *st)
768 {
769 unsigned int f_order = ad7192_get_f_order(st);
770
771 return DIV_ROUND_CLOSEST(st->fclk,
772 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
773 }
774
ad7192_update_filter_freq_avail(struct ad7192_state * st)775 static void ad7192_update_filter_freq_avail(struct ad7192_state *st)
776 {
777 unsigned int fadc;
778
779 /* Formulas for filter at page 25 of the datasheet */
780 fadc = ad7192_compute_f_adc(st, false, true);
781 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
782
783 fadc = ad7192_compute_f_adc(st, true, true);
784 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
785
786 fadc = ad7192_compute_f_adc(st, false, false);
787 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
788
789 fadc = ad7192_compute_f_adc(st, true, false);
790 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
791 }
792
793 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
794 ad7192_show_bridge_switch, ad7192_set,
795 AD7192_REG_GPOCON);
796
797 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
798 ad7192_show_ac_excitation, ad7192_set,
799 AD7192_REG_CONF);
800
801 static struct attribute *ad7192_attributes[] = {
802 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
803 NULL
804 };
805
806 static const struct attribute_group ad7192_attribute_group = {
807 .attrs = ad7192_attributes,
808 };
809
810 static struct attribute *ad7195_attributes[] = {
811 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
812 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
813 NULL
814 };
815
816 static const struct attribute_group ad7195_attribute_group = {
817 .attrs = ad7195_attributes,
818 };
819
ad7192_get_temp_scale(bool unipolar)820 static unsigned int ad7192_get_temp_scale(bool unipolar)
821 {
822 return unipolar ? 2815 * 2 : 2815;
823 }
824
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)825 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
826 int val, int val2)
827 {
828 int i, ret, freq;
829 unsigned int diff_new, diff_old;
830 int idx = 0;
831
832 diff_old = U32_MAX;
833 freq = val * 1000 + val2;
834
835 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {
836 diff_new = abs(freq - st->filter_freq_avail[i][0]);
837 if (diff_new < diff_old) {
838 diff_old = diff_new;
839 idx = i;
840 }
841 }
842
843 switch (idx) {
844 case 0:
845 st->mode &= ~AD7192_MODE_SINC3;
846
847 st->conf |= AD7192_CONF_CHOP;
848 break;
849 case 1:
850 st->mode |= AD7192_MODE_SINC3;
851
852 st->conf |= AD7192_CONF_CHOP;
853 break;
854 case 2:
855 st->mode &= ~AD7192_MODE_SINC3;
856
857 st->conf &= ~AD7192_CONF_CHOP;
858 break;
859 case 3:
860 st->mode |= AD7192_MODE_SINC3;
861
862 st->conf &= ~AD7192_CONF_CHOP;
863 break;
864 }
865
866 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
867 if (ret < 0)
868 return ret;
869
870 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
871 }
872
ad7192_get_3db_filter_freq(struct ad7192_state * st)873 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
874 {
875 unsigned int fadc;
876
877 fadc = ad7192_get_f_adc(st);
878
879 if (FIELD_GET(AD7192_CONF_CHOP, st->conf))
880 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
881 if (FIELD_GET(AD7192_MODE_SINC3, st->mode))
882 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
883 else
884 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
885 }
886
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)887 static int ad7192_read_raw(struct iio_dev *indio_dev,
888 struct iio_chan_spec const *chan,
889 int *val,
890 int *val2,
891 long m)
892 {
893 struct ad7192_state *st = iio_priv(indio_dev);
894 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);
895 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);
896
897 switch (m) {
898 case IIO_CHAN_INFO_RAW:
899 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
900 case IIO_CHAN_INFO_SCALE:
901 switch (chan->type) {
902 case IIO_VOLTAGE:
903 mutex_lock(&st->lock);
904 *val = st->scale_avail[gain][0];
905 *val2 = st->scale_avail[gain][1];
906 mutex_unlock(&st->lock);
907 return IIO_VAL_INT_PLUS_NANO;
908 case IIO_TEMP:
909 *val = 0;
910 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
911 return IIO_VAL_INT_PLUS_NANO;
912 default:
913 return -EINVAL;
914 }
915 case IIO_CHAN_INFO_OFFSET:
916 if (!unipolar)
917 *val = -(1 << (chan->scan_type.realbits - 1));
918 else
919 *val = 0;
920
921 switch (chan->type) {
922 case IIO_VOLTAGE:
923 /*
924 * Only applies to pseudo-differential inputs.
925 * AINCOM voltage has to be converted to "raw" units.
926 */
927 if (st->aincom_mv && !chan->differential)
928 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,
929 st->scale_avail[gain][1]);
930 return IIO_VAL_INT;
931 /* Kelvin to Celsius */
932 case IIO_TEMP:
933 *val -= 273 * ad7192_get_temp_scale(unipolar);
934 return IIO_VAL_INT;
935 default:
936 return -EINVAL;
937 }
938 case IIO_CHAN_INFO_SAMP_FREQ:
939 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);
940 return IIO_VAL_INT;
941 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
942 *val = ad7192_get_3db_filter_freq(st);
943 *val2 = 1000;
944 return IIO_VAL_FRACTIONAL;
945 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
946 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];
947 return IIO_VAL_INT;
948 }
949
950 return -EINVAL;
951 }
952
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)953 static int ad7192_write_raw(struct iio_dev *indio_dev,
954 struct iio_chan_spec const *chan,
955 int val,
956 int val2,
957 long mask)
958 {
959 struct ad7192_state *st = iio_priv(indio_dev);
960 int ret, i, div;
961 unsigned int tmp;
962
963 ret = iio_device_claim_direct_mode(indio_dev);
964 if (ret)
965 return ret;
966
967 mutex_lock(&st->lock);
968
969 switch (mask) {
970 case IIO_CHAN_INFO_SCALE:
971 ret = -EINVAL;
972 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
973 if (val2 == st->scale_avail[i][1]) {
974 ret = 0;
975 tmp = st->conf;
976 st->conf &= ~AD7192_CONF_GAIN_MASK;
977 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);
978 if (tmp == st->conf)
979 break;
980 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
981 3, st->conf);
982 ad7192_calibrate_all(st);
983 break;
984 }
985 break;
986 case IIO_CHAN_INFO_SAMP_FREQ:
987 if (!val) {
988 ret = -EINVAL;
989 break;
990 }
991
992 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
993 if (div < 1 || div > 1023) {
994 ret = -EINVAL;
995 break;
996 }
997
998 st->mode &= ~AD7192_MODE_RATE_MASK;
999 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);
1000 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
1001 ad7192_update_filter_freq_avail(st);
1002 break;
1003 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1004 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
1005 break;
1006 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1007 ret = -EINVAL;
1008 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)
1009 if (val == st->oversampling_ratio_avail[i]) {
1010 ret = 0;
1011 tmp = st->mode;
1012 st->mode &= ~AD7192_MODE_AVG_MASK;
1013 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);
1014 if (tmp == st->mode)
1015 break;
1016 ad_sd_write_reg(&st->sd, AD7192_REG_MODE,
1017 3, st->mode);
1018 break;
1019 }
1020 ad7192_update_filter_freq_avail(st);
1021 break;
1022 default:
1023 ret = -EINVAL;
1024 }
1025
1026 mutex_unlock(&st->lock);
1027
1028 iio_device_release_direct_mode(indio_dev);
1029
1030 return ret;
1031 }
1032
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1033 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
1034 struct iio_chan_spec const *chan,
1035 long mask)
1036 {
1037 switch (mask) {
1038 case IIO_CHAN_INFO_SCALE:
1039 return IIO_VAL_INT_PLUS_NANO;
1040 case IIO_CHAN_INFO_SAMP_FREQ:
1041 return IIO_VAL_INT;
1042 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1043 return IIO_VAL_INT_PLUS_MICRO;
1044 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1045 return IIO_VAL_INT;
1046 default:
1047 return -EINVAL;
1048 }
1049 }
1050
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1051 static int ad7192_read_avail(struct iio_dev *indio_dev,
1052 struct iio_chan_spec const *chan,
1053 const int **vals, int *type, int *length,
1054 long mask)
1055 {
1056 struct ad7192_state *st = iio_priv(indio_dev);
1057
1058 switch (mask) {
1059 case IIO_CHAN_INFO_SCALE:
1060 *vals = (int *)st->scale_avail;
1061 *type = IIO_VAL_INT_PLUS_NANO;
1062 /* Values are stored in a 2D matrix */
1063 *length = ARRAY_SIZE(st->scale_avail) * 2;
1064
1065 return IIO_AVAIL_LIST;
1066 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1067 *vals = (int *)st->filter_freq_avail;
1068 *type = IIO_VAL_FRACTIONAL;
1069 *length = ARRAY_SIZE(st->filter_freq_avail) * 2;
1070
1071 return IIO_AVAIL_LIST;
1072 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1073 *vals = (int *)st->oversampling_ratio_avail;
1074 *type = IIO_VAL_INT;
1075 *length = ARRAY_SIZE(st->oversampling_ratio_avail);
1076
1077 return IIO_AVAIL_LIST;
1078 }
1079
1080 return -EINVAL;
1081 }
1082
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1083 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
1084 {
1085 struct ad7192_state *st = iio_priv(indio_dev);
1086 u32 conf = st->conf;
1087 int ret;
1088 int i;
1089
1090 conf &= ~AD7192_CONF_CHAN_MASK;
1091 for_each_set_bit(i, scan_mask, 8)
1092 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, BIT(i));
1093
1094 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
1095 if (ret < 0)
1096 return ret;
1097
1098 st->conf = conf;
1099
1100 return 0;
1101 }
1102
1103 static const struct iio_info ad7192_info = {
1104 .read_raw = ad7192_read_raw,
1105 .write_raw = ad7192_write_raw,
1106 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1107 .read_avail = ad7192_read_avail,
1108 .attrs = &ad7192_attribute_group,
1109 .validate_trigger = ad_sd_validate_trigger,
1110 .update_scan_mode = ad7192_update_scan_mode,
1111 };
1112
1113 static const struct iio_info ad7194_info = {
1114 .read_raw = ad7192_read_raw,
1115 .write_raw = ad7192_write_raw,
1116 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1117 .read_avail = ad7192_read_avail,
1118 .validate_trigger = ad_sd_validate_trigger,
1119 };
1120
1121 static const struct iio_info ad7195_info = {
1122 .read_raw = ad7192_read_raw,
1123 .write_raw = ad7192_write_raw,
1124 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1125 .read_avail = ad7192_read_avail,
1126 .attrs = &ad7195_attribute_group,
1127 .validate_trigger = ad_sd_validate_trigger,
1128 .update_scan_mode = ad7192_update_scan_mode,
1129 };
1130
1131 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \
1132 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \
1133 { \
1134 .type = (_type), \
1135 .differential = ((_channel2) == -1 ? 0 : 1), \
1136 .indexed = 1, \
1137 .channel = (_channel1), \
1138 .channel2 = (_channel2), \
1139 .address = (_address), \
1140 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1141 BIT(IIO_CHAN_INFO_OFFSET), \
1142 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1143 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1144 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1145 (_mask_all), \
1146 .info_mask_shared_by_type_available = (_mask_type_av), \
1147 .info_mask_shared_by_all_available = \
1148 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1149 (_mask_all_av), \
1150 .ext_info = (_ext_info), \
1151 .scan_index = (_si), \
1152 .scan_type = { \
1153 .sign = 'u', \
1154 .realbits = 24, \
1155 .storagebits = 32, \
1156 .endianness = IIO_BE, \
1157 }, \
1158 }
1159
1160 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1161 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \
1162 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1163
1164 #define AD719x_CHANNEL(_si, _channel1, _address) \
1165 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1166 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1167
1168 #define AD719x_TEMP_CHANNEL(_si, _address) \
1169 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1170
1171 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1172 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \
1173 IIO_VOLTAGE, \
1174 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1175 BIT(IIO_CHAN_INFO_SCALE), \
1176 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1177 ad7192_calibsys_ext_info)
1178
1179 #define AD7193_CHANNEL(_si, _channel1, _address) \
1180 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1181
1182 static const struct iio_chan_spec ad7192_channels[] = {
1183 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1184 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1185 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
1186 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
1187 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1188 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
1189 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
1190 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
1191 IIO_CHAN_SOFT_TIMESTAMP(8),
1192 };
1193
1194 static const struct iio_chan_spec ad7193_channels[] = {
1195 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1196 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1197 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
1198 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
1199 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
1200 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
1201 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1202 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
1203 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
1204 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
1205 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
1206 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
1207 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
1208 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
1209 IIO_CHAN_SOFT_TIMESTAMP(14),
1210 };
1211
ad7194_validate_ain_channel(struct device * dev,u32 ain)1212 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain)
1213 {
1214 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR);
1215 }
1216
ad7194_parse_channels(struct iio_dev * indio_dev)1217 static int ad7194_parse_channels(struct iio_dev *indio_dev)
1218 {
1219 struct device *dev = indio_dev->dev.parent;
1220 struct iio_chan_spec *ad7194_channels;
1221 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0);
1222 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0);
1223 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0);
1224 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0);
1225 unsigned int num_channels, index = 0;
1226 u32 ain[2];
1227 int ret;
1228
1229 num_channels = device_get_child_node_count(dev);
1230 if (num_channels > AD7194_CH_MAX_NR)
1231 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
1232 num_channels);
1233
1234 num_channels += AD7194_CH_BASE_NR;
1235
1236 ad7194_channels = devm_kcalloc(dev, num_channels,
1237 sizeof(*ad7194_channels), GFP_KERNEL);
1238 if (!ad7194_channels)
1239 return -ENOMEM;
1240
1241 indio_dev->channels = ad7194_channels;
1242 indio_dev->num_channels = num_channels;
1243
1244 device_for_each_child_node_scoped(dev, child) {
1245 ret = fwnode_property_read_u32_array(child, "diff-channels",
1246 ain, ARRAY_SIZE(ain));
1247 if (ret == 0) {
1248 if (!ad7194_validate_ain_channel(dev, ain[0]))
1249 return dev_err_probe(dev, -EINVAL,
1250 "Invalid AIN channel: %u\n",
1251 ain[0]);
1252
1253 if (!ad7194_validate_ain_channel(dev, ain[1]))
1254 return dev_err_probe(dev, -EINVAL,
1255 "Invalid AIN channel: %u\n",
1256 ain[1]);
1257
1258 *ad7194_channels = ad7194_chan_diff;
1259 ad7194_channels->scan_index = index++;
1260 ad7194_channels->channel = ain[0];
1261 ad7194_channels->channel2 = ain[1];
1262 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);
1263 } else {
1264 ret = fwnode_property_read_u32(child, "single-channel",
1265 &ain[0]);
1266 if (ret)
1267 return dev_err_probe(dev, ret,
1268 "Missing channel property\n");
1269
1270 if (!ad7194_validate_ain_channel(dev, ain[0]))
1271 return dev_err_probe(dev, -EINVAL,
1272 "Invalid AIN channel: %u\n",
1273 ain[0]);
1274
1275 *ad7194_channels = ad7194_chan;
1276 ad7194_channels->scan_index = index++;
1277 ad7194_channels->channel = ain[0];
1278 ad7194_channels->address = AD7194_CH(ain[0]);
1279 }
1280 ad7194_channels++;
1281 }
1282
1283 *ad7194_channels = ad7194_chan_temp;
1284 ad7194_channels->scan_index = index++;
1285 ad7194_channels->address = AD7194_CH_TEMP;
1286 ad7194_channels++;
1287
1288 *ad7194_channels = ad7194_chan_timestamp;
1289 ad7194_channels->scan_index = index;
1290
1291 return 0;
1292 }
1293
1294 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
1295 [ID_AD7190] = {
1296 .chip_id = CHIPID_AD7190,
1297 .name = "ad7190",
1298 .channels = ad7192_channels,
1299 .num_channels = ARRAY_SIZE(ad7192_channels),
1300 .sigma_delta_info = &ad7192_sigma_delta_info,
1301 .info = &ad7192_info,
1302 },
1303 [ID_AD7192] = {
1304 .chip_id = CHIPID_AD7192,
1305 .name = "ad7192",
1306 .channels = ad7192_channels,
1307 .num_channels = ARRAY_SIZE(ad7192_channels),
1308 .sigma_delta_info = &ad7192_sigma_delta_info,
1309 .info = &ad7192_info,
1310 },
1311 [ID_AD7193] = {
1312 .chip_id = CHIPID_AD7193,
1313 .name = "ad7193",
1314 .channels = ad7193_channels,
1315 .num_channels = ARRAY_SIZE(ad7193_channels),
1316 .sigma_delta_info = &ad7192_sigma_delta_info,
1317 .info = &ad7192_info,
1318 },
1319 [ID_AD7194] = {
1320 .chip_id = CHIPID_AD7194,
1321 .name = "ad7194",
1322 .info = &ad7194_info,
1323 .sigma_delta_info = &ad7194_sigma_delta_info,
1324 .parse_channels = ad7194_parse_channels,
1325 },
1326 [ID_AD7195] = {
1327 .chip_id = CHIPID_AD7195,
1328 .name = "ad7195",
1329 .channels = ad7192_channels,
1330 .num_channels = ARRAY_SIZE(ad7192_channels),
1331 .sigma_delta_info = &ad7192_sigma_delta_info,
1332 .info = &ad7195_info,
1333 },
1334 };
1335
ad7192_probe(struct spi_device * spi)1336 static int ad7192_probe(struct spi_device *spi)
1337 {
1338 struct device *dev = &spi->dev;
1339 struct ad7192_state *st;
1340 struct iio_dev *indio_dev;
1341 int ret, avdd_mv;
1342
1343 if (!spi->irq)
1344 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");
1345
1346 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1347 if (!indio_dev)
1348 return -ENOMEM;
1349
1350 st = iio_priv(indio_dev);
1351
1352 mutex_init(&st->lock);
1353
1354 /*
1355 * Regulator aincom is optional to maintain compatibility with older DT.
1356 * Newer firmware should provide a zero volt fixed supply if wired to
1357 * ground.
1358 */
1359 ret = devm_regulator_get_enable_read_voltage(dev, "aincom");
1360 if (ret < 0 && ret != -ENODEV)
1361 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n");
1362
1363 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;
1364
1365 /* AVDD can optionally be used as reference voltage */
1366 ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1367 if (ret == -ENODEV || ret == -EINVAL) {
1368 int ret2;
1369
1370 /*
1371 * We get -EINVAL if avdd is a supply with unknown voltage. We
1372 * still need to enable it since it is also a power supply.
1373 */
1374 ret2 = devm_regulator_get_enable(dev, "avdd");
1375 if (ret2)
1376 return dev_err_probe(dev, ret2,
1377 "Failed to enable AVDD supply\n");
1378 } else if (ret < 0) {
1379 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n");
1380 }
1381
1382 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;
1383
1384 ret = devm_regulator_get_enable(dev, "dvdd");
1385 if (ret)
1386 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
1387
1388 /*
1389 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.
1390 * If this supply is not present, fall back to AVDD as reference.
1391 */
1392 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
1393 if (ret == -ENODEV) {
1394 if (avdd_mv == 0)
1395 return dev_err_probe(dev, -ENODEV,
1396 "No reference voltage available\n");
1397 } else if (ret < 0) {
1398 return ret;
1399 }
1400
1401 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;
1402
1403 st->chip_info = spi_get_device_match_data(spi);
1404 if (!st->chip_info)
1405 return -ENODEV;
1406
1407 indio_dev->name = st->chip_info->name;
1408 indio_dev->modes = INDIO_DIRECT_MODE;
1409 indio_dev->info = st->chip_info->info;
1410 if (st->chip_info->parse_channels) {
1411 ret = st->chip_info->parse_channels(indio_dev);
1412 if (ret)
1413 return ret;
1414 } else {
1415 indio_dev->channels = st->chip_info->channels;
1416 indio_dev->num_channels = st->chip_info->num_channels;
1417 }
1418
1419 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);
1420 if (ret)
1421 return ret;
1422
1423 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1424 if (ret)
1425 return ret;
1426
1427 ret = ad7192_clock_setup(st);
1428 if (ret)
1429 return ret;
1430
1431 ret = ad7192_setup(indio_dev, dev);
1432 if (ret)
1433 return ret;
1434
1435 return devm_iio_device_register(dev, indio_dev);
1436 }
1437
1438 static const struct of_device_id ad7192_of_match[] = {
1439 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1440 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1441 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1442 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] },
1443 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1444 { }
1445 };
1446 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1447
1448 static const struct spi_device_id ad7192_ids[] = {
1449 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1450 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1451 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1452 { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] },
1453 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1454 { }
1455 };
1456 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1457
1458 static struct spi_driver ad7192_driver = {
1459 .driver = {
1460 .name = "ad7192",
1461 .of_match_table = ad7192_of_match,
1462 },
1463 .probe = ad7192_probe,
1464 .id_table = ad7192_ids,
1465 };
1466 module_spi_driver(ad7192_driver);
1467
1468 MODULE_AUTHOR("Michael Hennerich <[email protected]>");
1469 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC");
1470 MODULE_LICENSE("GPL v2");
1471 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1472