1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2013 Altera Corporation
4 * Based on gpio-mpc8xxx.c
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/irq.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <linux/spinlock.h>
17 #include <linux/types.h>
18
19 #include <linux/gpio/driver.h>
20
21 #define ALTERA_GPIO_MAX_NGPIO 32
22 #define ALTERA_GPIO_DATA 0x0
23 #define ALTERA_GPIO_DIR 0x4
24 #define ALTERA_GPIO_IRQ_MASK 0x8
25 #define ALTERA_GPIO_EDGE_CAP 0xc
26
27 /**
28 * struct altera_gpio_chip
29 * @gc : GPIO chip structure.
30 * @regs : memory mapped IO address for the controller registers.
31 * @gpio_lock : synchronization lock so that new irq/set/get requests
32 * will be blocked until the current one completes.
33 * @interrupt_trigger : specifies the hardware configured IRQ trigger type
34 * (rising, falling, both, high)
35 */
36 struct altera_gpio_chip {
37 struct gpio_chip gc;
38 void __iomem *regs;
39 raw_spinlock_t gpio_lock;
40 int interrupt_trigger;
41 };
42
altera_gpio_irq_unmask(struct irq_data * d)43 static void altera_gpio_irq_unmask(struct irq_data *d)
44 {
45 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
46 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
47 unsigned long flags;
48 u32 intmask;
49
50 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
51
52 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
53 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
54 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
55 intmask |= BIT(irqd_to_hwirq(d));
56 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
57 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
58 }
59
altera_gpio_irq_mask(struct irq_data * d)60 static void altera_gpio_irq_mask(struct irq_data *d)
61 {
62 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
63 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
64 unsigned long flags;
65 u32 intmask;
66
67 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
68 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
69 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
70 intmask &= ~BIT(irqd_to_hwirq(d));
71 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
72 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
73
74 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
75 }
76
77 /*
78 * This controller's IRQ type is synthesized in hardware, so this function
79 * just checks if the requested set_type matches the synthesized IRQ type
80 */
altera_gpio_irq_set_type(struct irq_data * d,unsigned int type)81 static int altera_gpio_irq_set_type(struct irq_data *d,
82 unsigned int type)
83 {
84 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
85 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
86
87 if (type == IRQ_TYPE_NONE) {
88 irq_set_handler_locked(d, handle_bad_irq);
89 return 0;
90 }
91 if (type == altera_gc->interrupt_trigger) {
92 if (type == IRQ_TYPE_LEVEL_HIGH)
93 irq_set_handler_locked(d, handle_level_irq);
94 else
95 irq_set_handler_locked(d, handle_simple_irq);
96 return 0;
97 }
98 irq_set_handler_locked(d, handle_bad_irq);
99 return -EINVAL;
100 }
101
altera_gpio_irq_startup(struct irq_data * d)102 static unsigned int altera_gpio_irq_startup(struct irq_data *d)
103 {
104 altera_gpio_irq_unmask(d);
105
106 return 0;
107 }
108
altera_gpio_get(struct gpio_chip * gc,unsigned offset)109 static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
110 {
111 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
112
113 return !!(readl(altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
114 }
115
altera_gpio_set(struct gpio_chip * gc,unsigned offset,int value)116 static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
117 {
118 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
119 unsigned long flags;
120 unsigned int data_reg;
121
122 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
123 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
124 if (value)
125 data_reg |= BIT(offset);
126 else
127 data_reg &= ~BIT(offset);
128 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
129 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
130 }
131
altera_gpio_direction_input(struct gpio_chip * gc,unsigned offset)132 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
133 {
134 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
135 unsigned long flags;
136 unsigned int gpio_ddr;
137
138 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
139 /* Set pin as input, assumes software controlled IP */
140 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
141 gpio_ddr &= ~BIT(offset);
142 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
143 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
144
145 return 0;
146 }
147
altera_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)148 static int altera_gpio_direction_output(struct gpio_chip *gc,
149 unsigned offset, int value)
150 {
151 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
152 unsigned long flags;
153 unsigned int data_reg, gpio_ddr;
154
155 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
156 /* Sets the GPIO value */
157 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
158 if (value)
159 data_reg |= BIT(offset);
160 else
161 data_reg &= ~BIT(offset);
162 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
163
164 /* Set pin as output, assumes software controlled IP */
165 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
166 gpio_ddr |= BIT(offset);
167 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
168 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
169
170 return 0;
171 }
172
altera_gpio_irq_edge_handler(struct irq_desc * desc)173 static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
174 {
175 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
176 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
177 struct irq_domain *irqdomain = gc->irq.domain;
178 struct irq_chip *chip;
179 unsigned long status;
180 int i;
181
182 chip = irq_desc_get_chip(desc);
183
184 chained_irq_enter(chip, desc);
185
186 while ((status =
187 (readl(altera_gc->regs + ALTERA_GPIO_EDGE_CAP) &
188 readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
189 writel(status, altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
190 for_each_set_bit(i, &status, gc->ngpio)
191 generic_handle_domain_irq(irqdomain, i);
192 }
193
194 chained_irq_exit(chip, desc);
195 }
196
altera_gpio_irq_leveL_high_handler(struct irq_desc * desc)197 static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
198 {
199 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
200 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
201 struct irq_domain *irqdomain = gc->irq.domain;
202 struct irq_chip *chip;
203 unsigned long status;
204 int i;
205
206 chip = irq_desc_get_chip(desc);
207
208 chained_irq_enter(chip, desc);
209
210 status = readl(altera_gc->regs + ALTERA_GPIO_DATA);
211 status &= readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
212
213 for_each_set_bit(i, &status, gc->ngpio)
214 generic_handle_domain_irq(irqdomain, i);
215
216 chained_irq_exit(chip, desc);
217 }
218
219 static const struct irq_chip altera_gpio_irq_chip = {
220 .name = "altera-gpio",
221 .irq_mask = altera_gpio_irq_mask,
222 .irq_unmask = altera_gpio_irq_unmask,
223 .irq_set_type = altera_gpio_irq_set_type,
224 .irq_startup = altera_gpio_irq_startup,
225 .irq_shutdown = altera_gpio_irq_mask,
226 .flags = IRQCHIP_IMMUTABLE,
227 GPIOCHIP_IRQ_RESOURCE_HELPERS,
228 };
229
altera_gpio_probe(struct platform_device * pdev)230 static int altera_gpio_probe(struct platform_device *pdev)
231 {
232 struct device *dev = &pdev->dev;
233 int reg, ret;
234 struct altera_gpio_chip *altera_gc;
235 struct gpio_irq_chip *girq;
236 int mapped_irq;
237
238 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
239 if (!altera_gc)
240 return -ENOMEM;
241
242 raw_spin_lock_init(&altera_gc->gpio_lock);
243
244 if (device_property_read_u32(dev, "altr,ngpio", ®))
245 /* By default assume maximum ngpio */
246 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
247 else
248 altera_gc->gc.ngpio = reg;
249
250 if (altera_gc->gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
251 dev_warn(&pdev->dev,
252 "ngpio is greater than %d, defaulting to %d\n",
253 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
254 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
255 }
256
257 altera_gc->gc.direction_input = altera_gpio_direction_input;
258 altera_gc->gc.direction_output = altera_gpio_direction_output;
259 altera_gc->gc.get = altera_gpio_get;
260 altera_gc->gc.set = altera_gpio_set;
261 altera_gc->gc.owner = THIS_MODULE;
262 altera_gc->gc.parent = &pdev->dev;
263 altera_gc->gc.base = -1;
264
265 altera_gc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));
266 if (!altera_gc->gc.label)
267 return -ENOMEM;
268
269 altera_gc->regs = devm_platform_ioremap_resource(pdev, 0);
270 if (IS_ERR(altera_gc->regs))
271 return dev_err_probe(dev, PTR_ERR(altera_gc->regs), "failed to ioremap memory resource\n");
272
273 mapped_irq = platform_get_irq_optional(pdev, 0);
274 if (mapped_irq < 0)
275 goto skip_irq;
276
277 if (device_property_read_u32(dev, "altr,interrupt-type", ®)) {
278 dev_err(&pdev->dev,
279 "altr,interrupt-type value not set in device tree\n");
280 return -EINVAL;
281 }
282 altera_gc->interrupt_trigger = reg;
283
284 girq = &altera_gc->gc.irq;
285 gpio_irq_chip_set_chip(girq, &altera_gpio_irq_chip);
286
287 if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
288 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
289 else
290 girq->parent_handler = altera_gpio_irq_edge_handler;
291 girq->num_parents = 1;
292 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
293 GFP_KERNEL);
294 if (!girq->parents)
295 return -ENOMEM;
296 girq->default_type = IRQ_TYPE_NONE;
297 girq->handler = handle_bad_irq;
298 girq->parents[0] = mapped_irq;
299
300 skip_irq:
301 ret = devm_gpiochip_add_data(dev, &altera_gc->gc, altera_gc);
302 if (ret) {
303 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
304 return ret;
305 }
306
307 return 0;
308 }
309
310 static const struct of_device_id altera_gpio_of_match[] = {
311 { .compatible = "altr,pio-1.0", },
312 {},
313 };
314 MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
315
316 static struct platform_driver altera_gpio_driver = {
317 .driver = {
318 .name = "altera_gpio",
319 .of_match_table = altera_gpio_of_match,
320 },
321 .probe = altera_gpio_probe,
322 };
323
altera_gpio_init(void)324 static int __init altera_gpio_init(void)
325 {
326 return platform_driver_register(&altera_gpio_driver);
327 }
328 subsys_initcall(altera_gpio_init);
329
altera_gpio_exit(void)330 static void __exit altera_gpio_exit(void)
331 {
332 platform_driver_unregister(&altera_gpio_driver);
333 }
334 module_exit(altera_gpio_exit);
335
336 MODULE_AUTHOR("Tien Hock Loh <[email protected]>");
337 MODULE_DESCRIPTION("Altera GPIO driver");
338 MODULE_LICENSE("GPL");
339