1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel E3-1200
4 * Copyright (C) 2014 Jason Baron <[email protected]>
5 *
6 * Support for the E3-1200 processor family. Heavily based on previous
7 * Intel EDAC drivers.
8 *
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
10 * id to identify these processors.
11 *
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
13 *
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
27 *
28 * Based on Intel specification:
29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
35 *
36 * According to the above datasheet (p.16):
37 * "
38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
39 * requests that cross a DW boundary.
40 * "
41 *
42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
45 */
46
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/pci_ids.h>
51 #include <linux/edac.h>
52
53 #include <linux/io-64-nonatomic-lo-hi.h>
54 #include "edac_module.h"
55
56 #define EDAC_MOD_STR "ie31200_edac"
57
58 #define ie31200_printk(level, fmt, arg...) \
59 edac_printk(level, "ie31200", fmt, ##arg)
60
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f
72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918
73
74 /* Coffee Lake-S */
75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
86
87 /* Test if HB is for Skylake or later. */
88 #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
89 (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
90 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
91 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
92 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
93 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_12) || \
94 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
95 PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
96
97 #define IE31200_RANKS_PER_CHANNEL 4
98 #define IE31200_DIMMS_PER_CHANNEL 2
99 #define IE31200_CHANNELS 2
100
101 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
102 #define IE31200_MCHBAR_LOW 0x48
103 #define IE31200_MCHBAR_HIGH 0x4c
104 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
105 #define IE31200_MMR_WINDOW_SIZE BIT(15)
106
107 /*
108 * Error Status Register (16b)
109 *
110 * 15 reserved
111 * 14 Isochronous TBWRR Run Behind FIFO Full
112 * (ITCV)
113 * 13 Isochronous TBWRR Run Behind FIFO Put
114 * (ITSTV)
115 * 12 reserved
116 * 11 MCH Thermal Sensor Event
117 * for SMI/SCI/SERR (GTSE)
118 * 10 reserved
119 * 9 LOCK to non-DRAM Memory Flag (LCKF)
120 * 8 reserved
121 * 7 DRAM Throttle Flag (DTF)
122 * 6:2 reserved
123 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
124 * 0 Single-bit DRAM ECC Error Flag (DSERR)
125 */
126 #define IE31200_ERRSTS 0xc8
127 #define IE31200_ERRSTS_UE BIT(1)
128 #define IE31200_ERRSTS_CE BIT(0)
129 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
130
131 /*
132 * Channel 0 ECC Error Log (64b)
133 *
134 * 63:48 Error Column Address (ERRCOL)
135 * 47:32 Error Row Address (ERRROW)
136 * 31:29 Error Bank Address (ERRBANK)
137 * 28:27 Error Rank Address (ERRRANK)
138 * 26:24 reserved
139 * 23:16 Error Syndrome (ERRSYND)
140 * 15: 2 reserved
141 * 1 Multiple Bit Error Status (MERRSTS)
142 * 0 Correctable Error Status (CERRSTS)
143 */
144
145 #define IE31200_C0ECCERRLOG 0x40c8
146 #define IE31200_C1ECCERRLOG 0x44c8
147 #define IE31200_C0ECCERRLOG_SKL 0x4048
148 #define IE31200_C1ECCERRLOG_SKL 0x4448
149 #define IE31200_ECCERRLOG_CE BIT(0)
150 #define IE31200_ECCERRLOG_UE BIT(1)
151 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
152 #define IE31200_ECCERRLOG_RANK_SHIFT 27
153 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
154 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
155
156 #define IE31200_ECCERRLOG_SYNDROME(log) \
157 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
158 IE31200_ECCERRLOG_SYNDROME_SHIFT)
159
160 #define IE31200_CAPID0 0xe4
161 #define IE31200_CAPID0_PDCD BIT(4)
162 #define IE31200_CAPID0_DDPCD BIT(6)
163 #define IE31200_CAPID0_ECC BIT(1)
164
165 #define IE31200_MAD_DIMM_0_OFFSET 0x5004
166 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
167 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
168 #define IE31200_MAD_DIMM_SIZE_SKL GENMASK_ULL(5, 0)
169 #define IE31200_MAD_DIMM_A_RANK BIT(17)
170 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
171 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
172 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
173 #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
174 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
175 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
176 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
177
178 /* Skylake reports 1GB increments, everything else is 256MB */
179 #define IE31200_PAGES(n, skl) \
180 (n << (28 + (2 * skl) - PAGE_SHIFT))
181
182 static int nr_channels;
183 static struct pci_dev *mci_pdev;
184 static int ie31200_registered = 1;
185
186 struct ie31200_priv {
187 void __iomem *window;
188 void __iomem *c0errlog;
189 void __iomem *c1errlog;
190 };
191
192 enum ie31200_chips {
193 IE31200 = 0,
194 };
195
196 struct ie31200_dev_info {
197 const char *ctl_name;
198 };
199
200 struct ie31200_error_info {
201 u16 errsts;
202 u16 errsts2;
203 u64 eccerrlog[IE31200_CHANNELS];
204 };
205
206 static const struct ie31200_dev_info ie31200_devs[] = {
207 [IE31200] = {
208 .ctl_name = "IE31200"
209 },
210 };
211
212 struct dimm_data {
213 u8 size; /* in multiples of 256MB, except Skylake is 1GB */
214 u8 dual_rank : 1,
215 x16_width : 2; /* 0 means x8 width */
216 };
217
how_many_channels(struct pci_dev * pdev)218 static int how_many_channels(struct pci_dev *pdev)
219 {
220 int n_channels;
221 unsigned char capid0_2b; /* 2nd byte of CAPID0 */
222
223 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
224
225 /* check PDCD: Dual Channel Disable */
226 if (capid0_2b & IE31200_CAPID0_PDCD) {
227 edac_dbg(0, "In single channel mode\n");
228 n_channels = 1;
229 } else {
230 edac_dbg(0, "In dual channel mode\n");
231 n_channels = 2;
232 }
233
234 /* check DDPCD - check if both channels are filled */
235 if (capid0_2b & IE31200_CAPID0_DDPCD)
236 edac_dbg(0, "2 DIMMS per channel disabled\n");
237 else
238 edac_dbg(0, "2 DIMMS per channel enabled\n");
239
240 return n_channels;
241 }
242
ecc_capable(struct pci_dev * pdev)243 static bool ecc_capable(struct pci_dev *pdev)
244 {
245 unsigned char capid0_4b; /* 4th byte of CAPID0 */
246
247 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
248 if (capid0_4b & IE31200_CAPID0_ECC)
249 return false;
250 return true;
251 }
252
eccerrlog_row(u64 log)253 static int eccerrlog_row(u64 log)
254 {
255 return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
256 IE31200_ECCERRLOG_RANK_SHIFT);
257 }
258
ie31200_clear_error_info(struct mem_ctl_info * mci)259 static void ie31200_clear_error_info(struct mem_ctl_info *mci)
260 {
261 /*
262 * Clear any error bits.
263 * (Yes, we really clear bits by writing 1 to them.)
264 */
265 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
266 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
267 }
268
ie31200_get_and_clear_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)269 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
270 struct ie31200_error_info *info)
271 {
272 struct pci_dev *pdev;
273 struct ie31200_priv *priv = mci->pvt_info;
274
275 pdev = to_pci_dev(mci->pdev);
276
277 /*
278 * This is a mess because there is no atomic way to read all the
279 * registers at once and the registers can transition from CE being
280 * overwritten by UE.
281 */
282 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
283 if (!(info->errsts & IE31200_ERRSTS_BITS))
284 return;
285
286 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
287 if (nr_channels == 2)
288 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
289
290 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
291
292 /*
293 * If the error is the same for both reads then the first set
294 * of reads is valid. If there is a change then there is a CE
295 * with no info and the second set of reads is valid and
296 * should be UE info.
297 */
298 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
299 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
300 if (nr_channels == 2)
301 info->eccerrlog[1] =
302 lo_hi_readq(priv->c1errlog);
303 }
304
305 ie31200_clear_error_info(mci);
306 }
307
ie31200_process_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)308 static void ie31200_process_error_info(struct mem_ctl_info *mci,
309 struct ie31200_error_info *info)
310 {
311 int channel;
312 u64 log;
313
314 if (!(info->errsts & IE31200_ERRSTS_BITS))
315 return;
316
317 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
318 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
319 -1, -1, -1, "UE overwrote CE", "");
320 info->errsts = info->errsts2;
321 }
322
323 for (channel = 0; channel < nr_channels; channel++) {
324 log = info->eccerrlog[channel];
325 if (log & IE31200_ECCERRLOG_UE) {
326 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
327 0, 0, 0,
328 eccerrlog_row(log),
329 channel, -1,
330 "ie31200 UE", "");
331 } else if (log & IE31200_ECCERRLOG_CE) {
332 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
333 0, 0,
334 IE31200_ECCERRLOG_SYNDROME(log),
335 eccerrlog_row(log),
336 channel, -1,
337 "ie31200 CE", "");
338 }
339 }
340 }
341
ie31200_check(struct mem_ctl_info * mci)342 static void ie31200_check(struct mem_ctl_info *mci)
343 {
344 struct ie31200_error_info info;
345
346 ie31200_get_and_clear_error_info(mci, &info);
347 ie31200_process_error_info(mci, &info);
348 }
349
ie31200_map_mchbar(struct pci_dev * pdev)350 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
351 {
352 union {
353 u64 mchbar;
354 struct {
355 u32 mchbar_low;
356 u32 mchbar_high;
357 };
358 } u;
359 void __iomem *window;
360
361 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
362 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
363 u.mchbar &= IE31200_MCHBAR_MASK;
364
365 if (u.mchbar != (resource_size_t)u.mchbar) {
366 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
367 (unsigned long long)u.mchbar);
368 return NULL;
369 }
370
371 window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
372 if (!window)
373 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
374 (unsigned long long)u.mchbar);
375
376 return window;
377 }
378
__skl_populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)379 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
380 int chan)
381 {
382 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE_SKL;
383 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
384 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
385 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
386 }
387
__populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)388 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
389 int chan)
390 {
391 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
392 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
393 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
394 }
395
populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan,bool skl)396 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
397 bool skl)
398 {
399 if (skl)
400 __skl_populate_dimm_info(dd, addr_decode, chan);
401 else
402 __populate_dimm_info(dd, addr_decode, chan);
403 }
404
405
ie31200_probe1(struct pci_dev * pdev,int dev_idx)406 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
407 {
408 int i, j, ret;
409 struct mem_ctl_info *mci = NULL;
410 struct edac_mc_layer layers[2];
411 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
412 void __iomem *window;
413 struct ie31200_priv *priv;
414 u32 addr_decode, mad_offset;
415
416 /*
417 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
418 * this logic when adding new CPU support.
419 */
420 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
421
422 edac_dbg(0, "MC:\n");
423
424 if (!ecc_capable(pdev)) {
425 ie31200_printk(KERN_INFO, "No ECC support\n");
426 return -ENODEV;
427 }
428
429 nr_channels = how_many_channels(pdev);
430 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
431 layers[0].size = IE31200_RANKS_PER_CHANNEL;
432 layers[0].is_virt_csrow = true;
433 layers[1].type = EDAC_MC_LAYER_CHANNEL;
434 layers[1].size = nr_channels;
435 layers[1].is_virt_csrow = false;
436 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
437 sizeof(struct ie31200_priv));
438 if (!mci)
439 return -ENOMEM;
440
441 window = ie31200_map_mchbar(pdev);
442 if (!window) {
443 ret = -ENODEV;
444 goto fail_free;
445 }
446
447 edac_dbg(3, "MC: init mci\n");
448 mci->pdev = &pdev->dev;
449 if (skl)
450 mci->mtype_cap = MEM_FLAG_DDR4;
451 else
452 mci->mtype_cap = MEM_FLAG_DDR3;
453 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
454 mci->edac_cap = EDAC_FLAG_SECDED;
455 mci->mod_name = EDAC_MOD_STR;
456 mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
457 mci->dev_name = pci_name(pdev);
458 mci->edac_check = ie31200_check;
459 mci->ctl_page_to_phys = NULL;
460 priv = mci->pvt_info;
461 priv->window = window;
462 if (skl) {
463 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
464 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
465 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
466 } else {
467 priv->c0errlog = window + IE31200_C0ECCERRLOG;
468 priv->c1errlog = window + IE31200_C1ECCERRLOG;
469 mad_offset = IE31200_MAD_DIMM_0_OFFSET;
470 }
471
472 /* populate DIMM info */
473 for (i = 0; i < IE31200_CHANNELS; i++) {
474 addr_decode = readl(window + mad_offset +
475 (i * 4));
476 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
477 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
478 populate_dimm_info(&dimm_info[i][j], addr_decode, j,
479 skl);
480 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
481 dimm_info[i][j].size,
482 dimm_info[i][j].dual_rank,
483 dimm_info[i][j].x16_width);
484 }
485 }
486
487 /*
488 * The dram rank boundary (DRB) reg values are boundary addresses
489 * for each DRAM rank with a granularity of 64MB. DRB regs are
490 * cumulative; the last one will contain the total memory
491 * contained in all ranks.
492 */
493 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
494 for (j = 0; j < IE31200_CHANNELS; j++) {
495 struct dimm_info *dimm;
496 unsigned long nr_pages;
497
498 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
499 if (nr_pages == 0)
500 continue;
501
502 if (dimm_info[j][i].dual_rank) {
503 nr_pages = nr_pages / 2;
504 dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
505 dimm->nr_pages = nr_pages;
506 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
507 dimm->grain = 8; /* just a guess */
508 if (skl)
509 dimm->mtype = MEM_DDR4;
510 else
511 dimm->mtype = MEM_DDR3;
512 dimm->dtype = DEV_UNKNOWN;
513 dimm->edac_mode = EDAC_UNKNOWN;
514 }
515 dimm = edac_get_dimm(mci, i * 2, j, 0);
516 dimm->nr_pages = nr_pages;
517 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
518 dimm->grain = 8; /* same guess */
519 if (skl)
520 dimm->mtype = MEM_DDR4;
521 else
522 dimm->mtype = MEM_DDR3;
523 dimm->dtype = DEV_UNKNOWN;
524 dimm->edac_mode = EDAC_UNKNOWN;
525 }
526 }
527
528 ie31200_clear_error_info(mci);
529
530 if (edac_mc_add_mc(mci)) {
531 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
532 ret = -ENODEV;
533 goto fail_unmap;
534 }
535
536 /* get this far and it's successful */
537 edac_dbg(3, "MC: success\n");
538 return 0;
539
540 fail_unmap:
541 iounmap(window);
542
543 fail_free:
544 edac_mc_free(mci);
545
546 return ret;
547 }
548
ie31200_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)549 static int ie31200_init_one(struct pci_dev *pdev,
550 const struct pci_device_id *ent)
551 {
552 int rc;
553
554 edac_dbg(0, "MC:\n");
555 if (pci_enable_device(pdev) < 0)
556 return -EIO;
557 rc = ie31200_probe1(pdev, ent->driver_data);
558 if (rc == 0 && !mci_pdev)
559 mci_pdev = pci_dev_get(pdev);
560
561 return rc;
562 }
563
ie31200_remove_one(struct pci_dev * pdev)564 static void ie31200_remove_one(struct pci_dev *pdev)
565 {
566 struct mem_ctl_info *mci;
567 struct ie31200_priv *priv;
568
569 edac_dbg(0, "\n");
570 pci_dev_put(mci_pdev);
571 mci_pdev = NULL;
572 mci = edac_mc_del_mc(&pdev->dev);
573 if (!mci)
574 return;
575 priv = mci->pvt_info;
576 iounmap(priv->window);
577 edac_mc_free(mci);
578 }
579
580 static const struct pci_device_id ie31200_pci_tbl[] = {
581 { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
582 { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
583 { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
584 { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
585 { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
586 { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
587 { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588 { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589 { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
590 { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
591 { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
592 { PCI_VEND_DEV(INTEL, IE31200_HB_12), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
593 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
594 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
595 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
596 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
597 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
598 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
599 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
600 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
601 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
602 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
603 { 0, } /* 0 terminated list. */
604 };
605 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
606
607 static struct pci_driver ie31200_driver = {
608 .name = EDAC_MOD_STR,
609 .probe = ie31200_init_one,
610 .remove = ie31200_remove_one,
611 .id_table = ie31200_pci_tbl,
612 };
613
ie31200_init(void)614 static int __init ie31200_init(void)
615 {
616 int pci_rc, i;
617
618 edac_dbg(3, "MC:\n");
619 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
620 opstate_init();
621
622 pci_rc = pci_register_driver(&ie31200_driver);
623 if (pci_rc < 0)
624 return pci_rc;
625
626 if (!mci_pdev) {
627 ie31200_registered = 0;
628 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
629 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
630 ie31200_pci_tbl[i].device,
631 NULL);
632 if (mci_pdev)
633 break;
634 }
635
636 if (!mci_pdev) {
637 edac_dbg(0, "ie31200 pci_get_device fail\n");
638 pci_rc = -ENODEV;
639 goto fail0;
640 }
641
642 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
643 if (pci_rc < 0) {
644 edac_dbg(0, "ie31200 init fail\n");
645 pci_rc = -ENODEV;
646 goto fail1;
647 }
648 }
649
650 return 0;
651 fail1:
652 pci_dev_put(mci_pdev);
653 fail0:
654 pci_unregister_driver(&ie31200_driver);
655
656 return pci_rc;
657 }
658
ie31200_exit(void)659 static void __exit ie31200_exit(void)
660 {
661 edac_dbg(3, "MC:\n");
662 pci_unregister_driver(&ie31200_driver);
663 if (!ie31200_registered)
664 ie31200_remove_one(mci_pdev);
665 }
666
667 module_init(ie31200_init);
668 module_exit(ie31200_exit);
669
670 MODULE_LICENSE("GPL");
671 MODULE_AUTHOR("Jason Baron <[email protected]>");
672 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
673