1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <delay.h>
6 #include <soc/emi.h>
7 #include <soc/dramc_pi_api.h>
8 #include <soc/dramc_param.h>
9 #include <soc/dramc_register.h>
10 #include <soc/infracfg.h>
11 #include <string.h>
12 #include <timer.h>
13
dramc_cke_fix_onoff(enum cke_type option,u8 chn)14 void dramc_cke_fix_onoff(enum cke_type option, u8 chn)
15 {
16 u8 on = 0, off = 0;
17
18 /* if CKE is dynamic, set both CKE fix On and Off as 0 */
19 if (option != CKE_DYNAMIC) {
20 on = option;
21 off = 1 - option;
22 }
23
24 SET32_BITFIELDS(&ch[chn].ao.ckectrl,
25 CKECTRL_CKEFIXON, on,
26 CKECTRL_CKEFIXOFF, off);
27 }
28
dvfs_settings(u8 freq_group)29 static void dvfs_settings(u8 freq_group)
30 {
31 u8 dll_idle;
32
33 switch (freq_group) {
34 case LP4X_DDR1600:
35 dll_idle = 0x18;
36 break;
37 case LP4X_DDR2400:
38 dll_idle = 0x10;
39 break;
40 case LP4X_DDR3200:
41 dll_idle = 0xc;
42 break;
43 case LP4X_DDR3600:
44 dll_idle = 0xa;
45 break;
46 default:
47 die("Invalid DDR frequency group %u\n", freq_group);
48 return;
49 }
50
51 dll_idle = dll_idle << 1;
52 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
53 setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5);
54 setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29);
55 clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle);
56
57 setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19);
58 setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24);
59 setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7);
60 }
61 }
62
ddr_phy_pll_setting(u8 chn,u8 freq_group)63 static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
64 {
65 u8 cap_sel, mid_cap_sel;
66 u8 vth_sel = 0x2;
67 u8 ca_dll_mode[2];
68 u32 sdm_pcw, delta;
69
70 switch (freq_group) {
71 case LP4X_DDR1600:
72 mid_cap_sel = 0x0;
73 cap_sel = 0x3;
74 sdm_pcw = 0x7b00;
75 delta = 0;
76 break;
77 case LP4X_DDR2400:
78 mid_cap_sel = 0x3;
79 cap_sel = 0x0;
80 sdm_pcw = 0x5c00;
81 delta = 0;
82 break;
83 case LP4X_DDR3200:
84 mid_cap_sel = 0x2;
85 cap_sel = 0x0;
86 sdm_pcw = 0x7b00;
87 delta = 0xc03;
88 break;
89 case LP4X_DDR3600:
90 mid_cap_sel = 0x1;
91 cap_sel = 0x0;
92 sdm_pcw = 0x8a00;
93 delta = 0xd96;
94 break;
95 default:
96 die("Invalid DDR frequency group %u\n", freq_group);
97 return;
98 }
99
100 if (freq_group == LP4X_DDR1600)
101 ca_dll_mode[CHANNEL_A] = DLL_SLAVE;
102 else
103 ca_dll_mode[CHANNEL_A] = DLL_MASTER;
104 ca_dll_mode[CHANNEL_B] = DLL_SLAVE;
105
106 clrbits32(&ch[chn].phy.shu[0].pll[4], 0xffff);
107 clrbits32(&ch[chn].phy.shu[0].pll[6], 0xffff);
108 setbits32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18);
109 clrsetbits32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0);
110 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18);
111
112 SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1,
113 ca_dll_mode[chn] == DLL_SLAVE);
114
115 bool is_master = (ca_dll_mode[chn] == DLL_MASTER);
116 u8 phdet_out = is_master ? 0x0 : 0x1;
117 u8 phdet_in = is_master ? 0x0 : 0x1;
118 u8 gain = is_master ? 0x6 : 0x7;
119 u8 idle_cnt = is_master ? 0x9 : 0x7;
120 u8 fast_psjp = is_master ? 0x1 : 0x0;
121
122 clrsetbits32(&ch[chn].phy.shu[0].ca_dll[0],
123 (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) |
124 (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4),
125 (phdet_out << 31) | (phdet_in << 30) |
126 (gain << 20) | (idle_cnt << 16) |
127 (0x8 << 12) |
128 (0x1 << 10) | (0x1 << 9) | (fast_psjp << 4));
129
130 u8 pd_ck_sel = is_master ? 0x1 : 0x0;
131 u8 fastpj_ck_sel = is_master ? 0x0 : 0x1;
132
133 clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1],
134 (0x1 << 2) | (0x1 << 0),
135 (pd_ck_sel << 2) | (fastpj_ck_sel << 0));
136
137 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6],
138 0x1 << 7, (is_master ? 0x1 : 0x0) << 7);
139
140 struct reg_value regs_bak[] = {
141 {&ch[chn].phy.b[0].dq[7]},
142 {&ch[chn].phy.b[1].dq[7]},
143 {&ch[chn].phy.ca_cmd[7]},
144 };
145
146 for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
147 regs_bak[i].value = read32(regs_bak[i].addr);
148
149 for (size_t b = 0; b < 2; b++)
150 setbits32(&ch[chn].phy.b[b].dq[7],
151 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
152 setbits32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
153 setbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
154
155 /* 26M */
156 SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0);
157
158 /* MID FINE_TUNE */
159 clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27));
160 clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27));
161 clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27));
162 clrbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
163
164 /* PLL */
165 clrbits32(&ch[chn].phy.pll1, 0x1 << 31);
166 clrbits32(&ch[chn].phy.pll2, 0x1 << 31);
167
168 /* DLL */
169 clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
170 clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
171 clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
172 setbits32(&ch[chn].phy.b[0].dll_fine_tune[2],
173 (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) |
174 (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
175 setbits32(&ch[chn].phy.b[1].dll_fine_tune[2],
176 (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) |
177 (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
178 setbits32(&ch[chn].phy.ca_dll_fine_tune[2],
179 (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 15) |
180 (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
181
182 /* RESETB */
183 clrbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
184 clrbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
185 clrbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
186
187 udelay(1);
188
189 /* MPLL 52M */
190 clrsetbits32(&ch[chn].phy.shu[0].pll[8],
191 (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
192 clrsetbits32(&ch[chn].phy.shu[0].pll[10],
193 (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
194 clrsetbits32(&ch[chn].phy.shu[0].pll[5],
195 (0xffff << 16) | 0x1 << 0, sdm_pcw << 16);
196 clrsetbits32(&ch[chn].phy.shu[0].pll[7],
197 (0xffff << 16) | 0x1 << 0, sdm_pcw << 16);
198
199 setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1);
200 setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1);
201 setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1);
202
203 clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11);
204 clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19);
205 clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19);
206
207 clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6],
208 (0x3 << 22) | (0x3 << 24) | (0x3 << 28),
209 (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
210 clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6],
211 (0x3 << 22) | (0x3 << 24) | (0x3 << 28),
212 (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
213 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6],
214 (0x3 << 22) | (0x3 << 24) | (0x3 << 28),
215 (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
216
217 /* RESETB */
218 setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
219 setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
220 setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
221 udelay(1);
222
223 /* PLL EN */
224 setbits32(&ch[chn].phy.pll1, 0x1 << 31);
225 setbits32(&ch[chn].phy.pll2, 0x1 << 31);
226 udelay(100);
227
228 /* MIDPI Init 1 */
229 setbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
230 udelay(1);
231
232 /* MIDPI Init 2 */
233 u8 midpi_en;
234 u8 midpi_ckdiv4_en;
235
236 if (freq_group > LP4X_DDR1600) {
237 midpi_en = 0x1;
238 midpi_ckdiv4_en = 0x0;
239 } else {
240 midpi_en = 0x0;
241 midpi_ckdiv4_en = 0x1;
242 }
243
244 u32 dq6_clear = (0x1 << 26) | (0x1 << 27);
245 u32 dq6_set = (midpi_en << 26) | (midpi_ckdiv4_en << 27);
246
247 clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set);
248 clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set);
249 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set);
250
251 udelay(1);
252 clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19,
253 (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) |
254 ((chn ? 0 : 1) << 19));
255 setbits32(&ch[chn].phy.b[0].dll_fine_tune[3],
256 (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) |
257 (0x1 << 17));
258 setbits32(&ch[chn].phy.b[1].dll_fine_tune[3],
259 (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) |
260 (0x1 << 17));
261
262 clrbits32(&ch[chn].phy.ca_dll_fine_tune[2],
263 (0x1 << 10) | (0x1 << 13) |
264 (0x1 << 15) | (0x1 << 16) | (0x1 << 17) |
265 (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
266 clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2],
267 (0x1 << 10) | (0x1 << 13) | (0x1 << 14) |
268 (0x1 << 15) | (0x1 << 17) |
269 (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
270 clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2],
271 (0x1 << 10) | (0x1 << 13) |
272 (0x1 << 14) | (0x1 << 15) | (0x1 << 17) |
273 (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
274
275 setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11);
276 clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11);
277 clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11);
278 udelay(2);
279
280 setbits32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4);
281 udelay(1);
282
283 /* DLL */
284 setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
285 udelay(1);
286 setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
287 setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
288 udelay(1);
289
290 clrbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
291 for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
292 write32(regs_bak[i].addr, regs_bak[i].value);
293
294 dramc_cke_fix_onoff(CKE_DYNAMIC, CHANNEL_A);
295 dramc_cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B);
296
297 if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) {
298 setbits32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0);
299 setbits32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0);
300 setbits32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1);
301 setbits32(&ch[chn].phy.shu[0].pll20, 0x1 << 1);
302 clrsetbits32(&ch[chn].phy.shu[0].pll[14],
303 0xffff << 16, 0x0208 << 16);
304 clrsetbits32(&ch[chn].phy.shu[0].pll20,
305 0xffff << 16, 0x0208 << 16);
306 clrsetbits32(&ch[chn].phy.shu[0].pll[15],
307 0xffffffff << 0, delta << 16);
308 clrsetbits32(&ch[chn].phy.shu[0].pll21,
309 0xffffffff << 0, delta << 16);
310 }
311 }
312
dramc_gating_mode(u8 mode)313 static void dramc_gating_mode(u8 mode)
314 {
315 u8 vref_sel = 0, burst = 0;
316
317 if (mode) {
318 vref_sel = 2;
319 burst = 1;
320 }
321
322 for (u8 b = 0; b < 2; b++) {
323 clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14);
324 setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
325 }
326
327 clrsetbits32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5);
328 setbits32(&ch[0].ao.stbcal, 0x1 << 30);
329
330 for (u8 b = 0; b < 2; b++) {
331 clrbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
332 udelay(1);
333 setbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
334 }
335 }
336
update_initial_settings(u8 freq_group)337 static void update_initial_settings(u8 freq_group)
338 {
339 u8 operate_fsp = get_freq_fsq(freq_group);
340 u16 rx_vref = 0x16;
341
342 if (operate_fsp == FSP_1)
343 rx_vref = 0xb;
344
345 if (operate_fsp == FSP_1) {
346 setbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
347 setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
348 setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
349 } else {
350 clrbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
351 clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
352 clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
353 }
354
355 for (size_t b = 0; b < 2; b++)
356 for (size_t r = 0; r < 2; r++)
357 clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
358 (0x1 << 23) | (0x1 << 28) | (0x3 << 30));
359 clrbits32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0);
360
361 setbits32(&ch[0].phy.ca_cmd[3], 0x1 << 10);
362 setbits32(&ch[0].phy.ca_cmd[10], 0x1 << 5);
363 clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14);
364 setbits32(&ch[0].phy.b[0].dq[3], 0x7 << 5);
365 setbits32(&ch[0].phy.b[1].dq[3], 0x7 << 5);
366 setbits32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7));
367 clrbits32(&ch[0].phy.b[0].dq[3], 0x1 << 1);
368 clrbits32(&ch[0].phy.b[1].dq[3], 0x1 << 1);
369 setbits32(&ch[0].phy.b[0].dq[5], 0x1 << 31);
370 setbits32(&ch[0].phy.b[1].dq[5], 0x1 << 31);
371 setbits32(&ch[0].phy.ca_cmd[5], 0x1 << 31);
372
373 clrsetbits32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16);
374 clrsetbits32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6),
375 (0x1 << 5) | (0x0 << 6));
376 setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 9);
377 setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 9);
378 setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 9);
379 clrsetbits32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
380 clrsetbits32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0);
381 clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
382
383 setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 6);
384 setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 3);
385 setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 3);
386 setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 3);
387 setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 5);
388 setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 5);
389 setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 5);
390
391 for (u8 b = 0; b < 2; b++) {
392 clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0);
393 clrsetbits32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8);
394 }
395
396 setbits32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
397 setbits32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
398 setbits32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
399 dramc_gating_mode(1);
400
401 setbits32(&ch[0].phy.ca_cmd[8], 0x1 << 19);
402 clrbits32(&ch[0].phy.ca_cmd[8], 0x1 << 18);
403 clrsetbits32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0);
404 clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16),
405 (0x2a << 20) | (0x1 << 16));
406
407 clrbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8);
408 clrbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8);
409 clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8);
410
411 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
412 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
413 clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0);
414 clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0);
415 clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0);
416 }
417 dramc_set_broadcast(DRAMC_BROADCAST_ON);
418
419 /* IMP Tracking Init Settings */
420 clrsetbits32(&ch[0].ao.shu[0].impcal1,
421 (0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28),
422 (0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28));
423
424 setbits32(&ch[0].ao.srefctrl, 0xf << 12);
425 setbits32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17);
426 setbits32(&ch[0].ao.shu[0].misc, 0xf << 12);
427 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[8],
428 (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
429 (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
430 clrsetbits32(&ch[0].phy.shu[0].b[1].dq[8],
431 (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
432 (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
433 clrsetbits32(&ch[0].phy.shu[0].ca_cmd[8],
434 (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
435 (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
436 setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 26);
437 clrbits32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
438 clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
439 clrsetbits32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15),
440 (0x7fff << 0) | (0x1 << 15));
441
442 clrbits32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29);
443 clrbits32(&ch[0].ao.write_lev, 0x1 << 2);
444 setbits32(&ch[0].ao.dummy_rd, 0x1 << 24);
445 clrbits32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1));
446 setbits32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
447 setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3));
448
449 setbits32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0);
450 setbits32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0);
451 setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
452
453 setbits32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26));
454 setbits32(&ch[0].ao.srefctrl, 0x1 << 22);
455 clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0);
456 setbits32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12));
457 setbits32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12));
458 setbits32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12));
459 setbits32(&ch[0].ao.stbcal2, 0x1 << 16);
460 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
461 (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),
462 (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));
463 clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7],
464 (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),
465 (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));
466
467 /* Disable RODT tracking */
468 clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0);
469
470 /* Rx Gating tracking settings */
471 clrsetbits32(&ch[0].ao.shu[0].dqsg,
472 (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12));
473 clrbits32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15));
474 clrbits32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15));
475 clrsetbits32(&ch[0].ao.shu[0].stbcal,
476 (0x7 << 4) | (0x1 << 8), (0x1 << 4) | (0x1 << 8));
477
478 clrsetbits32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8);
479 clrsetbits32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8);
480 clrbits32(&ch[0].phy.ca_cmd[10], 0xff << 8);
481
482 setbits32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24);
483 setbits32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24);
484
485 /* Enable WDQS */
486 clrsetbits32(&ch[0].phy.shu[0].b[0].dll[1],
487 (0x1 << 10) | (0x1 << 16) | (0x1 << 17),
488 (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17));
489 clrsetbits32(&ch[0].phy.shu[0].b[1].dll[1],
490 (0x1 << 10) | (0x1 << 16) | (0x1 << 17),
491 (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17));
492 setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
493 setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
494 setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
495 setbits32(&ch[0].ao.drsctrl, 0x1 << 19);
496 setbits32(&ch[0].ao.refctrl0, 0x1 << 28);
497 setbits32(&ch[0].ao.zqcs, 0x1 << 19);
498 setbits32(&ch[0].ao.dummy_rd, 0x3 << 26);
499 setbits32(&ch[0].ao.shuctrl2, 0x1 << 8);
500 clrsetbits32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24);
501 setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 27);
502 setbits32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20);
503 setbits32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20);
504 setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20);
505 clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 27);
506 setbits32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8);
507 setbits32(&ch[0].ao.clkctrl, 0x1 << 7);
508 setbits32(&ch[0].ao.refctrl1, 0x1 << 7);
509 clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26),
510 (0x0 << 2) | (0x3 << 6) | (0x3 << 26));
511 setbits32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10));
512 clrbits32(&ch[0].ao.stbcal2, 0xf << 4);
513 clrbits32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19);
514
515 setbits32(&ch[0].ao.ckectrl, 0x1 << 22);
516 clrsetbits32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26),
517 (0x1 << 31) | (0xa << 21) | (0xa << 26));
518 setbits32(&ch[0].ao.ckectrl, 0x1 << 23);
519 clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31);
520
521 /* CA prebit shift and delay */
522 SET32_BITFIELDS(&ch[0].ao.shu[0].selph_ca7,
523 SHU_SELPH_CA7_DLY_RA0, 0x0,
524 SHU_SELPH_CA7_DLY_RA1, 0x0,
525 SHU_SELPH_CA7_DLY_RA2, 0x0,
526 SHU_SELPH_CA7_DLY_RA3, 0x0,
527 SHU_SELPH_CA7_DLY_RA4, 0x0,
528 SHU_SELPH_CA7_DLY_RA5, 0x0);
529 SET32_BITFIELDS(&ch[0].phy.shu[0].rk[0].ca_cmd[9],
530 SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 0x20);
531 SET32_BITFIELDS(&ch[0].phy.shu[0].rk[1].ca_cmd[9],
532 SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 0x20);
533 }
534
dramc_power_on_sequence(void)535 static void dramc_power_on_sequence(void)
536 {
537 for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
538 clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
539
540 dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_A);
541 dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_B);
542
543 udelay(200);
544 for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
545 setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
546
547 for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
548 setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
549
550 udelay(2000);
551 dramc_cke_fix_onoff(CKE_FIXON, CHANNEL_A);
552 dramc_cke_fix_onoff(CKE_FIXON, CHANNEL_B);
553 udelay(2);
554 }
555
ddr_phy_reserved_rg_setting(u8 freq_group)556 static void ddr_phy_reserved_rg_setting(u8 freq_group)
557 {
558 u32 hyst_sel = 0, midpi_cap_sel = 0, lp3_sel = 0;
559
560 if (get_freq_fsq(freq_group) == FSP_0) {
561 hyst_sel = 1;
562 midpi_cap_sel = 1;
563 }
564
565 if (freq_group == LP4X_DDR1600)
566 lp3_sel = 1;
567
568 /* fine tune */
569 for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
570 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6,
571 (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) |
572 (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20));
573
574 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
575 clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1],
576 (0xf << 9) | (0x1f << 16) | (0x7ff << 21),
577 (0x1 << 8) | (0x7 << 13) | (0x4 << 16));
578
579 for (u8 b = 0; b < 2; b++) {
580 clrsetbits32(&ch[chn].phy.shu[0].b[b].dq[6],
581 (0x1f << 6) | (0x3f << 11) | (0x7 << 19),
582 (0x1 << 6) | (hyst_sel << 8) | (midpi_cap_sel << 9)
583 | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20));
584
585 clrsetbits32(&ch[chn].phy.shu[0].b[b].dll[1],
586 (0x3 << 8) | (0x3 << 11) | (0x7 << 14) | (0x3fff << 18),
587 (0x1 << 10) | (0x1 << 13) | (0x1 << 17));
588 }
589 }
590 }
591
dramc_duty_set_clk_delay(u8 chn,s8 clkDelay)592 static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay)
593 {
594 u8 dly, dlyb, revb0, revb1;
595
596 dly = (clkDelay < 0) ? -clkDelay : 0;
597 dlyb = (clkDelay < 0) ? 0 : clkDelay;
598 revb0 = dly ? 1 : 0;
599 revb1 = dlyb ? 1 : 0;
600
601 for (u8 r = 0; r < RANK_MAX; r++) {
602 clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1],
603 (0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28));
604 clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0],
605 (0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28));
606 }
607 clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[3],
608 (0x3 << 8), (revb0 << 8) | (revb1 << 9));
609 }
610
dramc_duty_set_dqs_delay(u8 chn,const s8 * s_dqsDelay)611 static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay)
612 {
613 u8 dly, dlyb, revb0, revb1;
614 s8 dqsDelay;
615
616 for (u8 r = 0; r < RANK_MAX; r++)
617 for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) {
618 dqsDelay = s_dqsDelay[dqs];
619
620 dly = (dqsDelay < 0) ? -dqsDelay : 0;
621 dlyb = (dqsDelay < 0) ? 0 : dqsDelay;
622 revb0 = dly ? 1 : 0;
623 revb1 = dlyb ? 1 : 0;
624 clrsetbits32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1],
625 (0xf << 24) | (0xf << 28) | (0xf << 16) | (0xf << 20),
626 (dly << 24) | (dly << 28) | (dlyb << 16) | (dlyb << 20));
627 }
628 clrsetbits32(&ch[chn].phy.shu[0].b[0].dll[1],
629 0x3 << 8, (revb0 << 8) | (revb1 << 9));
630 }
631
dramc_duty_calibration(const struct sdram_params * params,u8 freq_group)632 static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group)
633 {
634 switch (params->source) {
635 case DRAMC_PARAM_SOURCE_SDRAM_CONFIG:
636 break;
637 case DRAMC_PARAM_SOURCE_FLASH:
638 dramc_dbg("bypass duty calibration\n");
639
640 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
641 dramc_duty_set_clk_delay(chn, params->duty_clk_delay[chn]);
642 dramc_duty_set_dqs_delay(chn, params->duty_dqs_delay[chn]);
643 }
644 return;
645 default:
646 die("Invalid DRAM param source %u\n", params->source);
647 return;
648 }
649
650 s8 clkDelay[CHANNEL_MAX] = {0x0};
651 s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0};
652
653 switch (freq_group) {
654 case LP4X_DDR1600:
655 clkDelay[CHANNEL_A] = 2;
656 clkDelay[CHANNEL_B] = 1;
657 dqsDelay[CHANNEL_A][0] = 0;
658 dqsDelay[CHANNEL_A][1] = 0;
659 dqsDelay[CHANNEL_B][0] = -1;
660 dqsDelay[CHANNEL_B][1] = 0;
661 break;
662 case LP4X_DDR2400:
663 clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0;
664 dqsDelay[CHANNEL_A][0] = 0;
665 dqsDelay[CHANNEL_A][1] = -2;
666 dqsDelay[CHANNEL_B][0] = 0;
667 dqsDelay[CHANNEL_B][1] = -2;
668 break;
669 case LP4X_DDR3200:
670 clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1;
671 dqsDelay[CHANNEL_A][0] = 1;
672 dqsDelay[CHANNEL_A][1] = -2;
673 dqsDelay[CHANNEL_B][0] = 1;
674 dqsDelay[CHANNEL_B][1] = -2;
675 break;
676 case LP4X_DDR3600:
677 clkDelay[CHANNEL_A] = 2;
678 clkDelay[CHANNEL_B] = 1;
679 dqsDelay[CHANNEL_A][0] = 0;
680 dqsDelay[CHANNEL_A][1] = 0;
681 dqsDelay[CHANNEL_B][0] = -1;
682 dqsDelay[CHANNEL_B][1] = 0;
683 break;
684 default:
685 die("Invalid DDR frequency group %u\n", freq_group);
686 return;
687 }
688
689 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
690 dramc_duty_set_clk_delay(chn, clkDelay[chn]);
691 dramc_duty_set_dqs_delay(chn, dqsDelay[chn]);
692 }
693 }
694
dramc_zq_calibration(u8 chn,u8 rank)695 static u8 dramc_zq_calibration(u8 chn, u8 rank)
696 {
697 const u32 TIMEOUT_US = 100;
698
699 struct reg_value regs_bak[] = {
700 {&ch[chn].ao.mrs},
701 {&ch[chn].ao.dramc_pd_ctrl},
702 {&ch[chn].ao.ckectrl},
703 };
704
705 for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
706 regs_bak[i].value = read32(regs_bak[i].addr);
707
708 setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
709 dramc_cke_fix_onoff(CKE_FIXON, chn);
710
711 SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
712 SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
713 SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 1);
714
715 if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4)) {
716 dramc_dbg("ZQCAL Start fail (time out)\n");
717 return 1;
718 }
719
720 SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 0);
721
722 udelay(1);
723 SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 1);
724
725 if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) {
726 dramc_dbg("ZQCAL Latch fail (time out)\n");
727 return 1;
728 }
729
730 SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 0);
731 udelay(1);
732 for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
733 write32(regs_bak[i].addr, regs_bak[i].value);
734
735 return 0;
736 }
737
dramc_mode_reg_init(u8 freq_group,struct mr_value * mr,const struct sdram_params * params)738 static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr,
739 const struct sdram_params *params)
740 {
741 u8 *MR01Value = mr->MR01Value;
742 u8 MR02Value[FSP_MAX] = {0x12, 0x12};
743 u8 MR03Value = 0x30;
744 u8 MR11Value[FSP_MAX] = {0x0, 0x23};
745 u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
746 {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} },
747 };
748 u8 MR13Value = 0x18;
749 u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
750 {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} },
751 };
752
753 u8 MR22Value[FSP_MAX] = {0x38, 0x34};
754 u32 cbt_mode = params->cbt_mode_extern;
755
756 MR01Value[FSP_0] = 0x6;
757 MR01Value[FSP_1] = 0x6;
758
759 if (freq_group == LP4X_DDR1600) {
760 MR02Value[0] = 0x12;
761 MR02Value[1] = 0x00;
762
763 MR01Value[FSP_0] |= (0x5 << 4);
764 MR01Value[FSP_1] |= (0x5 << 4);
765 } else if (freq_group == LP4X_DDR2400) {
766 MR02Value[0] = 0x24;
767 MR02Value[1] = 0x2d;
768
769 MR01Value[FSP_0] |= (0x5 << 4);
770 MR01Value[FSP_1] |= (0x5 << 4);
771 } else if (freq_group == LP4X_DDR3200) {
772 MR02Value[0] = 0x1a;
773 MR02Value[1] = 0x2d;
774
775 MR01Value[FSP_0] |= (0x5 << 4);
776 MR01Value[FSP_1] |= (0x5 << 4);
777 } else if (freq_group == LP4X_DDR3600) {
778 MR02Value[0] = 0x1a;
779 MR02Value[1] = 0x36;
780
781 MR01Value[FSP_0] |= (0x6 << 4);
782 MR01Value[FSP_1] |= (0x6 << 4);
783 }
784
785 if (cbt_mode)
786 MR11Value[FSP_1] = 0x13;
787
788 u8 operate_fsp = get_freq_fsq(freq_group);
789 dramc_dbg("%s operate_fsp:%d, freq:%d\n", __func__, operate_fsp, freq_group);
790
791 u8 chn, rank;
792 u32 broadcast_bak = dramc_get_broadcast();
793 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
794 dramc_power_on_sequence();
795
796 for (chn = 0; chn < CHANNEL_MAX; chn++) {
797 for (rank = 0; rank < params->rank_num; rank++) {
798 clrsetbits32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24);
799
800 dramc_zq_calibration(chn, rank);
801
802 for (uint32_t fsp = FSP_0; fsp < FSP_MAX; fsp++) {
803 dramc_dbg("chn:%d,rank:%d,fsp%d\n", chn, rank, fsp);
804
805 if (fsp == FSP_0)
806 MR13Value = (1 << 4) | (1 << 3);
807 else
808 MR13Value |= 0x40;
809 dramc_mode_reg_write(chn, 0xd, MR13Value);
810 dramc_mode_reg_write(chn, 0xc,
811 MR12Value[chn][rank][fsp]);
812 dramc_mode_reg_write(chn, 0x1, MR01Value[fsp]);
813 dramc_mode_reg_write(chn, 0x2, MR02Value[fsp]);
814 dramc_mode_reg_write(chn, 0xb, MR11Value[fsp]);
815
816 if (cbt_mode == CBT_R0_NORMAL_R1_BYTE) {
817 if (rank == 0)
818 MR22Value[FSP_1] = 0x3c;
819 else
820 MR22Value[FSP_1] = 0x34;
821 } else {
822 MR22Value[FSP_1] = 0x34;
823 }
824
825 dramc_mode_reg_write(chn, 0x16, MR22Value[fsp]);
826 dramc_mode_reg_write(chn, 0xe,
827 MR14Value[chn][rank][fsp]);
828
829 /* MR3 set write-DBI and read-DBI */
830 dramc_mode_reg_write(chn, 0x3, MR03Value);
831 }
832
833 if (operate_fsp == FSP_0)
834 MR13Value &= 0x3f;
835 else
836 MR13Value |= 0xc0;
837 dramc_mode_reg_write(chn, 0xd, MR13Value);
838 }
839
840 clrsetbits32(&ch[chn].ao.shu[0].hwset_mr13,
841 (0x1fff << 0) | (0xff << 16),
842 (13 << 0) | ((MR13Value | (0x1 << 3)) << 16));
843 clrsetbits32(&ch[chn].ao.shu[0].hwset_vrcg,
844 (0x1fff << 0) | (0xff << 16),
845 (13 << 0) | ((MR13Value | (0x1 << 3)) << 16));
846 clrsetbits32(&ch[chn].ao.shu[0].hwset_mr2,
847 (0x1fff << 0) | (0xff << 16),
848 (2 << 0) | (MR02Value[operate_fsp] << 16));
849 }
850
851 mr->MR13Value = MR13Value;
852
853 clrsetbits32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24);
854 clrsetbits32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24);
855 dramc_set_broadcast(broadcast_bak);
856 }
857
auto_refresh_cke_off(void)858 static void auto_refresh_cke_off(void)
859 {
860 u32 broadcast_bak = dramc_get_broadcast();
861 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
862
863 for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
864 setbits32(&ch[chn].ao.refctrl0, 0x1 << 29);
865
866 udelay(3);
867 dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_A);
868 dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_B);
869
870 dramc_set_broadcast(broadcast_bak);
871 }
872
dramc_setting_DDR1600(u32 cbt_mode)873 static void dramc_setting_DDR1600(u32 cbt_mode)
874 {
875 clrsetbits32(&ch[0].ao.shu[0].rankctl,
876 (0xf << 20) | (0xf << 24) | (0xf << 28),
877 (0x0 << 20) | (0x0 << 24) | (0x2 << 28));
878 clrbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24);
879 clrbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30));
880
881 clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
882 clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
883
884 clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600);
885 clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600);
886
887 if (cbt_mode)
888 clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 31), (0x1 << 31));
889 else
890 clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31),
891 (0x0 << 29) | (0x1 << 31));
892
893 clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0);
894
895 for (size_t rank = 0; rank < 2; rank++) {
896 int value = ((rank == 0) ? 0x1a : 0x1e);
897 clrbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8));
898 clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune,
899 (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
900 (value << 0) | (value << 8) | (value << 16) | (value << 24));
901
902 for (size_t b = 0; b < 2; b++) {
903 if (cbt_mode) {
904 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b],
905 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
906 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
907 (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) |
908 (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));
909 } else {
910 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b],
911 (0x7 << 8) | (0x7 << 12) |
912 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
913 (0x2 << 8) | (0x2 << 12) |
914 (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));
915 }
916 }
917 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
918 0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
919 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
920 0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
921 }
922
923 clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8),
924 (0x0 << 2) | (0x3 << 8));
925 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20);
926
927 if (cbt_mode)
928 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4),
929 (0x2 << 4));
930 else
931 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
932 (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
933 (0x2 << 4) | (0x0 << 7) | (0x0 << 13));
934
935 clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20);
936
937 if (cbt_mode == 0)
938 clrbits32(&ch[0].phy.shu[0].b[1].dq[7],
939 (0x1 << 7) | (0x1 << 13));
940
941 for (size_t r = 0; r < 2; r++) {
942 int value = ((r == 0) ? 0x1a : 0x26);
943 for (size_t b = 0; b < 2; b++)
944 clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
945 (0x3f << 8) | (0x3f << 16),
946 (value << 8) | (value << 16));
947 }
948 }
949
dramc_setting_DDR2400(u32 cbt_mode)950 static void dramc_setting_DDR2400(u32 cbt_mode)
951 {
952 clrsetbits32(&ch[0].ao.shu[0].rankctl,
953 (0xf << 20) | (0xf << 24) | (0xf << 28),
954 (0x2 << 20) | (0x2 << 24) | (0x4 << 28));
955 clrsetbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24);
956 setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
957
958 setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
959 setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
960
961 clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400);
962 clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400);
963
964 if (cbt_mode)
965 clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 31), (0x0 << 31));
966 else
967 clrsetbits32(&ch[0].ao.shu[0].wodt,
968 (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31));
969
970 clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0);
971
972 for (size_t rank = 0; rank < 2; rank++) {
973 int value = ((rank == 0) ? 0x19 : 0x1f);
974 clrsetbits32(&ch[0].ao.shu[0].rk[rank].dqsien,
975 (0x7f << 0) | (0x7f << 8), (value << 0) | (value << 8));
976 clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune,
977 (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
978 (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24));
979
980 for (size_t b = 0; b < 2; b++) {
981 if (cbt_mode) {
982 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b],
983 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
984 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
985 (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |
986 (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
987 } else {
988 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b],
989 (0x7 << 8) | (0x7 << 12) |
990 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
991 (0x3 << 8) | (0x3 << 12) |
992 (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
993 }
994 }
995 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
996 0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
997 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
998 0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
999 }
1000
1001 clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
1002 (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8));
1003 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20);
1004
1005 if (cbt_mode)
1006 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
1007 (0x3 << 4), (0x1 << 4));
1008 else
1009 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
1010 (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
1011 (0x1 << 4) | (0x1 << 7) | (0x1 << 13));
1012
1013 clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20);
1014
1015 if (cbt_mode == 0)
1016 setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13));
1017
1018 for (size_t r = 0; r < 2; r++) {
1019 for (size_t b = 0; b < 2; b++)
1020 clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
1021 (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16));
1022 }
1023 }
1024
dramc_setting_DDR3600(void)1025 static void dramc_setting_DDR3600(void)
1026 {
1027 clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600);
1028 clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600);
1029 }
1030
dramc_setting(const struct sdram_params * params,u8 freq_group,const struct dram_impedance * impedance)1031 static void dramc_setting(const struct sdram_params *params, u8 freq_group,
1032 const struct dram_impedance *impedance)
1033 {
1034 u8 chn;
1035
1036 auto_refresh_cke_off();
1037 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1038
1039 for (chn = 0; chn < CHANNEL_MAX; chn++)
1040 setbits32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1));
1041
1042 dramc_set_broadcast(DRAMC_BROADCAST_ON);
1043
1044 setbits32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0);
1045
1046 /* 26M */
1047 clrbits32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4);
1048 clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 17);
1049
1050 clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
1051 write32(&ch[0].phy.misc_spm_ctrl2, 0x0);
1052 write32(&ch[0].phy.misc_spm_ctrl0, 0x0);
1053 write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf);
1054 write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00);
1055 setbits32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1));
1056 clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0);
1057 clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0);
1058
1059 for (size_t b = 0; b <= 2; b += 2)
1060 clrsetbits32(&ch[0].phy.shu[0].pll[4 + b],
1061 (0x3 << 18) | (0x3 << 24) | (0x3 << 26),
1062 (0x2 << 18) | (0x1 << 24) | (0x1 << 26));
1063
1064 clrbits32(&ch[0].phy.shu[0].pll[14], 0x1 << 1);
1065 clrbits32(&ch[0].phy.shu[0].pll20, 0x1 << 1);
1066 clrbits32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20));
1067 for (size_t b = 0; b < 2; b++)
1068 clrbits32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20));
1069 for (size_t b = 0; b < 2; b++)
1070 clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28);
1071 clrbits32(&ch[0].phy.ca_cmd[10], 0x7 << 28);
1072
1073 setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
1074 setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
1075 setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9);
1076 setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9);
1077
1078 for (size_t b = 0; b < 2; b++) {
1079 for (size_t r = 0; r < 2; r++)
1080 setbits32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29);
1081 clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20);
1082
1083 for (size_t r = 0; r < 2; r++) {
1084 clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[1],
1085 (0xffff << 0) | (0xffff << 16), (0x2 << 0) | (0x2 << 16));
1086 clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
1087 (0x1 << 23) | (0x1 << 28) | (0x3 << 30),
1088 (0x1 << 23) | (0x1 << 28) | (0x2 << 30));
1089 }
1090 }
1091
1092 clrbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
1093 clrbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
1094
1095 for (size_t b = 0; b < 2; b++) {
1096 setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 0);
1097 for (size_t r = 0; r < 2; r++)
1098 clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
1099 (0x3f << 8) | (0x3f << 16), (0x1f << 8) | (0x1f << 16));
1100
1101 clrsetbits32(&ch[0].phy.b[b].dq[4],
1102 (0x7f << 0) | (0x7f << 8), (0x10 << 0) | (0x10 << 8));
1103 clrsetbits32(&ch[0].phy.b[b].dq[5],
1104 (0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) | (0x1 << 24),
1105 (0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) | (0x0 << 24));
1106 clrsetbits32(&ch[0].phy.b[b].dq[6],
1107 (0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) |
1108 (0xf << 16) | (0x1 << 24),
1109 (0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) |
1110 (0x3 << 16) | (0x1 << 24));
1111 clrsetbits32(&ch[0].phy.b[b].dq[5],
1112 (0xff << 0) | (0x1 << 25), (0x0 << 0) | (0x1 << 25));
1113 }
1114
1115 setbits32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7));
1116 clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16),
1117 (0x0 << 6) | (0x0 << 14) | (0x0 << 16));
1118
1119 clrbits32(&ch[0].phy.pll3, 0x1 << 0);
1120 setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3);
1121 setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
1122
1123 udelay(1);
1124 clrsetbits32(&ch[0].phy.shu[0].pll[8],
1125 (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
1126
1127 udelay(1);
1128 clrbits32(&ch[0].phy.shu[0].pll[9],
1129 (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));
1130 clrbits32(&ch[0].phy.shu[0].pll[11],
1131 (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));
1132 udelay(1);
1133
1134 clrsetbits32(&ch[0].phy.shu[0].pll[10],
1135 (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
1136 udelay(1);
1137
1138 /* PLL EN */
1139 /* MID FINE_TUNE Init 1 */
1140 clrsetbits32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18);
1141
1142 udelay(1);
1143 clrsetbits32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0);
1144
1145 udelay(1);
1146 setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
1147
1148 for (size_t b = 0; b < 2; b++)
1149 setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10));
1150
1151 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1152 setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0);
1153 setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0);
1154 dramc_set_broadcast(DRAMC_BROADCAST_ON);
1155
1156 for (size_t b = 0; b < 2; b++)
1157 clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0],
1158 (0x1 << 4) | (0x3 << 9) | (0xf << 12) |
1159 (0xf << 16) | (0xf << 20) | (0x1 << 30),
1160 (0x0 << 4) | (0x3 << 9) | (0x8 << 12) |
1161 (0x7 << 16) | (0x7 << 20) | (0x1 << 30));
1162
1163 clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0);
1164 clrsetbits32(&ch[0].phy.shu[0].ca_cmd[0],
1165 (0x1 << 4) | (0x7 << 12) | (0x1 << 20),
1166 (0x1 << 4) | (0x4 << 12) | (0x1 << 20));
1167
1168 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1169 clrsetbits32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6);
1170 clrsetbits32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6);
1171 dramc_set_broadcast(DRAMC_BROADCAST_ON);
1172
1173 for (size_t b = 0; b < 2; b++)
1174 clrsetbits32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6);
1175
1176 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1177 for (chn = 0; chn < CHANNEL_MAX; chn++)
1178 clrsetbits32(&ch[chn].phy.misc_shu_opt,
1179 (0x1 << 0) | (0x3 << 2) | (0x1 << 8) |
1180 (0x3 << 10) | (0x1 << 16) | (0x3 << 18),
1181 (0x1 << 0) | (0x2 << 2) | (0x1 << 8) |
1182 (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18));
1183
1184 udelay(9);
1185 clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2);
1186 clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0);
1187 dramc_set_broadcast(DRAMC_BROADCAST_ON);
1188
1189 for (size_t b = 0; b < 2; b++)
1190 clrsetbits32(&ch[0].phy.shu[0].b[b].dll[1],
1191 (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2));
1192 udelay(1);
1193
1194 clrbits32(&ch[0].phy.pll2, 0x1 << 31);
1195 clrsetbits32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf);
1196 udelay(1);
1197
1198 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1199 ddr_phy_reserved_rg_setting(freq_group);
1200 for (chn = 0; chn < CHANNEL_MAX; chn++)
1201 ddr_phy_pll_setting(chn, freq_group);
1202
1203 dramc_set_broadcast(DRAMC_BROADCAST_ON);
1204 setbits32(&ch[0].ao.drsctrl, 0x1 << 29);
1205
1206 /* Set Run time MRR CKE fix to 1 in tMRRI old mode
1207 * to avoid no ACK from precharge all */
1208 setbits32(&ch[0].ao.ckectrl, 0x1 << 27);
1209 clrsetbits32(&ch[0].ao.dramctrl,
1210 (0x1 << 15) | (0x1 << 17) | (0x1 << 23),
1211 (0x0 << 15) | (0x1 << 17) | (0x1 << 23));
1212 setbits32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
1213 setbits32(&ch[0].phy.b[0].dq[9], 0x1 << 4);
1214 setbits32(&ch[0].phy.b[1].dq[9], 0x1 << 4);
1215
1216 clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien,
1217 (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),
1218 (0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24));
1219 clrsetbits32(&ch[0].ao.stbcal1,
1220 (0x1 << 4) | (0x1 << 8) | (0x1 << 12), (0x1 << 4) | (0x1 << 8));
1221 clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
1222 (0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31),
1223 (0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31));
1224
1225 for (size_t i = 0; i < 4; i++) {
1226 clrsetbits32(&ch[0].ao.shu[0].drving[i],
1227 (0x1f << 0) | (0x1f << 5) | (0x1f << 10) |
1228 (0x1f << 15) | (0x1f << 20) | (0x1f << 25),
1229 (0xa << 0) | (0xa << 5) | (0xa << 10) |
1230 (0xa << 15) | (0xa << 20) | (0xa << 25));
1231 }
1232
1233 clrsetbits32(&ch[0].ao.shuctrl2,
1234 (0x3f << 0) | (0x1 << 12) | (0x1 << 14) |
1235 (0x1 << 15) | (0xff << 16) | (0x1 << 24),
1236 (0xa << 0) | (0x1 << 12) | (0x1 << 14) |
1237 (0x1 << 15) | (0x1 << 16) | (0x0 << 24));
1238 setbits32(&ch[0].ao.dvfsdll, 0x1 << 0);
1239 setbits32(&ch[0].ao.ddrconf0,
1240 (0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26));
1241 setbits32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28));
1242 clrbits32(&ch[0].ao.stbcal2, 0x1 << 29);
1243 setbits32(&ch[0].ao.clkar, 0x1 << 19);
1244
1245 for (size_t b = 0; b < 2; b++)
1246 clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20);
1247 clrsetbits32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20);
1248 setbits32(&ch[0].phy.misc_ctrl0,
1249 (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31));
1250
1251 setbits32(&ch[0].phy.misc_ctrl1,
1252 (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24));
1253 clrsetbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24);
1254 clrsetbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24);
1255 clrsetbits32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24);
1256 clrbits32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6));
1257 clrbits32(&ch[0].phy.b[0].dq[7], 0x1 << 6);
1258 clrbits32(&ch[0].phy.b[1].dq[7], 0x1 << 6);
1259
1260 clrsetbits32(&ch[0].ao.shu[0].conf[0],
1261 (0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) |
1262 (0x1 << 29) | (0x3 << 30),
1263 (0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) |
1264 (0x1 << 29) | (0x2 << 30));
1265 clrsetbits32(&ch[0].ao.shu[0].odtctrl,
1266 (0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) | (0x1 << 31),
1267 (0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) | (0x1 << 31));
1268 setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
1269 setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
1270
1271 clrsetbits32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24);
1272 clrbits32(&ch[0].ao.shu[0].selph_ca1,
1273 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
1274 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
1275 clrsetbits32(&ch[0].ao.shu[0].selph_ca2,
1276 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) | (0x7 << 24),
1277 (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) | (0x0 << 24));
1278 clrbits32(&ch[0].ao.shu[0].selph_ca3,
1279 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
1280 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
1281 clrbits32(&ch[0].ao.shu[0].selph_ca4,
1282 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
1283 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
1284 clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8);
1285 clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200);
1286 clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200);
1287
1288 for (size_t rank = 0; rank < 2; rank++) {
1289 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
1290 0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
1291 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
1292 0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
1293 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
1294 0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
1295 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
1296 0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
1297 }
1298
1299 for (int b = 0; b < 2; b++) {
1300 clrsetbits32(&ch[0].phy.shu[0].rk[0].b[b].dq[7],
1301 (0x3f << 8) | (0x3f << 16), (0x1a << 8) | (0x1a << 16));
1302 clrsetbits32(&ch[0].phy.shu[0].rk[1].b[b].dq[7],
1303 (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16));
1304 }
1305 udelay(1);
1306
1307 for (size_t b = 0; b < 2; b++) {
1308 setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
1309 clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14);
1310 }
1311 setbits32(&ch[0].ao.stbcal, 0x1 << 31);
1312 clrsetbits32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24);
1313 clrsetbits32(&ch[0].ao.shu[0].ckectrl,
1314 (0x3 << 24) | (0x3 << 28), (0x3 << 24) | (0x3 << 28));
1315 setbits32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31));
1316 setbits32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31));
1317 setbits32(&ch[0].ao.rkcfg, 0x1 << 2);
1318 clrsetbits32(&ch[0].ao.shu[0].conf[2],
1319 (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28));
1320 clrsetbits32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26);
1321 clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0);
1322
1323 setbits32(&ch[0].ao.shuctrl, 0x1 << 16);
1324 clrbits32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6));
1325 clrsetbits32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23),
1326 (0x1 << 15) | (0x0 << 23));
1327 clrbits32(&ch[0].ao.dramctrl, 0x1 << 9);
1328 setbits32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31));
1329 setbits32(&ch[0].ao.perfctl0,
1330 (0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) |
1331 (0x1 << 9) | (0x1 << 10) | (0x1 << 11) | (0x1 << 14) | (0x1 << 17));
1332 clrsetbits32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0);
1333 clrsetbits32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3));
1334 setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8);
1335 setbits32(&ch[0].ao.clkctrl, 0x1 << 29);
1336 clrsetbits32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12));
1337 clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28),
1338 (0x4 << 20) | (0x4 << 24) | (0x6 << 28));
1339 udelay(2);
1340
1341 if (params->cbt_mode_extern == CBT_R0_R1_NORMAL) {
1342 clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien,
1343 (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8));
1344 clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien,
1345 (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),
1346 (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24));
1347 }
1348
1349 setbits32(&ch[0].ao.dramctrl, 0x1 << 19);
1350 clrsetbits32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0);
1351 udelay(1);
1352
1353 clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16);
1354 setbits32(&ch[0].ao.refctrl0, 0x1 << 30);
1355 setbits32(&ch[0].ao.srefctrl, 0x1 << 30);
1356 setbits32(&ch[0].ao.mpc_option, 0x1 << 17);
1357 setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30);
1358 setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0);
1359 clrsetbits32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16));
1360 setbits32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11));
1361 clrsetbits32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4);
1362 clrsetbits32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4);
1363 clrsetbits32(&ch[0].ao.test2_3,
1364 (0x1 << 7) | (0x7 << 8) | (0x1 << 28),
1365 (0x1 << 7) | (0x4 << 8) | (0x1 << 28));
1366 clrbits32(&ch[0].ao.rstmask, 0x1 << 29);
1367 clrbits32(&ch[0].ao.rstmask, 0x1 << 30);
1368
1369 udelay(1);
1370 clrsetbits32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4));
1371
1372 if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) {
1373 clrsetbits32(&ch[0].ao.perfctl0,
1374 (0x1 << 18) | (0x1 << 19) | (0x1 << 27),
1375 (0x0 << 18) | (0x1 << 19) | (0x1 << 27));
1376 clrbits32(&ch[0].ao.rstmask, 0x1 << 28);
1377 setbits32(&ch[0].ao.rkcfg, 0x1 << 11);
1378 setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28);
1379 setbits32(&ch[0].ao.eyescan, 0x1 << 2);
1380 } else {
1381 clrbits32(&ch[0].ao.dramctrl, 0x1 << 0);
1382 clrsetbits32(&ch[0].ao.perfctl0,
1383 (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19));
1384 setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28);
1385 clrbits32(&ch[0].ao.rstmask, 0x1 << 28);
1386 setbits32(&ch[0].ao.rkcfg, 0x1 << 11);
1387 setbits32(&ch[0].ao.mpc_option, 0x1 << 17);
1388 setbits32(&ch[0].ao.eyescan, 0x1 << 2);
1389 setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29);
1390 setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7);
1391 setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7);
1392 clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20);
1393
1394 for (size_t r = 0; r < 2; r++)
1395 for (size_t b = 0; b < 2; b++)
1396 clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[b],
1397 (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4));
1398 }
1399
1400 udelay(5);
1401
1402 clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16);
1403 clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16);
1404 clrsetbits32(&ch[0].ao.stbcal,
1405 (0x1 << 0) | (0x1 << 22) | (0x1 << 24) | (0x1 << 26) | (0x1 << 27),
1406 (0x1 << 0) | (0x0 << 22) | (0x0 << 24) | (0x1 << 26) | (0x1 << 27));
1407 setbits32(&ch[0].ao.stbcal1, 0x1 << 6);
1408 clrsetbits32(&ch[0].ao.shu[0].dqsg,
1409 (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12));
1410 clrbits32(&ch[0].phy.misc_ctrl0, 0xf << 0);
1411 setbits32(&ch[0].ao.shu[0].stbcal, 0x1 << 8);
1412 setbits32(&ch[0].ao.stbcal, 0x1 << 17);
1413 clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14);
1414 clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14);
1415 clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4);
1416
1417 if (freq_group == LP4X_DDR1600)
1418 clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0);
1419 else
1420 clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0);
1421 setbits32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5));
1422 setbits32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27));
1423 clrbits32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26));
1424 clrsetbits32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4);
1425 udelay(12);
1426
1427 if (params->cbt_mode_extern != CBT_R0_R1_NORMAL)
1428 clrsetbits32(&ch[0].ao.shu[0].rankctl,
1429 (0xf << 20) | (0xf << 24) | (0xf << 28),
1430 (0x3 << 20) | (0x3 << 24) | (0x5 << 28));
1431 else
1432 clrsetbits32(&ch[0].ao.shu[0].rankctl,
1433 (0xf << 24) | (0xf << 28),
1434 (0x4 << 24) | (0x6 << 28));
1435
1436 clrbits32(&ch[0].ao.shu[0].wodt, 0x1 << 31);
1437
1438 if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) {
1439 clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien,
1440 (0x7f << 0) | (0x7f << 8),
1441 (0x19 << 0) | (0x19 << 8));
1442 clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien,
1443 (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),
1444 (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24));
1445 }
1446
1447 clrsetbits32(&ch[0].ao.shu[0].rk[0].fine_tune,
1448 (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
1449 (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24));
1450 clrsetbits32(&ch[0].ao.shu[0].rk[1].fine_tune,
1451 (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
1452 (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24));
1453 for (u8 rank = 0; rank < 2; rank++) {
1454 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
1455 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
1456 (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));
1457 clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
1458 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
1459 (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));
1460 }
1461 clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
1462 (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24),
1463 (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24));
1464
1465 if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) {
1466 setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12));
1467 setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12));
1468 } else {
1469 setbits32(&ch[0].phy.shu[0].b[0].dq[7],
1470 (0x1 << 12) | (0x1 << 13));
1471 setbits32(&ch[0].phy.shu[0].b[1].dq[7],
1472 (0x1 << 12) | (0x1 << 13));
1473 }
1474 clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0);
1475
1476 /* The default dramc init settings were tuned at frequency of 3200Mbps.
1477 For other frequencies uses dramc_setting_DDRxxx() to overwrite
1478 the default settings. */
1479 switch (freq_group) {
1480 case LP4X_DDR1600:
1481 dramc_setting_DDR1600(params->cbt_mode_extern);
1482 break;
1483 case LP4X_DDR2400:
1484 dramc_setting_DDR2400(params->cbt_mode_extern);
1485 break;
1486 case LP4X_DDR3200:
1487 /* Do nothing */
1488 break;
1489 case LP4X_DDR3600:
1490 dramc_setting_DDR3600();
1491 break;
1492 default:
1493 die("Invalid DDR frequency group %u\n", freq_group);
1494 return;
1495 }
1496
1497 update_initial_settings(freq_group);
1498 dramc_sw_impedance_save_reg(freq_group, impedance);
1499
1500 clrbits32(&ch[0].ao.test2_4, 0x1 << 17);
1501 clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0);
1502 udelay(1);
1503
1504 setbits32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18));
1505 setbits32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25));
1506 setbits32(&ch[0].ao.refctrl0, 0x1 << 29);
1507 setbits32(&ch[0].ao.dramctrl, 0x1 << 26);
1508 clrsetbits32(&ch[0].ao.dummy_rd,
1509 (0x1 << 4) | (0x1 << 11) | (0x1 << 13) |
1510 (0x1 << 14) | (0x3 << 16) | (0x1 << 22),
1511 (0x1 << 4) | (0x1 << 11) | (0x1 << 13) |
1512 (0x1 << 14) | (params->rank_num << 16) | (0x1 << 22));
1513 clrsetbits32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28);
1514 clrbits32(&ch[0].ao.dramctrl, 0x1 << 0);
1515 udelay(1);
1516
1517 dramc_set_broadcast(DRAMC_BROADCAST_OFF);
1518 clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17));
1519 setbits32(&ch[0].ao.shuctrl2, 0x1 << 12);
1520 clrsetbits32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17));
1521 clrbits32(&ch[1].ao.shuctrl2, 0x1 << 12);
1522 }
1523
1524 struct ac_time {
1525 u8 dqsinctl;
1526 u8 datlat;
1527 u8 trcd;
1528 u8 trrd;
1529 u8 twr;
1530 u8 twtr;
1531 u8 trc;
1532 u8 tras;
1533 u8 trp;
1534 u8 trpab;
1535 u8 tfaw;
1536 u8 trtw_odt_on;
1537 u8 trtp;
1538 u8 txp;
1539 u8 refcnt;
1540 u8 trfc;
1541 u8 trfcpb;
1542 u8 tzqcs;
1543 u8 refcnt_fr_clk;
1544 u8 txrefcnt;
1545 u8 tmrr2w_odt_on;
1546 u8 twtpd;
1547 u8 trtpd;
1548 u8 xrtw2w;
1549 u8 xrtw2r;
1550 u8 xrtr2w;
1551 u8 xrtr2r;
1552 u8 twtr_05T;
1553 u8 trtw_odt_on_05T;
1554 u8 twtpd_05T;
1555 u8 trtpd_05T;
1556 u8 tfaw_05T;
1557 u8 trrd_05T;
1558 u8 twr_05T;
1559 u8 tras_05T;
1560 u8 trpab_05T;
1561 u8 trp_05T;
1562 u8 trcd_05T;
1563 u8 trtp_05T;
1564 u8 txp_05T;
1565 u8 trfc_05T;
1566 u8 trfcpb_05T;
1567 u8 trc_05T;
1568 u8 r_dmcatrain_intv;
1569 u8 r_dmmrw_intv;
1570 u8 r_dmfspchg_prdcnt;
1571 u8 ckeprd;
1572 u8 ckelckcnt;
1573 u8 zqlat2;
1574 };
1575
1576 static const struct ac_time ac_timing_tbl[LP4X_DDRFREQ_MAX] = {
1577 /* LP4x-1600, 800MHz, RDBI_OFF, normal mode */
1578 [LP4X_DDR1600] = {
1579 .tras = 0, .tras_05T = 0,
1580 .trp = 2, .trp_05T = 0,
1581 .trpab = 0, .trpab_05T = 1,
1582 .trc = 4, .trc_05T = 0,
1583 .trfc = 44, .trfc_05T = 0,
1584 .trfcpb = 16, .trfcpb_05T = 0,
1585 .txp = 0, .txp_05T = 0,
1586 .trtp = 1, .trtp_05T = 1,
1587 .trcd = 3, .trcd_05T = 0,
1588 .twr = 7, .twr_05T = 1,
1589 .twtr = 4, .twtr_05T = 1,
1590 .trrd = 0, .trrd_05T = 0,
1591 .tfaw = 0, .tfaw_05T = 0,
1592 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
1593 .refcnt = 48,
1594 .refcnt_fr_clk = 101,
1595 .txrefcnt = 62,
1596 .tzqcs = 16,
1597 .xrtw2w = 5,
1598 .xrtw2r = 3,
1599 .xrtr2w = 3,
1600 .xrtr2r = 8,
1601 .r_dmcatrain_intv = 8,
1602 .r_dmmrw_intv = 0xf,
1603 .r_dmfspchg_prdcnt = 50,
1604 .trtpd = 6, .trtpd_05T = 0,
1605 .twtpd = 6, .twtpd_05T = 0,
1606 .tmrr2w_odt_on = 5,
1607 .ckeprd = 1,
1608 .ckelckcnt = 0,
1609 .zqlat2 = 6,
1610 .dqsinctl = 1, .datlat = 10,
1611 },
1612 /* LP4x-2400, 1200MHz, RDBI_OFF, normal mode */
1613 [LP4X_DDR2400] = {
1614 .tras = 4, .tras_05T = 1,
1615 .trp = 3, .trp_05T = 1,
1616 .trpab = 1, .trpab_05T = 0,
1617 .trc = 10, .trc_05T = 0,
1618 .trfc = 72, .trfc_05T = 0,
1619 .trfcpb = 30, .trfcpb_05T = 0,
1620 .txp = 0, .txp_05T = 1,
1621 .trtp = 1, .trtp_05T = 0,
1622 .trcd = 4, .trcd_05T = 1,
1623 .twr = 10, .twr_05T = 1,
1624 .twtr = 6, .twtr_05T = 1,
1625 .trrd = 1, .trrd_05T = 0,
1626 .tfaw = 3, .tfaw_05T = 0,
1627 .trtw_odt_on = 7, .trtw_odt_on_05T = 0,
1628 .refcnt = 73,
1629 .refcnt_fr_clk = 101,
1630 .txrefcnt = 91,
1631 .tzqcs = 25,
1632 .xrtw2w = 5,
1633 .xrtw2r = 3,
1634 .xrtr2w = 6,
1635 .xrtr2r = 8,
1636 .r_dmcatrain_intv = 9,
1637 .r_dmmrw_intv = 0xf,
1638 .r_dmfspchg_prdcnt = 75,
1639 .trtpd = 9, .trtpd_05T = 0,
1640 .twtpd = 9, .twtpd_05T = 0,
1641 .tmrr2w_odt_on = 8,
1642 .ckeprd = 2,
1643 .ckelckcnt = 0,
1644 .zqlat2 = 9,
1645 .dqsinctl = 3, .datlat = 13,
1646 },
1647 /* LP4x-3200, 1600MHz, RDBI_OFF, normal mode */
1648 [LP4X_DDR3200] = {
1649 .tras = 8, .tras_05T = 1,
1650 .trp = 5, .trp_05T = 1,
1651 .trpab = 1, .trpab_05T = 0,
1652 .trc = 16, .trc_05T = 1,
1653 .trfc = 100, .trfc_05T = 0,
1654 .trfcpb = 44, .trfcpb_05T = 0,
1655 .txp = 1, .txp_05T = 0,
1656 .trtp = 2, .trtp_05T = 1,
1657 .trcd = 6, .trcd_05T = 1,
1658 .twr = 12, .twr_05T = 1,
1659 .twtr = 7, .twtr_05T = 0,
1660 .trrd = 2, .trrd_05T = 0,
1661 .tfaw = 7, .tfaw_05T = 0,
1662 .trtw_odt_on = 7, .trtw_odt_on_05T = 0,
1663 .refcnt = 97,
1664 .refcnt_fr_clk = 101,
1665 .txrefcnt = 119,
1666 .tzqcs = 34,
1667 .xrtw2w = 5,
1668 .xrtw2r = 3,
1669 .xrtr2w = 6,
1670 .xrtr2r = 9,
1671 .r_dmcatrain_intv = 11,
1672 .r_dmmrw_intv = 0xf,
1673 .r_dmfspchg_prdcnt = 100,
1674 .trtpd = 11, .trtpd_05T = 0,
1675 .twtpd = 12, .twtpd_05T = 1,
1676 .tmrr2w_odt_on = 10,
1677 .ckeprd = 2,
1678 .ckelckcnt = 0,
1679 .zqlat2 = 12,
1680 .dqsinctl = 4, .datlat = 15,
1681 },
1682 /* LP4x-3600, 1800MHz, RDBI_OFF, normal mode */
1683 [LP4X_DDR3600] = {
1684 .tras = 11, .tras_05T = 1,
1685 .trp = 6, .trp_05T = 1,
1686 .trpab = 1, .trpab_05T = 1,
1687 .trc = 20, .trc_05T = 1,
1688 .trfc = 118, .trfc_05T = 1,
1689 .trfcpb = 53, .trfcpb_05T = 1,
1690 .txp = 1, .txp_05T = 1,
1691 .trtp = 2, .trtp_05T = 0,
1692 .trcd = 7, .trcd_05T = 1,
1693 .twr = 14, .twr_05T = 1,
1694 .twtr = 8, .twtr_05T = 0,
1695 .trrd = 3, .trrd_05T = 0,
1696 .tfaw = 10, .tfaw_05T = 0,
1697 .trtw_odt_on = 8, .trtw_odt_on_05T = 0,
1698 .refcnt = 113,
1699 .refcnt_fr_clk = 101,
1700 .txrefcnt = 138,
1701 .tzqcs = 40,
1702 .xrtw2w = 5,
1703 .xrtw2r = 3,
1704 .xrtr2w = 7,
1705 .xrtr2r = 9,
1706 .r_dmcatrain_intv = 13,
1707 .r_dmmrw_intv = 0xf,
1708 .r_dmfspchg_prdcnt = 117,
1709 .trtpd = 12, .trtpd_05T = 0,
1710 .twtpd = 13, .twtpd_05T = 0,
1711 .tmrr2w_odt_on = 11,
1712 .ckeprd = 3,
1713 .ckelckcnt = 0,
1714 .zqlat2 = 14,
1715 .dqsinctl = 6, .datlat = 18,
1716 },
1717 };
1718
1719 static const struct ac_time ac_timing_cbt_tbl[LP4X_DDRFREQ_MAX] = {
1720 /* LP4x-1600, 800MHz, RDBI_OFF, byte mode */
1721 [LP4X_DDR1600] = {
1722 .tras = 0, .tras_05T = 0,
1723 .trp = 2, .trp_05T = 0,
1724 .trpab = 0, .trpab_05T = 1,
1725 .trc = 4, .trc_05T = 0,
1726 .trfc = 44, .trfc_05T = 0,
1727 .trfcpb = 16, .trfcpb_05T = 0,
1728 .txp = 0, .txp_05T = 0,
1729 .trtp = 1, .trtp_05T = 1,
1730 .trcd = 3, .trcd_05T = 0,
1731 .twr = 7, .twr_05T = 0,
1732 .twtr = 4, .twtr_05T = 0,
1733 .trrd = 0, .trrd_05T = 0,
1734 .tfaw = 0, .tfaw_05T = 0,
1735 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
1736 .refcnt = 48,
1737 .refcnt_fr_clk = 101,
1738 .txrefcnt = 62,
1739 .tzqcs = 16,
1740 .xrtw2w = 5,
1741 .xrtw2r = 3,
1742 .xrtr2w = 3,
1743 .xrtr2r = 8,
1744 .r_dmcatrain_intv = 8,
1745 .r_dmmrw_intv = 0xf,
1746 .r_dmfspchg_prdcnt = 50,
1747 .trtpd = 7, .trtpd_05T = 0,
1748 .twtpd = 7, .twtpd_05T = 1,
1749 .tmrr2w_odt_on = 6,
1750 .ckeprd = 1,
1751 .ckelckcnt = 0,
1752 .zqlat2 = 6,
1753 .dqsinctl = 2, .datlat = 11,
1754 },
1755 /* LP4x-2400, 1200MHz, RDBI_OFF, byte mode */
1756 [LP4X_DDR2400] = {
1757 .tras = 4, .tras_05T = 1,
1758 .trp = 3, .trp_05T = 1,
1759 .trpab = 1, .trpab_05T = 0,
1760 .trc = 10, .trc_05T = 0,
1761 .trfc = 72, .trfc_05T = 0,
1762 .trfcpb = 30, .trfcpb_05T = 0,
1763 .txp = 0, .txp_05T = 1,
1764 .trtp = 1, .trtp_05T = 0,
1765 .trcd = 4, .trcd_05T = 1,
1766 .twr = 10, .twr_05T = 1,
1767 .twtr = 6, .twtr_05T = 1,
1768 .trrd = 1, .trrd_05T = 0,
1769 .tfaw = 3, .tfaw_05T = 0,
1770 .trtw_odt_on = 7, .trtw_odt_on_05T = 0,
1771 .refcnt = 73,
1772 .refcnt_fr_clk = 101,
1773 .txrefcnt = 91,
1774 .tzqcs = 25,
1775 .xrtw2w = 5,
1776 .xrtw2r = 3,
1777 .xrtr2w = 6,
1778 .xrtr2r = 8,
1779 .r_dmcatrain_intv = 9,
1780 .r_dmmrw_intv = 0xf,
1781 .r_dmfspchg_prdcnt = 75,
1782 .trtpd = 10, .trtpd_05T = 0,
1783 .twtpd = 10, .twtpd_05T = 0,
1784 .tmrr2w_odt_on = 9,
1785 .ckeprd = 2,
1786 .ckelckcnt = 0,
1787 .zqlat2 = 9,
1788 .dqsinctl = 4, .datlat = 14,
1789 },
1790 /* LP4x-3200, 1600MHz, RDBI_OFF, byte mode */
1791 [LP4X_DDR3200] = {
1792 .tras = 8, .tras_05T = 1,
1793 .trp = 5, .trp_05T = 1,
1794 .trpab = 1, .trpab_05T = 0,
1795 .trc = 16, .trc_05T = 1,
1796 .trfc = 100, .trfc_05T = 0,
1797 .trfcpb = 44, .trfcpb_05T = 0,
1798 .txp = 1, .txp_05T = 0,
1799 .trtp = 2, .trtp_05T = 1,
1800 .trcd = 6, .trcd_05T = 1,
1801 .twr = 13, .twr_05T = 1,
1802 .twtr = 8, .twtr_05T = 0,
1803 .trrd = 2, .trrd_05T = 0,
1804 .tfaw = 7, .tfaw_05T = 0,
1805 .trtw_odt_on = 8, .trtw_odt_on_05T = 0,
1806 .refcnt = 97,
1807 .refcnt_fr_clk = 101,
1808 .txrefcnt = 119,
1809 .tzqcs = 34,
1810 .xrtw2w = 5,
1811 .xrtw2r = 3,
1812 .xrtr2w = 7,
1813 .xrtr2r = 9,
1814 .r_dmcatrain_intv = 11,
1815 .r_dmmrw_intv = 0xf,
1816 .r_dmfspchg_prdcnt = 100,
1817 .trtpd = 12, .trtpd_05T = 0,
1818 .twtpd = 12, .twtpd_05T = 0,
1819 .tmrr2w_odt_on = 11,
1820 .ckeprd = 2,
1821 .ckelckcnt = 0,
1822 .zqlat2 = 12,
1823 .dqsinctl = 5, .datlat = 16,
1824 },
1825 /* LP4x-3600, 1800MHz, RDBI_OFF, byte mode */
1826 [LP4X_DDR3600] = {
1827 .tras = 11, .tras_05T = 1,
1828 .trp = 6, .trp_05T = 1,
1829 .trpab = 1, .trpab_05T = 1,
1830 .trc = 20, .trc_05T = 1,
1831 .trfc = 118, .trfc_05T = 1,
1832 .trfcpb = 53, .trfcpb_05T = 1,
1833 .txp = 1, .txp_05T = 1,
1834 .trtp = 2, .trtp_05T = 0,
1835 .trcd = 7, .trcd_05T = 1,
1836 .twr = 15, .twr_05T = 1,
1837 .twtr = 9, .twtr_05T = 0,
1838 .trrd = 3, .trrd_05T = 0,
1839 .tfaw = 10, .tfaw_05T = 0,
1840 .trtw_odt_on = 9, .trtw_odt_on_05T = 0,
1841 .refcnt = 113,
1842 .refcnt_fr_clk = 101,
1843 .txrefcnt = 138,
1844 .tzqcs = 40,
1845 .xrtw2w = 5,
1846 .xrtw2r = 3,
1847 .xrtr2w = 8,
1848 .xrtr2r = 9,
1849 .r_dmcatrain_intv = 13,
1850 .r_dmmrw_intv = 0xf,
1851 .r_dmfspchg_prdcnt = 117,
1852 .trtpd = 13, .trtpd_05T = 0,
1853 .twtpd = 14, .twtpd_05T = 0,
1854 .tmrr2w_odt_on = 10,
1855 .ckeprd = 3,
1856 .ckelckcnt = 0,
1857 .zqlat2 = 14,
1858 .dqsinctl = 7, .datlat = 17,
1859 },
1860 };
1861
ddr_update_ac_timing(u8 freq_group,u32 cbt_mode)1862 static void ddr_update_ac_timing(u8 freq_group, u32 cbt_mode)
1863 {
1864 struct ac_time ac_t;
1865 u32 temp, r2w_odt_onoff = ODT_ON;
1866 u8 new_datlat;
1867 u8 root = 0, tx_rank_inctl = 0, tx_dly = 0;
1868 u8 trtw = 0, trtw_05t = 0, tmrr2w = 0;
1869
1870 if (cbt_mode)
1871 memcpy(&ac_t, &ac_timing_cbt_tbl[freq_group], sizeof(struct ac_time));
1872 else
1873 memcpy(&ac_t, &ac_timing_tbl[freq_group], sizeof(struct ac_time));
1874
1875 new_datlat = ac_t.datlat - 2;
1876
1877 if (freq_group == LP4X_DDR1600) {
1878 root = 0; tx_rank_inctl = 0; tx_dly = 1;
1879 } else {
1880 root = (freq_group == LP4X_DDR3600) ? 1 : 0;
1881 tx_rank_inctl = 1; tx_dly = 2;
1882 }
1883
1884 if (r2w_odt_onoff == ODT_ON) {
1885 trtw = ac_t.trtw_odt_on;
1886 trtw_05t = ac_t.trtw_odt_on_05T;
1887 tmrr2w = ac_t.tmrr2w_odt_on;
1888 }
1889
1890 for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
1891 clrsetbits32(&ch[chn].ao.shu[0].actim[0],
1892 (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0),
1893 (ac_t.trcd << 24) | (ac_t.trrd << 16) |
1894 (ac_t.twr << 8) | (ac_t.twtr << 0));
1895 clrsetbits32(&ch[chn].ao.shu[0].actim[1],
1896 (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0),
1897 (ac_t.trc << 24) | (ac_t.tras << 16) |
1898 (ac_t.trp << 8) | (ac_t.trpab << 0));
1899 clrsetbits32(&ch[chn].ao.shu[0].actim[2],
1900 (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0),
1901 (ac_t.tfaw << 24) | (trtw << 16) |
1902 (ac_t.trtp << 8) | (ac_t.txp << 0));
1903 clrsetbits32(&ch[chn].ao.shu[0].actim[3],
1904 (0xff << 16) | (0xff << 24) | (0xff << 0),
1905 (ac_t.trfc << 16) | (ac_t.refcnt << 24) | (ac_t.trfcpb << 0));
1906 clrsetbits32(&ch[chn].ao.shu[0].actim[4],
1907 (0xff << 24) | (0xff << 16) | (0x3ff << 0),
1908 (ac_t.tzqcs << 24) | (ac_t.refcnt_fr_clk << 16) |
1909 (ac_t.txrefcnt << 0));
1910 clrsetbits32(&ch[chn].ao.shu[0].actim[5],
1911 (0xf << 24) | (0x1f << 8) | (0x1f << 0),
1912 (tmrr2w << 24) | (ac_t.twtpd << 8) | (ac_t.trtpd << 0));
1913 clrsetbits32(&ch[chn].ao.shu[0].actim_xrt,
1914 (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0),
1915 (ac_t.xrtw2w << 24) | (ac_t.xrtw2r << 16) |
1916 (ac_t.xrtr2w << 8) | (ac_t.xrtr2r << 0));
1917 clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t,
1918 (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) |
1919 (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) |
1920 (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
1921 (0x1 << 4) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0),
1922 (ac_t.twtr_05T << 25) | (trtw_05t << 24) |
1923 (ac_t.twtpd_05T << 16) | (ac_t.trtpd_05T << 15) |
1924 (ac_t.tfaw_05T << 13) | (ac_t.trrd_05T << 12) |
1925 (ac_t.twr_05T << 10) | (ac_t.tras_05T << 9) |
1926 (ac_t.trpab_05T << 8) | (ac_t.trp_05T << 7) |
1927 (ac_t.trcd_05T << 6) | (ac_t.trtp_05T << 5) |
1928 (ac_t.txp_05T << 4) | (ac_t.trfc_05T << 2) |
1929 (ac_t.trfcpb_05T << 1) | (ac_t.trc_05T << 0));
1930 clrsetbits32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20),
1931 (ac_t.r_dmcatrain_intv << 24) | (0x0 << 20));
1932
1933 /* DQSINCTL related */
1934 clrsetbits32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0,
1935 ac_t.dqsinctl << 0);
1936 clrsetbits32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0,
1937 ac_t.dqsinctl << 0);
1938 clrsetbits32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4,
1939 ac_t.dqsinctl << 4);
1940
1941 /* DATLAT related, tREFBW */
1942 clrsetbits32(&ch[chn].ao.shu[0].conf[1],
1943 (0x1f << 0) | (0x1f << 8) | (0x1f << 26) | (0x3ff << 16),
1944 (ac_t.datlat << 0) | (new_datlat << 8) |
1945 (new_datlat << 26) | (0x0 << 16));
1946 clrsetbits32(&ch[chn].ao.shu[0].conf[2],
1947 (0xff << 8), ac_t.r_dmfspchg_prdcnt << 8);
1948 clrsetbits32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6),
1949 (ac_t.r_dmmrw_intv << 13) | (ac_t.zqlat2 << 6));
1950
1951 /* CKEPRD - CKE pulse width */
1952 clrsetbits32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20);
1953
1954 /* CKELCKCNT: Valid clock requirement after CKE input low */
1955 clrsetbits32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24);
1956
1957 temp = ((read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20) & 0xf;
1958 clrsetbits32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0);
1959
1960 clrsetbits32(&ch[chn].ao.shu[0].rankctl,
1961 (0xf << 16) | (0xf << 12) | (0xf << 8),
1962 (root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8));
1963 }
1964
1965 clrsetbits32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10);
1966 clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, cbt_mode << 13);
1967
1968 if (cbt_mode == 0)
1969 clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, 0 << 13);
1970 else
1971 clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, 1 << 13);
1972 }
1973
dramc_init(const struct sdram_params * params,u8 freq_group,struct dram_shared_data * shared)1974 void dramc_init(const struct sdram_params *params, u8 freq_group,
1975 struct dram_shared_data *shared)
1976 {
1977 dramc_setting(params, freq_group, &shared->impedance);
1978
1979 dramc_duty_calibration(params, freq_group);
1980 dvfs_settings(freq_group);
1981
1982 dramc_mode_reg_init(freq_group, &shared->mr, params);
1983 ddr_update_ac_timing(freq_group, params->cbt_mode_extern);
1984 }
1985