1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /* Samsung DP (Display port) register interface driver. */
4
5 #include <device/mmio.h>
6 #include <console/console.h>
7 #include <delay.h>
8 #include <soc/clk.h>
9 #include <soc/cpu.h>
10 #include <soc/dp.h>
11 #include <soc/dp-core.h>
12 #include <soc/fimd.h>
13 #include <soc/periph.h>
14 #include <timer.h>
15
s5p_dp_reset(struct s5p_dp_device * dp)16 void s5p_dp_reset(struct s5p_dp_device *dp)
17 {
18 u32 reg;
19 struct exynos5_dp *base = dp->base;
20
21 write32(&base->dp_tx_sw_reset, RESET_DP_TX);
22
23 /* Stop Video */
24 clrbits32(&base->video_ctl_1, VIDEO_EN);
25 clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE);
26
27 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
28 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
29 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
30 write32(&base->func_en_1, reg);
31
32 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
33 SERDES_FIFO_FUNC_EN_N |
34 LS_CLK_DOMAIN_FUNC_EN_N;
35 write32(&base->func_en_2, reg);
36
37 udelay(20);
38
39 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
40 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
41
42 write32(&base->lane_map, reg);
43
44 write32(&base->sys_ctl_1, 0x0);
45 write32(&base->sys_ctl_2, 0x40);
46 write32(&base->sys_ctl_3, 0x0);
47 write32(&base->sys_ctl_4, 0x0);
48
49 write32(&base->pkt_send_ctl, 0x0);
50 write32(&base->dp_hdcp_ctl, 0x0);
51
52 write32(&base->dp_hpd_deglitch_l, 0x5e);
53 write32(&base->dp_hpd_deglitch_h, 0x1a);
54
55 write32(&base->dp_debug_ctl, 0x10);
56
57 write32(&base->dp_phy_test, 0x0);
58
59 write32(&base->dp_video_fifo_thrd, 0x0);
60 write32(&base->dp_audio_margin, 0x20);
61
62 write32(&base->m_vid_gen_filter_th, 0x4);
63 write32(&base->m_aud_gen_filter_th, 0x2);
64
65 write32(&base->soc_general_ctl, 0x00000101);
66
67 /* Set Analog Parameters */
68 write32(&base->analog_ctl_1, 0x10);
69 write32(&base->analog_ctl_2, 0x0C);
70 write32(&base->analog_ctl_3, 0x85);
71 write32(&base->pll_filter_ctl_1, 0x66);
72 write32(&base->tx_amp_tuning_ctl, 0x0);
73
74 /* Set interrupt pin assertion polarity as high */
75 write32(&base->int_ctl, INT_POL0 | INT_POL1);
76
77 /* Clear pending registers */
78 write32(&base->common_int_sta_1, 0xff);
79 write32(&base->common_int_sta_2, 0x4f);
80 write32(&base->common_int_sta_3, 0xe0);
81 write32(&base->common_int_sta_4, 0xe7);
82 write32(&base->dp_int_sta, 0x63);
83
84 /* 0:mask,1: unmask */
85 write32(&base->common_int_mask_1, 0x00);
86 write32(&base->common_int_mask_2, 0x00);
87 write32(&base->common_int_mask_3, 0x00);
88 write32(&base->common_int_mask_4, 0x00);
89 write32(&base->int_sta_mask, 0x00);
90 }
91
s5p_dp_get_pll_lock_status(struct s5p_dp_device * dp)92 unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp)
93 {
94 u32 reg;
95
96 reg = read32(&dp->base->dp_debug_ctl);
97 if (reg & PLL_LOCK)
98 return PLL_LOCKED;
99 else
100 return PLL_UNLOCKED;
101 }
102
s5p_dp_init_analog_func(struct s5p_dp_device * dp)103 int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
104 {
105 u32 reg;
106 struct stopwatch sw;
107 struct exynos5_dp *base = dp->base;
108
109 write32(&base->dp_phy_pd, 0x00);
110
111 reg = PLL_LOCK_CHG;
112 write32(&base->common_int_sta_1, reg);
113
114 clrbits32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL));
115
116 /* Power up PLL */
117 if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
118 clrbits32(&base->dp_pll_ctl, DP_PLL_PD);
119
120 stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);
121
122 while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
123 if (stopwatch_expired(&sw)) {
124 printk(BIOS_ERR, "%s: PLL is not locked\n",
125 __func__);
126 return -1;
127 }
128 }
129 }
130
131 /* Enable Serdes FIFO function and Link symbol clock domain module */
132 clrbits32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N |
133 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N));
134 return 0;
135 }
136
s5p_dp_init_aux(struct s5p_dp_device * dp)137 void s5p_dp_init_aux(struct s5p_dp_device *dp)
138 {
139 u32 reg;
140 struct exynos5_dp *base = dp->base;
141
142 /* Clear interrupts related to AUX channel */
143 reg = RPLY_RECEIV | AUX_ERR;
144 write32(&base->dp_int_sta, reg);
145
146 /* Disable AUX channel module */
147 setbits32(&base->func_en_2, AUX_FUNC_EN_N);
148
149 /* Disable AUX transaction H/W retry */
150 reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT;
151 reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT;
152 reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT);
153 write32(&base->aux_hw_retry_ctl, reg);
154
155 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
156 reg = DEFER_CTRL_EN;
157 reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT;
158 write32(&base->aux_ch_defer_dtl, reg);
159
160 /* Enable AUX channel module */
161 clrbits32(&base->func_en_2, AUX_FUNC_EN_N);
162 }
163
s5p_dp_start_aux_transaction(struct s5p_dp_device * dp)164 int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
165 {
166 int reg;
167 struct exynos5_dp *base = dp->base;
168
169 /* Enable AUX CH operation */
170 setbits32(&base->aux_ch_ctl_2, AUX_EN);
171
172 /* Is AUX CH command reply received? */
173 reg = read32(&base->dp_int_sta);
174 while (!(reg & RPLY_RECEIV))
175 reg = read32(&base->dp_int_sta);
176
177 /* Clear interrupt source for AUX CH command reply */
178 write32(&base->dp_int_sta, RPLY_RECEIV);
179
180 /* Clear interrupt source for AUX CH access error */
181 reg = read32(&base->dp_int_sta);
182 if (reg & AUX_ERR) {
183 printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: "
184 "0x%02x\n", __func__, reg);
185 write32(&base->dp_int_sta, AUX_ERR);
186 return -1;
187 }
188
189 /* Check AUX CH error access status */
190 reg = read32(&base->dp_int_sta);
191 if ((reg & AUX_STATUS_MASK) != 0) {
192 printk(BIOS_ERR, "AUX CH error happens: %d\n\n",
193 reg & AUX_STATUS_MASK);
194 return -1;
195 }
196
197 return 0;
198 }
199
s5p_dp_write_byte_to_dpcd(struct s5p_dp_device * dp,unsigned int reg_addr,unsigned char data)200 int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
201 unsigned int reg_addr,
202 unsigned char data)
203 {
204 u32 reg;
205 int i;
206 int retval;
207 struct exynos5_dp *base = dp->base;
208
209 for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
210 /* Clear AUX CH data buffer */
211 write32(&base->buf_data_ctl, BUF_CLR);
212
213 /* Select DPCD device address */
214 reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
215 reg &= AUX_ADDR_7_0_MASK;
216 write32(&base->aux_addr_7_0, reg);
217 reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
218 reg &= AUX_ADDR_15_8_MASK;
219 write32(&base->aux_addr_15_8, reg);
220 reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
221 reg &= AUX_ADDR_19_16_MASK;
222 write32(&base->aux_addr_19_16, reg);
223
224 /* Write data buffer */
225 reg = (unsigned int)data;
226 write32(&base->buf_data_0, reg);
227
228 /*
229 * Set DisplayPort transaction and write 1 byte
230 * If bit 3 is 1, DisplayPort transaction.
231 * If Bit 3 is 0, I2C transaction.
232 */
233 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
234 write32(&base->aux_ch_ctl_1, reg);
235
236 /* Start AUX transaction */
237 retval = s5p_dp_start_aux_transaction(dp);
238 if (retval == 0)
239 break;
240 else
241 printk(BIOS_DEBUG, "Aux Transaction fail!\n");
242 }
243
244 return retval;
245 }
246
s5p_dp_read_byte_from_dpcd(struct s5p_dp_device * dp,unsigned int reg_addr,unsigned char * data)247 int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
248 unsigned int reg_addr,
249 unsigned char *data)
250 {
251 u32 reg;
252 int i;
253 int retval;
254 struct exynos5_dp *base = dp->base;
255
256 for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
257 /* Clear AUX CH data buffer */
258 write32(&base->buf_data_ctl, BUF_CLR);
259
260 /* Select DPCD device address */
261 reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
262 reg &= AUX_ADDR_7_0_MASK;
263 write32(&base->aux_addr_7_0, reg);
264 reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
265 reg &= AUX_ADDR_15_8_MASK;
266 write32(&base->aux_addr_15_8, reg);
267 reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
268 reg &= AUX_ADDR_19_16_MASK;
269 write32(&base->aux_addr_19_16, reg);
270
271 /*
272 * Set DisplayPort transaction and read 1 byte
273 * If bit 3 is 1, DisplayPort transaction.
274 * If Bit 3 is 0, I2C transaction.
275 */
276 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
277 write32(&base->aux_ch_ctl_1, reg);
278
279 /* Start AUX transaction */
280 retval = s5p_dp_start_aux_transaction(dp);
281 if (retval == 0)
282 break;
283 else
284 printk(BIOS_DEBUG, "Aux Transaction fail!\n");
285 }
286
287 /* Read data buffer */
288 if (!retval) {
289 reg = read32(&base->buf_data_0);
290 *data = (unsigned char)(reg & 0xff);
291 }
292
293 return retval;
294 }
295
s5p_dp_init_video(struct s5p_dp_device * dp)296 void s5p_dp_init_video(struct s5p_dp_device *dp)
297 {
298 u32 reg;
299 struct exynos5_dp *base = dp->base;
300
301 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
302 write32(&base->common_int_sta_1, reg);
303
304 reg = 0x0;
305 write32(&base->sys_ctl_1, reg);
306
307 reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT;
308 reg |= CHA_CTRL;
309 write32(&base->sys_ctl_2, reg);
310
311 reg = 0x0;
312 write32(&base->sys_ctl_3, reg);
313 }
314
s5p_dp_set_video_color_format(struct s5p_dp_device * dp,unsigned int color_depth,unsigned int color_space,unsigned int dynamic_range,unsigned int coeff)315 void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
316 unsigned int color_depth,
317 unsigned int color_space,
318 unsigned int dynamic_range,
319 unsigned int coeff)
320 {
321 u32 reg;
322 struct exynos5_dp *base = dp->base;
323
324 /* Configure the input color depth, color space, dynamic range */
325 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
326 (color_depth << IN_BPC_SHIFT) |
327 (color_space << IN_COLOR_F_SHIFT);
328 write32(&base->video_ctl_2, reg);
329
330 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
331 reg = read32(&base->video_ctl_3);
332 reg &= ~IN_YC_COEFFI_MASK;
333 if (coeff)
334 reg |= IN_YC_COEFFI_ITU709;
335 else
336 reg |= IN_YC_COEFFI_ITU601;
337 write32(&base->video_ctl_3, reg);
338 }
339
s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device * dp)340 int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
341 {
342 u32 reg;
343 struct exynos5_dp *base = dp->base;
344
345 reg = read32(&base->sys_ctl_1);
346 write32(&base->sys_ctl_1, reg);
347
348 reg = read32(&base->sys_ctl_1);
349
350 if (!(reg & DET_STA))
351 return -1;
352
353 reg = read32(&base->sys_ctl_2);
354 write32(&base->sys_ctl_2, reg);
355
356 reg = read32(&base->sys_ctl_2);
357
358 if (reg & CHA_STA) {
359 printk(BIOS_DEBUG, "Input stream clk is changing\n");
360 return -1;
361 }
362
363 return 0;
364 }
365
s5p_dp_set_video_cr_mn(struct s5p_dp_device * dp,enum clock_recovery_m_value_type type,unsigned int m_value,unsigned int n_value)366 void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
367 enum clock_recovery_m_value_type type,
368 unsigned int m_value,
369 unsigned int n_value)
370 {
371 u32 reg;
372 struct exynos5_dp *base = dp->base;
373
374 if (type == REGISTER_M) {
375 setbits32(&base->sys_ctl_4, FIX_M_VID);
376
377 reg = m_value >> M_VID_0_VALUE_SHIFT;
378 write32(&base->m_vid_0, reg);
379
380 reg = (m_value >> M_VID_1_VALUE_SHIFT);
381 write32(&base->m_vid_1, reg);
382
383 reg = (m_value >> M_VID_2_VALUE_SHIFT);
384 write32(&base->m_vid_2, reg);
385
386 reg = n_value >> N_VID_0_VALUE_SHIFT;
387 write32(&base->n_vid_0, reg);
388
389 reg = (n_value >> N_VID_1_VALUE_SHIFT);
390 write32(&base->n_vid_1, reg);
391
392 reg = (n_value >> N_VID_2_VALUE_SHIFT);
393 write32(&base->n_vid_2, reg);
394 } else {
395 clrbits32(&base->sys_ctl_4, FIX_M_VID);
396
397 write32(&base->n_vid_0, 0x00);
398 write32(&base->n_vid_1, 0x80);
399 write32(&base->n_vid_2, 0x00);
400 }
401 }
402
s5p_dp_enable_video_master(struct s5p_dp_device * dp)403 void s5p_dp_enable_video_master(struct s5p_dp_device *dp)
404 {
405 u32 reg;
406 struct exynos5_dp *base = dp->base;
407
408 reg = read32(&base->soc_general_ctl);
409 reg &= ~VIDEO_MODE_MASK;
410 reg |= VIDEO_MODE_SLAVE_MODE;
411 write32(&base->soc_general_ctl, reg);
412 }
413
s5p_dp_is_video_stream_on(struct s5p_dp_device * dp)414 int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
415 {
416 u32 reg, i = 0;
417 struct stopwatch sw;
418 struct exynos5_dp *base = dp->base;
419
420 /* Wait for 4 VSYNC_DET interrupts */
421 stopwatch_init_msecs_expire(&sw, STREAM_ON_TIMEOUT);
422
423 do {
424 reg = read32(&base->common_int_sta_1);
425 if (reg & VSYNC_DET) {
426 i++;
427 write32(&base->common_int_sta_1, reg | VSYNC_DET);
428 }
429 if (i == 4)
430 break;
431 } while (!stopwatch_expired(&sw));
432
433 if (i != 4) {
434 printk(BIOS_DEBUG, "%s timeout\n", __func__);
435 return -1;
436 }
437
438 return 0;
439 }
440
s5p_dp_config_video_slave_mode(struct s5p_dp_device * dp,struct video_info * video_info)441 void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
442 struct video_info *video_info)
443 {
444 u32 reg;
445 struct exynos5_dp *base = dp->base;
446
447 reg = read32(&base->func_en_1);
448 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
449 reg |= MASTER_VID_FUNC_EN_N;
450 write32(&base->func_en_1, reg);
451
452 reg = read32(&base->video_ctl_10);
453 reg &= ~INTERACE_SCAN_CFG;
454 reg |= (video_info->interlaced << 2);
455 write32(&base->video_ctl_10, reg);
456
457 reg = read32(&base->video_ctl_10);
458 reg &= ~VSYNC_POLARITY_CFG;
459 reg |= (video_info->v_sync_polarity << 1);
460 write32(&base->video_ctl_10, reg);
461
462 reg = read32(&base->video_ctl_10);
463 reg &= ~HSYNC_POLARITY_CFG;
464 reg |= (video_info->h_sync_polarity << 0);
465 write32(&base->video_ctl_10, reg);
466
467 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
468 write32(&base->soc_general_ctl, reg);
469 }
470
s5p_dp_wait_hw_link_training_done(struct s5p_dp_device * dp)471 void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
472 {
473 u32 reg;
474 struct exynos5_dp *base = dp->base;
475
476 reg = read32(&base->dp_hw_link_training);
477 while (reg & HW_TRAINING_EN)
478 reg = read32(&base->dp_hw_link_training);
479 }
480