1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _css_receiver_2400_defs_h_ 8 #define _css_receiver_2400_defs_h_ 9 10 #include "css_receiver_2400_common_defs.h" 11 12 #define CSS_RECEIVER_DATA_WIDTH 8 13 #define CSS_RECEIVER_RX_TRIG 4 14 #define CSS_RECEIVER_RF_WORD 32 15 #define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 16 #define CSS_RECEIVER_CSI_RF_ADDR 4 17 #define CSS_RECEIVER_DATA_OUT 12 18 #define CSS_RECEIVER_CHN_NO 2 19 #define CSS_RECEIVER_DWORD_CNT 11 20 #define CSS_RECEIVER_FORMAT_TYP 5 21 #define CSS_RECEIVER_HRESPONSE 2 22 #define CSS_RECEIVER_STATE_WIDTH 3 23 #define CSS_RECEIVER_FIFO_DAT 32 24 #define CSS_RECEIVER_CNT_VAL 2 25 #define CSS_RECEIVER_PRED10_VAL 10 26 #define CSS_RECEIVER_PRED12_VAL 12 27 #define CSS_RECEIVER_CNT_WIDTH 8 28 #define CSS_RECEIVER_WORD_CNT 16 29 #define CSS_RECEIVER_PIXEL_LEN 6 30 #define CSS_RECEIVER_PIXEL_CNT 5 31 #define CSS_RECEIVER_COMP_8_BIT 8 32 #define CSS_RECEIVER_COMP_7_BIT 7 33 #define CSS_RECEIVER_COMP_6_BIT 6 34 35 #define CSI_CONFIG_WIDTH 4 36 37 /* division of gen_short data, ch_id and fmt_type over streaming data interface */ 38 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 39 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) 40 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) 41 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) 42 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) 43 #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) 44 45 #define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 46 #define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 47 48 #define hrt_css_receiver_2400_4_lane_port_offset 0x100 49 #define hrt_css_receiver_2400_1_lane_port_offset 0x200 50 #define hrt_css_receiver_2400_2_lane_port_offset 0x300 51 #define hrt_css_receiver_2400_backend_port_offset 0x100 52 53 #define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 54 #define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 55 #define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 56 #define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 57 #define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 58 #define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 59 #define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 60 #define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 61 #define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 62 #define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 63 #define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 64 #define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 65 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 66 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 67 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 68 #define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 69 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 70 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 71 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 72 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 73 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 74 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 75 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 76 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 77 #define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 78 #define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 79 #define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 80 81 /* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ 82 #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 83 #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 84 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 85 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 86 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 87 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 88 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 89 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 90 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 91 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 92 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 93 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 94 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 95 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 96 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 97 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 98 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 99 100 #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" 101 #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" 102 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" 103 #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" 104 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" 105 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" 106 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" 107 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" 108 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" 109 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" 110 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" 111 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" 112 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" 113 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" 114 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" 115 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" 116 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" 117 118 /* Bits for CSI2_DEVICE_READY register */ 119 #define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 120 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 121 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 122 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 123 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 124 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 125 #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 126 127 /* Bits for CSI2_FUNC_PROG register */ 128 #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 129 #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 130 131 /* Bits for INIT_COUNT register */ 132 #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 133 #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 134 135 /* Bits for COUNT registers */ 136 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 137 #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 138 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 139 #define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 140 141 /* Bits for RAW116_18_DATAID register */ 142 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 143 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 144 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 145 #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 146 147 /* Bits for COMP_FORMAT register, this selects the compression data format */ 148 #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 149 #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 150 #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) 151 #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 152 153 /* Bits for COMP_PREDICT register, this selects the predictor algorithm */ 154 #define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 155 #define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 156 #define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 157 158 /* Number of bits used for the delay registers */ 159 #define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 160 161 /* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ 162 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 163 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 164 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 165 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 166 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 167 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 168 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 169 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 170 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 171 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 172 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 173 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 174 #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 175 176 /* BITS for backend RAW16 and RAW 18 registers */ 177 178 #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 179 #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 180 #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 181 #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 182 #define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 183 #define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 184 185 #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 186 #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 187 #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 188 #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 189 #define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 190 #define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 191 192 /* These hsync and vsync values are for HSS simulation only */ 193 #define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16) 194 #define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17) 195 196 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 197 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 198 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) 199 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) 200 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) 201 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) 202 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) 203 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) 204 #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) 205 206 // SH Backend Register IDs 207 #define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 208 #define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 209 #define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 210 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 211 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 212 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 213 #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 214 #define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 215 #define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 216 #define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 217 #define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 218 #define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 219 #define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 220 #define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 221 #define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ 222 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ 223 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ 224 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ 225 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ 226 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ 227 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ 228 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ 229 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ 230 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ 231 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ 232 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ 233 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ 234 #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ 235 236 #define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 237 238 #define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 239 #define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 240 #define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 241 #define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 242 #define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 243 #define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 244 #define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 245 #define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 246 #define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 247 248 #endif /* _css_receiver_2400_defs_h_ */ 249