1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_INTEL_SPEEDSTEP_H 4 #define CPU_INTEL_SPEEDSTEP_H 5 6 #include <stdbool.h> 7 #include <stdint.h> 8 9 /* MWAIT coordination I/O base address. This must match 10 * the \_PR_.CP00 PM base address. 11 */ 12 #define PMB0_BASE 0x510 13 14 /* PMB1: I/O port that triggers SMI once cores are in the same state. 15 * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] 16 */ 17 #define PMB1_BASE 0x800 18 19 /* Speedstep related MSRs */ 20 #define MSR_THERM2_CTL 0x19D 21 #define MSR_EBC_FREQUENCY_ID 0x2c 22 #define MSR_FSB_FREQ 0xcd 23 #define MSR_FSB_CLOCK_VCC 0xce 24 #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 25 #define MSR_PMG_IO_BASE_ADDR 0xe3 26 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4 27 #define MSR_EXTENDED_CONFIG 0xee 28 #define FREQ_LIMIT_RATIO 0x1AD 29 30 typedef struct { 31 uint8_t dynfsb : 1; /* whether this is SLFM */ 32 uint8_t nonint : 1; /* add .5 to ratio */ 33 uint8_t ratio : 6; 34 uint8_t vid; 35 uint8_t is_turbo; 36 uint8_t is_slfm; 37 uint32_t power; 38 } sst_state_t; 39 #define SPEEDSTEP_RATIO_SHIFT 8 40 #define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) 41 #define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) 42 #define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) 43 #define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) 44 #define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) 45 #define SPEEDSTEP_VID_MASK 0x3f 46 #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){ \ 47 0, /* dynfsb won't be read. */ \ 48 ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ 49 (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ 50 >> SPEEDSTEP_RATIO_SHIFT), \ 51 (val & mask) & SPEEDSTEP_VID_MASK, \ 52 0, /* not turbo by default */ \ 53 0, /* not slfm by default */ \ 54 0 /* power is hardcoded in software. */ \ 55 }) 56 #define SPEEDSTEP_ENCODE_STATE(state) ( \ 57 ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ 58 ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ 59 ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ 60 ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) 61 #define SPEEDSTEP_DOUBLE_RATIO(state) ( \ 62 ((uint8_t)(state).ratio * 2) + (state).nonint) 63 64 typedef struct { 65 sst_state_t slfm; 66 sst_state_t min; 67 sst_state_t max; 68 sst_state_t turbo; 69 } sst_params_t; 70 71 /* Looking at core2's spec, the highest normal bus ratio for an eist enabled 72 processor is 14, the lowest is always 6. This makes 5 states with the 73 minimal step width of 2. With turbo mode and super LFM we have at most 7. */ 74 #define SPEEDSTEP_MAX_NORMAL_STATES 5 75 #define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) 76 typedef struct { 77 /* Table of p-states for EMTTM and ACPI by decreasing performance. */ 78 sst_state_t states[SPEEDSTEP_MAX_STATES]; 79 int num_states; 80 } sst_table_t; 81 82 void speedstep_gen_pstates(sst_table_t *); 83 84 #define SPEEDSTEP_MAX_POWER_YONAH 31000 85 #define SPEEDSTEP_MIN_POWER_YONAH 13100 86 #define SPEEDSTEP_MAX_POWER_MEROM 35000 87 #define SPEEDSTEP_MIN_POWER_MEROM 25000 88 #define SPEEDSTEP_SLFM_POWER_MEROM 12000 89 #define SPEEDSTEP_MAX_POWER_PENRYN 35000 90 #define SPEEDSTEP_MIN_POWER_PENRYN 15000 91 #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 92 93 bool southbridge_support_c5(void); 94 bool southbridge_support_c6(void); 95 bool northbridge_support_slfm(void); 96 97 #endif /* CPU_INTEL_SPEEDSTEP_H */ 98