1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_INTEL_MSR_H 4 #define CPU_INTEL_MSR_H 5 6 /* 7 * Common MSRs for Intel CPUs 8 */ 9 10 #define MSR_PIC_MSG_CONTROL 0x2e 11 #define TPR_UPDATES_DISABLE (1 << 10) 12 13 #define MSR_PLATFORM_INFO 0xce 14 15 #define MSR_BC_PBEC 0x139 16 #define B_STOP_PBET (1 << 0) 17 18 #define MSR_BOOT_GUARD_SACM_INFO 0x13a 19 #define V_TPM_PRESENT_MASK 0x06 20 #define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED (1 << 0) 21 #define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS (1 << 3) 22 #define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT (1 << 5) 23 #define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT (1 << 6) 24 #define B_BOOT_GUARD_SACM_INFO_REVOKED (1 << 7) 25 #define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32) 26 #define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34) 27 28 #define MSR_FEATURE_CONFIG 0x13c 29 #define AESNI_DISABLE (1 << 1) 30 #define AESNI_LOCK (1 << 0) 31 32 #define MSR_SPCL_CHIPSET_USAGE 0x1fe 33 34 #define MSR_PKG_C10_RESIDENCY 0x632 35 36 #define MSR_TME_ACTIVATE 0x982 37 #define TME_ACTIVATE_HI_KEYID_BITS_MASK 0xf 38 39 #endif /* CPU_INTEL_MSR_H */ 40