1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_AMD_MTRR_H 4 #define CPU_AMD_MTRR_H 5 6 #define MTRR_IORR0_BASE 0xC0010016 7 #define MTRR_IORR0_MASK 0xC0010017 8 #define MTRR_IORR1_BASE 0xC0010018 9 #define MTRR_IORR1_MASK 0xC0010019 10 11 #define MTRR_READ_MEM (1 << 4) 12 #define MTRR_WRITE_MEM (1 << 3) 13 14 #define SYSCFG_MSR 0xC0010010 15 #define SYSCFG_MSR_SMEE (1 << 23) 16 #define SYSCFG_MSR_TOM2WB (1 << 22) 17 #define SYSCFG_MSR_TOM2En (1 << 21) 18 #define SYSCFG_MSR_MtrrVarDramEn (1 << 20) 19 #define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) 20 #define SYSCFG_MSR_MtrrFixDramEn (1 << 18) 21 #define SYSCFG_MSR_UcLockEn (1 << 17) 22 #define SYSCFG_MSR_ChxToDirtyDis (1 << 16) 23 #define SYSCFG_MSR_ClVicBlkEn (1 << 11) 24 #define SYSCFG_MSR_SetDirtyEnO (1 << 10) 25 #define SYSCFG_MSR_SetDirtyEnS (1 << 9) 26 #define SYSCFG_MSR_SetDirtyEnE (1 << 8) 27 #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) 28 #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) 29 30 #define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) 31 #define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) 32 33 #if defined(__ASSEMBLER__) 34 #define TOP_MEM 0xC001001A 35 #define TOP_MEM2 0xC001001D 36 #else 37 #define TOP_MEM 0xC001001Aul 38 #define TOP_MEM2 0xC001001Dul 39 #endif 40 41 #if !defined(__ASSEMBLER__) 42 43 #include <cpu/x86/msr.h> 44 #include <stdint.h> 45 46 struct device; 47 void add_uma_resource_below_tolm(struct device *nb, int idx); 48 rdmsr_amd(unsigned int index)49static __always_inline msr_t rdmsr_amd(unsigned int index) 50 { 51 msr_t result; 52 __asm__ __volatile__ ( 53 "rdmsr" 54 : "=a" (result.lo), "=d" (result.hi) 55 : "c"(index), "D"(0x9c5a203a) 56 ); 57 return result; 58 } 59 wrmsr_amd(unsigned int index,msr_t msr)60static __always_inline void wrmsr_amd(unsigned int index, msr_t msr) 61 { 62 __asm__ __volatile__ ( 63 "wrmsr" 64 : /* No outputs */ 65 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a) 66 ); 67 } 68 get_top_of_mem_below_4gb(void)69static inline uint32_t get_top_of_mem_below_4gb(void) 70 { 71 return rdmsr(TOP_MEM).lo; 72 } 73 get_top_of_mem_above_4gb(void)74static inline uint64_t get_top_of_mem_above_4gb(void) 75 { 76 msr_t msr = rdmsr(TOP_MEM2); 77 return (uint64_t)msr.hi << 32 | msr.lo; 78 } 79 #endif 80 81 #endif /* CPU_AMD_MTRR_H */ 82