1 /*
2  * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A720_H
8 #define CORTEX_A720_H
9 
10 #define CORTEX_A720_MIDR					U(0x410FD810)
11 
12 /* Cortex A720 loop count for CVE-2022-23960 mitigation */
13 #define CORTEX_A720_BHB_LOOP_COUNT				U(132)
14 
15 /*******************************************************************************
16  * CPU Auxiliary Control register 1 specific definitions.
17  ******************************************************************************/
18 #define CORTEX_A720_CPUACTLR_EL1				S3_0_C15_C1_0
19 
20 /*******************************************************************************
21  * CPU Auxiliary Control register 2 specific definitions.
22  ******************************************************************************/
23 #define CORTEX_A720_CPUACTLR2_EL1				S3_0_C15_C1_1
24 
25 /*******************************************************************************
26  * CPU Extended Control register specific definitions
27  ******************************************************************************/
28 #define CORTEX_A720_CPUECTLR_EL1				S3_0_C15_C1_4
29 
30 /*******************************************************************************
31  * CPU Power Control register specific definitions
32  ******************************************************************************/
33 #define CORTEX_A720_CPUPWRCTLR_EL1				S3_0_C15_C2_7
34 #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
35 
36 #endif /* CORTEX_A720_H */
37