1 /** 2 * \file 3 * 4 * \brief SAMV71 clock configuration. 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef CONF_CLOCK_H_INCLUDED 48 #define CONF_CLOCK_H_INCLUDED 49 50 // ===== System Clock (MCK) Source Options 51 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC 52 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL 53 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS 54 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC 55 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC 56 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC 57 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL 58 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS 59 #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK 60 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK 61 62 // ===== Processor Clock (HCLK) Prescaler Options (Fhclk = Fsys / (SYSCLK_PRES)) 63 #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 64 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 65 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 66 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 67 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 68 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 69 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 70 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 71 72 // ===== System Clock (MCK) Division Options (Fmck = Fhclk / (SYSCLK_DIV)) 73 #define CONFIG_SYSCLK_DIV 2 74 75 // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) 76 // Use mul and div effective values here. 77 #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL 78 #define CONFIG_PLL0_MUL 25 79 #define CONFIG_PLL0_DIV 1 80 81 // ===== UPLL (UTMI) Hardware fixed at 480 MHz. 82 83 // ===== USB Clock Source Options (Fusb = FpllX / USB_div) 84 // Use div effective value here. 85 //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 86 #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL 87 #define CONFIG_USBCLK_DIV 1 88 89 // ===== Target frequency (Processor clock) 90 // - XTAL frequency: 12MHz 91 // - System clock source: PLLA 92 // - System clock prescaler: 1 (divided by 1) 93 // - System clock divider: 2 (divided by 2) 94 // - PLLA source: XTAL 95 // - PLLA output: XTAL * 25 / 1 96 // - Processor clock: 12 * 25 / 1 / 1 = 300MHz 97 // - System clock: 300 / 2 = 150MHz 98 // ===== Target frequency (USB Clock) 99 // - USB clock source: UPLL 100 // - USB clock divider: 1 (not divided) 101 // - UPLL frequency: 480MHz 102 // - USB clock: 480 / 1 = 480MHz 103 104 #endif /* CONF_CLOCK_H_INCLUDED */ 105