xref: /aosp_15_r20/external/coreboot/src/commonlib/bsd/include/commonlib/bsd/elog.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 
3 #ifndef _COMMONLIB_BSD_ELOG_H_
4 #define _COMMONLIB_BSD_ELOG_H_
5 
6 #include <stdint.h>
7 
8 #include <commonlib/bsd/cb_err.h>
9 
10 /* ELOG header */
11 struct elog_header {
12 	uint32_t magic;
13 	uint8_t version;
14 	uint8_t header_size;
15 	uint8_t reserved[2];
16 } __packed;
17 
18 /* ELOG related constants */
19 #define ELOG_SIGNATURE			0x474f4c45  /* 'ELOG' */
20 #define ELOG_VERSION			1
21 #define ELOG_RW_REGION_NAME		"RW_ELOG"
22 
23 /* SMBIOS event log header */
24 struct event_header {
25 	uint8_t type;
26 	uint8_t length;
27 	uint8_t year;
28 	uint8_t month;
29 	uint8_t day;
30 	uint8_t hour;
31 	uint8_t minute;
32 	uint8_t second;
33 } __packed;
34 
35 /* SMBIOS Type 15 related constants */
36 #define ELOG_HEADER_TYPE_OEM		0x88
37 
38 /* End of log */
39 #define ELOG_TYPE_EOL                     0xFF
40 
41 /*
42  * Standard SMBIOS event log types below 0x80
43  */
44 #define ELOG_TYPE_UNDEFINED_EVENT         0x00
45 #define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR  0x01
46 #define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR   0x02
47 #define ELOG_TYPE_MEM_PARITY_ERR          0x03
48 #define ELOG_TYPE_BUS_TIMEOUT             0x04
49 #define ELOG_TYPE_IO_CHECK                0x05
50 #define ELOG_TYPE_SW_NMI                  0x06
51 #define ELOG_TYPE_POST_MEM_RESIZE         0x07
52 #define ELOG_TYPE_POST_ERR                0x08
53 #define ELOG_TYPE_PCI_PERR                0x09
54 #define ELOG_TYPE_PCI_SERR                0x0A
55 #define ELOG_TYPE_CPU_FAIL                0x0B
56 #define ELOG_TYPE_EISA_TIMEOUT            0x0C
57 #define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS  0x0D
58 #define ELOG_TYPE_LOG_DISABLED            0x0E
59 #define ELOG_TYPE_UNDEFINED_EVENT2        0x0F
60 #define ELOG_TYPE_SYS_LIMIT_EXCEED        0x10
61 #define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED  0x11
62 #define ELOG_TYPE_SYS_CONFIG_INFO         0x12
63 #define ELOG_TYPE_HDD_INFO                0x13
64 #define ELOG_TYPE_SYS_RECONFIG            0x14
65 #define ELOG_TYPE_CPU_ERROR               0x15
66 #define ELOG_TYPE_LOG_CLEAR               0x16
67 #define ELOG_TYPE_BOOT                    0x17
68 
69 /*
70  * Extended defined OEM event types start at 0x80
71  */
72 
73 /* OS/kernel events */
74 #define ELOG_TYPE_OS_EVENT                0x81
75 #define ELOG_OS_EVENT_CLEAN              0  /* Clean Shutdown */
76 #define ELOG_OS_EVENT_NMIWDT             1  /* NMI Watchdog */
77 #define ELOG_OS_EVENT_PANIC              2  /* Panic */
78 #define ELOG_OS_EVENT_OOPS               3  /* Oops */
79 #define ELOG_OS_EVENT_DIE                4  /* Die */
80 #define ELOG_OS_EVENT_MCE                5  /* MCE */
81 #define ELOG_OS_EVENT_SOFTWDT            6  /* Software Watchdog */
82 #define ELOG_OS_EVENT_MBE                7  /* MBE */
83 #define ELOG_OS_EVENT_TRIPLE             8  /* Triple Fault */
84 #define ELOG_OS_EVENT_THERMAL            9  /* Critical Thermal Threshold */
85 
86 /* Last event from coreboot */
87 #define ELOG_TYPE_OS_BOOT                 0x90
88 
89 /* Embedded controller event */
90 #define ELOG_TYPE_EC_EVENT                0x91
91 #define EC_EVENT_LID_CLOSED                  0x01
92 #define EC_EVENT_LID_OPEN                    0x02
93 #define EC_EVENT_POWER_BUTTON                0x03
94 #define EC_EVENT_AC_CONNECTED                0x04
95 #define EC_EVENT_AC_DISCONNECTED             0x05
96 #define EC_EVENT_BATTERY_LOW                 0x06
97 #define EC_EVENT_BATTERY_CRITICAL            0x07
98 #define EC_EVENT_BATTERY                     0x08
99 #define EC_EVENT_THERMAL_THRESHOLD           0x09
100 #define EC_EVENT_DEVICE_EVENT                0x0a
101 #define EC_EVENT_THERMAL                     0x0b
102 #define EC_EVENT_USB_CHARGER                 0x0c
103 #define EC_EVENT_KEY_PRESSED                 0x0d
104 #define EC_EVENT_INTERFACE_READY             0x0e
105 #define EC_EVENT_KEYBOARD_RECOVERY           0x0f
106 #define EC_EVENT_THERMAL_SHUTDOWN            0x10
107 #define EC_EVENT_BATTERY_SHUTDOWN            0x11
108 #define EC_EVENT_THROTTLE_START              0x12
109 #define EC_EVENT_THROTTLE_STOP               0x13
110 #define EC_EVENT_HANG_DETECT                 0x14
111 #define EC_EVENT_HANG_REBOOT                 0x15
112 #define EC_EVENT_PD_MCU                      0x16
113 #define EC_EVENT_BATTERY_STATUS              0x17
114 #define EC_EVENT_PANIC                       0x18
115 #define EC_EVENT_KEYBOARD_FASTBOOT           0x19
116 #define EC_EVENT_RTC                         0x1a
117 #define EC_EVENT_MKBP                        0x1b
118 #define EC_EVENT_USB_MUX                     0x1c
119 #define EC_EVENT_MODE_CHANGE                 0x1d
120 #define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT  0x1e
121 #define EC_EVENT_EXTENDED                    0x1f
122 struct elog_ec_event {
123 	uint8_t event;
124 	uint8_t checksum;
125 } __packed;
126 
127 /* Power */
128 #define ELOG_TYPE_POWER_FAIL              0x92
129 #define ELOG_TYPE_SUS_POWER_FAIL          0x93
130 #define ELOG_TYPE_PWROK_FAIL              0x94
131 #define ELOG_TYPE_SYS_PWROK_FAIL          0x95
132 #define ELOG_TYPE_POWER_ON                0x96
133 #define ELOG_TYPE_POWER_BUTTON            0x97
134 #define ELOG_TYPE_POWER_BUTTON_OVERRIDE   0x98
135 
136 /* Reset */
137 #define ELOG_TYPE_RESET_BUTTON            0x99
138 #define ELOG_TYPE_SYSTEM_RESET            0x9a
139 #define ELOG_TYPE_RTC_RESET               0x9b
140 #define ELOG_TYPE_TCO_RESET               0x9c
141 
142 /* Sleep/Wake */
143 #define ELOG_TYPE_ACPI_ENTER              0x9d
144 /*
145  * Deep Sx wake variant is provided below - 0xad
146  * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02
147  */
148 
149 #define ELOG_TYPE_ACPI_WAKE               0x9e
150 #define ELOG_TYPE_WAKE_SOURCE             0x9f
151 #define  ELOG_WAKE_SOURCE_PCIE             0x00
152 #define  ELOG_WAKE_SOURCE_PME              0x01
153 #define  ELOG_WAKE_SOURCE_PME_INTERNAL     0x02
154 #define  ELOG_WAKE_SOURCE_RTC              0x03
155 #define  ELOG_WAKE_SOURCE_GPE              0x04
156 #define  ELOG_WAKE_SOURCE_SMBUS            0x05
157 #define  ELOG_WAKE_SOURCE_PWRBTN           0x06
158 #define  ELOG_WAKE_SOURCE_PME_HDA          0x07
159 #define  ELOG_WAKE_SOURCE_PME_GBE          0x08
160 #define  ELOG_WAKE_SOURCE_PME_EMMC         0x09
161 #define  ELOG_WAKE_SOURCE_PME_SDCARD       0x0a
162 #define  ELOG_WAKE_SOURCE_PME_PCIE1        0x0b
163 #define  ELOG_WAKE_SOURCE_PME_PCIE2        0x0c
164 #define  ELOG_WAKE_SOURCE_PME_PCIE3        0x0d
165 #define  ELOG_WAKE_SOURCE_PME_PCIE4        0x0e
166 #define  ELOG_WAKE_SOURCE_PME_PCIE5        0x0f
167 #define  ELOG_WAKE_SOURCE_PME_PCIE6        0x10
168 #define  ELOG_WAKE_SOURCE_PME_PCIE7        0x11
169 #define  ELOG_WAKE_SOURCE_PME_PCIE8        0x12
170 #define  ELOG_WAKE_SOURCE_PME_PCIE9        0x13
171 #define  ELOG_WAKE_SOURCE_PME_PCIE10       0x14
172 #define  ELOG_WAKE_SOURCE_PME_PCIE11       0x15
173 #define  ELOG_WAKE_SOURCE_PME_PCIE12       0x16
174 #define  ELOG_WAKE_SOURCE_PME_SATA         0x17
175 #define  ELOG_WAKE_SOURCE_PME_CSE          0x18
176 #define  ELOG_WAKE_SOURCE_PME_CSE2         0x19
177 #define  ELOG_WAKE_SOURCE_PME_CSE3         0x1a
178 #define  ELOG_WAKE_SOURCE_PME_XHCI         0x1b
179 #define  ELOG_WAKE_SOURCE_PME_XDCI         0x1c
180 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_2   0x1d
181 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_3   0x1e
182 #define  ELOG_WAKE_SOURCE_PME_WIFI         0x1f
183 #define  ELOG_WAKE_SOURCE_PME_PCIE13       0x20
184 #define  ELOG_WAKE_SOURCE_PME_PCIE14       0x21
185 #define  ELOG_WAKE_SOURCE_PME_PCIE15       0x22
186 #define  ELOG_WAKE_SOURCE_PME_PCIE16       0x23
187 #define  ELOG_WAKE_SOURCE_PME_PCIE17       0x24
188 #define  ELOG_WAKE_SOURCE_PME_PCIE18       0x25
189 #define  ELOG_WAKE_SOURCE_PME_PCIE19       0x26
190 #define  ELOG_WAKE_SOURCE_PME_PCIE20       0x27
191 #define  ELOG_WAKE_SOURCE_PME_PCIE21       0x28
192 #define  ELOG_WAKE_SOURCE_PME_PCIE22       0x29
193 #define  ELOG_WAKE_SOURCE_PME_PCIE23       0x2a
194 #define  ELOG_WAKE_SOURCE_PME_PCIE24       0x2b
195 #define  ELOG_WAKE_SOURCE_GPIO             0x2c
196 #define  ELOG_WAKE_SOURCE_PME_TBT          0x2d
197 #define  ELOG_WAKE_SOURCE_PME_TCSS_XHCI    0x2e
198 #define  ELOG_WAKE_SOURCE_PME_TCSS_XDCI    0x2f
199 #define  ELOG_WAKE_SOURCE_PME_TCSS_DMA     0x30
200 
201 struct elog_event_data_wake {
202 	uint8_t source;
203 	uint32_t instance;
204 } __packed;
205 
206 /* ChromeOS related events */
207 #define ELOG_DEPRECATED_TYPE_CROS_DEVELOPER_MODE     0xa0
208 #define ELOG_DEPRECATED_TYPE_CROS_RECOVERY_MODE      0xa1
209 #define  ELOG_DEPRECATED_CROS_RECOVERY_MODE_BUTTON    0x02
210 
211 /* Management Engine Events */
212 #define ELOG_TYPE_MANAGEMENT_ENGINE      0xa2
213 #define  ELOG_ME_PATH_NORMAL              0x00
214 #define  ELOG_ME_PATH_S3WAKE              0x01
215 #define  ELOG_ME_PATH_ERROR               0x02
216 #define  ELOG_ME_PATH_RECOVERY            0x03
217 #define  ELOG_ME_PATH_DISABLED            0x04
218 #define  ELOG_ME_PATH_FW_UPDATE           0x05
219 
220 #define ELOG_TYPE_MANAGEMENT_ENGINE_EXT  0xa4
221 #define  ELOG_ME_PHASE_ROM                0
222 #define  ELOG_ME_PHASE_BRINGUP            1
223 #define  ELOG_ME_PHASE_UKERNEL            2
224 #define  ELOG_ME_PHASE_POLICY             3
225 #define  ELOG_ME_PHASE_MODULE             4
226 #define  ELOG_ME_PHASE_UNKNOWN            5
227 #define  ELOG_ME_PHASE_HOST               6
228 struct elog_event_data_me_extended {
229 	uint8_t current_working_state;
230 	uint8_t operation_state;
231 	uint8_t operation_mode;
232 	uint8_t error_code;
233 	uint8_t progress_code;
234 	uint8_t current_pmevent;
235 	uint8_t current_state;
236 } __packed;
237 
238 /* Last post code from previous boot */
239 #define ELOG_TYPE_LAST_POST_CODE          0xa3
240 #define ELOG_TYPE_POST_EXTRA              0xa6
241 #define  ELOG_TYPE_POST_EXTRA_PATH       0x01
242 #define   ELOG_DEV_PATH_TYPE_NONE          0
243 #define   ELOG_DEV_PATH_TYPE_ROOT          1
244 #define   ELOG_DEV_PATH_TYPE_PCI           2
245 #define   ELOG_DEV_PATH_TYPE_PNP           3
246 #define   ELOG_DEV_PATH_TYPE_I2C           4
247 #define   ELOG_DEV_PATH_TYPE_APIC          5
248 #define   ELOG_DEV_PATH_TYPE_DOMAIN        6
249 #define   ELOG_DEV_PATH_TYPE_CPU_CLUSTER   7
250 #define   ELOG_DEV_PATH_TYPE_CPU           8
251 #define   ELOG_DEV_PATH_TYPE_CPU_BUS       9
252 #define   ELOG_DEV_PATH_TYPE_IOAPIC        10
253 
254 /* EC Shutdown Reason */
255 #define ELOG_TYPE_EC_SHUTDOWN             0xa5
256 
257 /* ARM/generic versions of sleep/wake - These came from another firmware
258  * apparently, but not all the firmware sources were updated so that the
259  * elog namespace was coherent. */
260 #define ELOG_TYPE_SLEEP                   0xa7
261 #define ELOG_TYPE_WAKE                    0xa8
262 #define ELOG_TYPE_FW_WAKE                 0xa9
263 
264 /* Memory Cache Update */
265 #define ELOG_TYPE_MEM_CACHE_UPDATE        0xaa
266 #define  ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL    0
267 #define  ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY  1
268 #define  ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE  2
269 #define  ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
270 #define  ELOG_MEM_CACHE_UPDATE_STATUS_FAIL    1
271 struct elog_event_mem_cache_update {
272 	uint8_t slot;
273 	uint8_t status;
274 } __packed;
275 
276 /* CPU Thermal Trip */
277 #define ELOG_TYPE_THERM_TRIP              0xab
278 
279 /* Cr50 */
280 #define ELOG_TYPE_CR50_UPDATE             0xac
281 
282 /* Deep Sx wake variant */
283 #define ELOG_TYPE_ACPI_DEEP_WAKE          0xad
284 
285 /* EC Device Event */
286 #define ELOG_TYPE_EC_DEVICE_EVENT         0xae
287 #define ELOG_EC_DEVICE_EVENT_TRACKPAD       0x01
288 #define ELOG_EC_DEVICE_EVENT_DSP            0x02
289 #define ELOG_EC_DEVICE_EVENT_WIFI           0x03
290 
291 /* S0ix sleep/wake */
292 #define ELOG_TYPE_S0IX_ENTER              0xaf
293 #define ELOG_TYPE_S0IX_EXIT               0xb0
294 
295 /* Extended events */
296 #define ELOG_TYPE_EXTENDED_EVENT          0xb1
297 #define  ELOG_SLEEP_PENDING_PM1_WAKE       0x01
298 #define  ELOG_SLEEP_PENDING_GPE0_WAKE      0x02
299 
300 /* Cr50 reset to enable TPM */
301 #define ELOG_TYPE_CR50_NEED_RESET         0xb2
302 
303 /* CSME-Initiated Host Reset */
304 #define ELOG_TYPE_MI_HRPD                 0xb3
305 #define ELOG_TYPE_MI_HRPC                 0xb4
306 #define ELOG_TYPE_MI_HR                   0xb5
307 
308 /* ChromeOS diagnostics-related events */
309 #define ELOG_TYPE_CROS_DIAGNOSTICS                0xb6
310 #define  ELOG_DEPRECATED_CROS_LAUNCH_DIAGNOSTICS   0x01
311 #define  ELOG_CROS_DIAGNOSTICS_LOGS                0x02
312 /* Type codes for elog_event_cros_diag_log in ELOG_CROS_DIAGNOSTICS_LOGS */
313 #define   ELOG_CROS_DIAG_TYPE_NONE                  0x00
314 #define   ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH        0x01
315 #define   ELOG_CROS_DIAG_TYPE_STORAGE_TEST_SHORT    0x02
316 #define   ELOG_CROS_DIAG_TYPE_STORAGE_TEST_EXTENDED 0x03
317 #define   ELOG_CROS_DIAG_TYPE_MEMORY_QUICK          0x04
318 #define   ELOG_CROS_DIAG_TYPE_MEMORY_FULL           0x05
319 /*
320  * Result codes for elog_event_cros_diag_log in ELOG_CROS_DIAGNOSTICS_LOGS
321  *
322  * These values are persisted to logs. Entries should not be renumbered and
323  * numeric values should never be reused.
324  */
325 #define   ELOG_CROS_DIAG_RESULT_PASSED              0x01
326 #define   ELOG_CROS_DIAG_RESULT_ERROR               0x02
327 #define   ELOG_CROS_DIAG_RESULT_FAILED              0x03
328 #define   ELOG_CROS_DIAG_RESULT_ABORTED             0x04
329 
330 /*
331  * ChromeOS diagnostics log format:
332  * [23:19] = ELOG_CROS_DIAG_TYPE_*
333  * [18:16] = ELOG_CROS_DIAG_RESULT_*
334  * [15:0]  = Running time in seconds
335  */
336 #define ELOG_CROS_DIAG_LOG_TYPE_BITS 5
337 #define ELOG_CROS_DIAG_LOG_RESULT_BITS 3
338 union elog_event_cros_diag_log {
339 	uint8_t raw[3];
340 	struct {
341 		/* 5-bit type code, see ELOG_CROS_DIAG_TYPE_* above */
342 		uint8_t type	: ELOG_CROS_DIAG_LOG_TYPE_BITS;
343 		/* 3-bit result code, see ELOG_CROS_DIAG_RESULT_* above */
344 		uint8_t result	: ELOG_CROS_DIAG_LOG_RESULT_BITS;
345 		/*
346 		 * The running time of this diagnostics test item. If the
347 		 * running time exceeds the UINT16_MAX, it will be stored as
348 		 * UINT16_MAX instead.
349 		 */
350 		uint16_t time_s;
351 	} __packed;
352 } __packed;
353 
354 struct elog_event_extended_event {
355 	uint8_t event_type;
356 	uint32_t event_complement;
357 } __packed;
358 
359 /*
360  * Firmware boot related information retrieved from vboot and store as
361  * per `union vb2_fw_boot_info` data structure.
362  */
363 #define ELOG_TYPE_FW_VBOOT_INFO           0xb7
364 
365 /*
366  * Events related to early Sign Of Life
367  */
368 #define ELOG_TYPE_FW_EARLY_SOL            0xb8
369 #define  ELOG_FW_EARLY_SOL_CSE_SYNC        0x0
370 #define  ELOG_FW_EARLY_SOL_MRC             0x1
371 
372 /* Platform Service Record(PSR) Events */
373 #define ELOG_TYPE_PSR_DATA_BACKUP         0xb9
374 #define  ELOG_PSR_DATA_BACKUP_SUCCESS      0x0
375 #define  ELOG_PSR_DATA_BACKUP_FAILED       0x1
376 
377 #define ELOG_TYPE_PSR_DATA_LOST           0xba
378 
379 /*
380  * Events related to Firmware Splash Screen
381  */
382 #define ELOG_TYPE_FW_SPLASH_SCREEN        0xbb
383 
384 /*
385  * Events related to CSE sync from payload
386  */
387 #define ELOG_TYPE_FW_LATE_SOL             0xbc
388 #define  ELOG_FW_LATE_SOL_CSE_SYNC         0x0
389 
390 /* Only the 7-LSB are used for size */
391 #define ELOG_MAX_EVENT_SIZE                    0x7F
392 
393 enum cb_err elog_verify_header(const struct elog_header *header);
394 const struct event_header *elog_get_next_event(const struct event_header *event);
395 const void *event_get_data(const struct event_header *event);
396 void elog_fill_timestamp(struct event_header *event, uint8_t sec, uint8_t min,
397 			 uint8_t hour, uint8_t mday, uint8_t mon, uint16_t year);
398 /* Update the checksum at the last byte. */
399 void elog_update_checksum(struct event_header *event, uint8_t checksum);
400 /* Simple byte checksum for events. */
401 uint8_t elog_checksum_event(const struct event_header *event);
402 
403 #endif  /* _COMMONLIB_BSD_ELOG_H_ */
404