1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* 24 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. 25 * 26 * Use of this source code is governed by a BSD-style license 27 * that can be found in the LICENSE file in the root of the source 28 * tree. An additional intellectual property rights grant can be found 29 * in the file PATENTS. All contributing project authors may 30 * be found in the AUTHORS file in the root of the source tree. 31 */ 32 33 //! 34 //! \file codechal_vdenc_vp9_g11.h 35 //! \brief VP9 VDENC encoder for GEN11 platform. 36 //! 37 38 #ifndef __CODECHAL_VDENC_VP9_G11_H__ 39 #define __CODECHAL_VDENC_VP9_G11_H__ 40 41 #include "codechal.h" 42 #include "codechal_hw.h" 43 #include "codechal_vdenc_vp9_base.h" 44 #include "mhw_vdbox_g11_X.h" 45 #include "codechal_encode_singlepipe_virtualengine.h" 46 #include "codechal_encode_scalability.h" 47 48 #define CODECHAL_ENCODE_HME_FIRST_STEP_G11 0 49 #define CODECHAL_ENCODE_HME_FOLLOWING_STEP_G11 1 50 #define CODECHAL_ENCODE_MV_SHIFT_FACTOR_32x_G11 1 51 #define CODECHAL_ENCODE_MV_SHIFT_FACTOR_16x_G11 2 52 #define CODECHAL_ENCODE_MV_SHIFT_FACTOR_4x_G11 2 53 #define CODECHAL_ENCODE_PREV_MV_READ_POSITION_16x_G11 1 54 #define CODECHAL_ENCODE_PREV_MV_READ_POSITION_4x_G11 0 55 56 class CodechalVdencVp9StateG11 : public CodechalVdencVp9State 57 { 58 public: 59 enum MeBindingTableOffset 60 { 61 CODECHAL_ENCODE_ME_MV_DATA_SURFACE_G11 = 0, 62 CODECHAL_ENCODE_16xME_MV_DATA_SURFACE_G11 = 1, 63 CODECHAL_ENCODE_32xME_MV_DATA_SURFACE_G11 = 1, 64 CODECHAL_ENCODE_ME_DISTORTION_SURFACE_G11 = 2, 65 CODECHAL_ENCODE_ME_BRC_DISTORTION_G11 = 3, 66 CODECHAL_ENCODE_ME_RESERVED0_G11 = 4, 67 CODECHAL_ENCODE_ME_CURR_FOR_FWD_REF_G11 = 5, 68 CODECHAL_ENCODE_ME_FWD_REF_IDX0_G11 = 6, 69 CODECHAL_ENCODE_ME_RESERVED1_G11 = 7, 70 CODECHAL_ENCODE_ME_FWD_REF_IDX1_G11 = 8, 71 CODECHAL_ENCODE_ME_RESERVED2_G11 = 9, 72 CODECHAL_ENCODE_ME_FWD_REF_IDX2_G11 = 10, 73 CODECHAL_ENCODE_ME_RESERVED3_G11 = 11, 74 CODECHAL_ENCODE_ME_FWD_REF_IDX3_G11 = 12, 75 CODECHAL_ENCODE_ME_RESERVED4_G11 = 13, 76 CODECHAL_ENCODE_ME_FWD_REF_IDX4_G11 = 14, 77 CODECHAL_ENCODE_ME_RESERVED5_G11 = 15, 78 CODECHAL_ENCODE_ME_FWD_REF_IDX5_G11 = 16, 79 CODECHAL_ENCODE_ME_RESERVED6_G11 = 17, 80 CODECHAL_ENCODE_ME_FWD_REF_IDX6_G11 = 18, 81 CODECHAL_ENCODE_ME_RESERVED7_G11 = 19, 82 CODECHAL_ENCODE_ME_FWD_REF_IDX7_G11 = 20, 83 CODECHAL_ENCODE_ME_RESERVED8_G11 = 21, 84 CODECHAL_ENCODE_ME_CURR_FOR_BWD_REF_G11 = 22, 85 CODECHAL_ENCODE_ME_BWD_REF_IDX0_G11 = 23, 86 CODECHAL_ENCODE_ME_RESERVED9_G11 = 24, 87 CODECHAL_ENCODE_ME_BWD_REF_IDX1_G11 = 25, 88 CODECHAL_ENCODE_ME_VDENC_STREAMIN_OUTPUT_G11 = 26, 89 CODECHAL_ENCODE_ME_VDENC_STREAMIN_INPUT_G11 = 27, 90 CODECHAL_ENCODE_ME_NUM_SURFACES_G11 = 28 91 }; 92 93 struct StatsInfo 94 { 95 uint32_t tileSizeRecord; 96 uint32_t vdencStats; 97 uint32_t pakStats; 98 uint32_t counterBuffer; 99 }; 100 101 struct MeCurbe 102 { 103 // DW0 104 union 105 { 106 struct 107 { 108 uint32_t SkipModeEn : MOS_BITFIELD_BIT(0); 109 uint32_t AdaptiveEn : MOS_BITFIELD_BIT(1); 110 uint32_t BiMixDis : MOS_BITFIELD_BIT(2); 111 uint32_t : MOS_BITFIELD_RANGE(3, 4); 112 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT(5); 113 uint32_t : MOS_BITFIELD_BIT(6); 114 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT(7); 115 uint32_t : MOS_BITFIELD_RANGE(8, 23); 116 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 117 }; 118 struct 119 { 120 uint32_t Value; 121 }; 122 } DW0; 123 124 // DW1 125 union 126 { 127 struct 128 { 129 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE(0, 5); 130 uint32_t : MOS_BITFIELD_RANGE(6, 15); 131 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 132 uint32_t : MOS_BITFIELD_RANGE(22, 27); 133 uint32_t UniMixDisable : MOS_BITFIELD_BIT(28); 134 uint32_t : MOS_BITFIELD_RANGE(29, 31); 135 }; 136 struct 137 { 138 uint32_t Value; 139 }; 140 } DW1; 141 142 // DW2 143 union 144 { 145 struct 146 { 147 uint32_t MaxLenSP : MOS_BITFIELD_RANGE(0, 7); 148 uint32_t MaxNumSU : MOS_BITFIELD_RANGE(8, 15); 149 uint32_t : MOS_BITFIELD_RANGE(16, 31); 150 }; 151 struct 152 { 153 uint32_t Value; 154 }; 155 } DW2; 156 157 // DW3 158 union 159 { 160 struct 161 { 162 uint32_t SrcSize : MOS_BITFIELD_RANGE(0, 1); 163 uint32_t : MOS_BITFIELD_RANGE(2, 3); 164 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE(4, 5); 165 uint32_t SrcAccess : MOS_BITFIELD_BIT(6); 166 uint32_t RefAccess : MOS_BITFIELD_BIT(7); 167 uint32_t SearchCtrl : MOS_BITFIELD_RANGE(8, 10); 168 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT(11); 169 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 170 uint32_t SkipType : MOS_BITFIELD_BIT(14); 171 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT(15); 172 uint32_t InterChromaMode : MOS_BITFIELD_BIT(16); 173 uint32_t FTEnable : MOS_BITFIELD_BIT(17); 174 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT(18); 175 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT(19); 176 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 177 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 178 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 179 uint32_t : MOS_BITFIELD_BIT(31); 180 }; 181 struct 182 { 183 uint32_t Value; 184 }; 185 } DW3; 186 187 // DW4 188 union 189 { 190 struct 191 { 192 uint32_t : MOS_BITFIELD_RANGE(0, 7); 193 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 194 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 195 uint32_t : MOS_BITFIELD_RANGE(24, 31); 196 }; 197 struct 198 { 199 uint32_t Value; 200 }; 201 } DW4; 202 203 // DW5 204 union 205 { 206 struct 207 { 208 uint32_t : MOS_BITFIELD_RANGE(0, 7); 209 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 210 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 211 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 212 }; 213 struct 214 { 215 uint32_t Value; 216 }; 217 } DW5; 218 219 // DW6 220 union 221 { 222 struct 223 { 224 uint32_t : MOS_BITFIELD_BIT(0); 225 uint32_t InputStreamInSurfaceEnable : MOS_BITFIELD_BIT(1); 226 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 227 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 228 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 229 uint32_t : MOS_BITFIELD_RANGE(5, 7); 230 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 231 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 232 }; 233 struct 234 { 235 uint32_t Value; 236 }; 237 } DW6; 238 239 // DW7 240 union 241 { 242 struct 243 { 244 uint32_t : MOS_BITFIELD_RANGE(0, 15); 245 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 246 uint32_t BilinearEnable : MOS_BITFIELD_BIT(18); 247 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT(19); 248 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT(20); 249 uint32_t AConlyHAAR : MOS_BITFIELD_BIT(21); 250 uint32_t RefIDCostMode : MOS_BITFIELD_BIT(22); 251 uint32_t : MOS_BITFIELD_BIT(23); 252 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 253 }; 254 struct 255 { 256 uint32_t Value; 257 }; 258 } DW7; 259 260 // DW8 261 union 262 { 263 struct 264 { 265 uint32_t Mode0Cost : MOS_BITFIELD_RANGE(0, 7); 266 uint32_t Mode1Cost : MOS_BITFIELD_RANGE(8, 15); 267 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 268 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 269 }; 270 struct 271 { 272 uint32_t Value; 273 }; 274 } DW8; 275 276 // DW9 277 union 278 { 279 struct 280 { 281 uint32_t Mode4Cost : MOS_BITFIELD_RANGE(0, 7); 282 uint32_t Mode5Cost : MOS_BITFIELD_RANGE(8, 15); 283 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 284 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 285 }; 286 struct 287 { 288 uint32_t Value; 289 }; 290 } DW9; 291 292 // DW10 293 union 294 { 295 struct 296 { 297 uint32_t Mode8Cost : MOS_BITFIELD_RANGE(0, 7); 298 uint32_t Mode9Cost : MOS_BITFIELD_RANGE(8, 15); 299 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 300 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 301 }; 302 struct 303 { 304 uint32_t Value; 305 }; 306 } DW10; 307 308 // DW11 309 union 310 { 311 struct 312 { 313 uint32_t MV0Cost : MOS_BITFIELD_RANGE(0, 7); 314 uint32_t MV1Cost : MOS_BITFIELD_RANGE(8, 15); 315 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 316 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 317 }; 318 struct 319 { 320 uint32_t Value; 321 }; 322 } DW11; 323 324 // DW12 325 union 326 { 327 struct 328 { 329 uint32_t MV4Cost : MOS_BITFIELD_RANGE(0, 7); 330 uint32_t MV5Cost : MOS_BITFIELD_RANGE(8, 15); 331 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 332 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 333 }; 334 struct 335 { 336 uint32_t Value; 337 }; 338 } DW12; 339 340 // DW13 341 union 342 { 343 struct 344 { 345 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 346 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 347 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 348 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 349 uint32_t : MOS_BITFIELD_RANGE(27, 31); 350 }; 351 struct 352 { 353 uint32_t Value; 354 }; 355 } DW13; 356 357 // DW14 358 union 359 { 360 struct 361 { 362 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 363 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 364 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 365 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 366 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 367 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 368 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 369 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 370 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 371 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 372 uint32_t : MOS_BITFIELD_RANGE(10, 31); 373 }; 374 struct 375 { 376 uint32_t Value; 377 }; 378 } DW14; 379 380 // DW15 381 union 382 { 383 struct 384 { 385 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 386 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 387 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 388 }; 389 struct 390 { 391 uint32_t Value; 392 }; 393 } DW15; 394 395 struct 396 { 397 // DW16 398 union 399 { 400 struct 401 { 402 SearchPathDelta SPDelta_0; 403 SearchPathDelta SPDelta_1; 404 SearchPathDelta SPDelta_2; 405 SearchPathDelta SPDelta_3; 406 }; 407 struct 408 { 409 uint32_t Value; 410 }; 411 } DW16; 412 413 // DW17 414 union 415 { 416 struct 417 { 418 SearchPathDelta SPDelta_4; 419 SearchPathDelta SPDelta_5; 420 SearchPathDelta SPDelta_6; 421 SearchPathDelta SPDelta_7; 422 }; 423 struct 424 { 425 uint32_t Value; 426 }; 427 } DW17; 428 429 // DW18 430 union 431 { 432 struct 433 { 434 SearchPathDelta SPDelta_8; 435 SearchPathDelta SPDelta_9; 436 SearchPathDelta SPDelta_10; 437 SearchPathDelta SPDelta_11; 438 }; 439 struct 440 { 441 uint32_t Value; 442 }; 443 } DW18; 444 445 // DW19 446 union 447 { 448 struct 449 { 450 SearchPathDelta SPDelta_12; 451 SearchPathDelta SPDelta_13; 452 SearchPathDelta SPDelta_14; 453 SearchPathDelta SPDelta_15; 454 }; 455 struct 456 { 457 uint32_t Value; 458 }; 459 } DW19; 460 461 // DW20 462 union 463 { 464 struct 465 { 466 SearchPathDelta SPDelta_16; 467 SearchPathDelta SPDelta_17; 468 SearchPathDelta SPDelta_18; 469 SearchPathDelta SPDelta_19; 470 }; 471 struct 472 { 473 uint32_t Value; 474 }; 475 } DW20; 476 477 // DW21 478 union 479 { 480 struct 481 { 482 SearchPathDelta SPDelta_20; 483 SearchPathDelta SPDelta_21; 484 SearchPathDelta SPDelta_22; 485 SearchPathDelta SPDelta_23; 486 }; 487 struct 488 { 489 uint32_t Value; 490 }; 491 } DW21; 492 493 // DW22 494 union 495 { 496 struct 497 { 498 SearchPathDelta SPDelta_24; 499 SearchPathDelta SPDelta_25; 500 SearchPathDelta SPDelta_26; 501 SearchPathDelta SPDelta_27; 502 }; 503 struct 504 { 505 uint32_t Value; 506 }; 507 } DW22; 508 509 // DW23 510 union 511 { 512 struct 513 { 514 SearchPathDelta SPDelta_28; 515 SearchPathDelta SPDelta_29; 516 SearchPathDelta SPDelta_30; 517 SearchPathDelta SPDelta_31; 518 }; 519 struct 520 { 521 uint32_t Value; 522 }; 523 } DW23; 524 525 // DW24 526 union 527 { 528 struct 529 { 530 SearchPathDelta SPDelta_32; 531 SearchPathDelta SPDelta_33; 532 SearchPathDelta SPDelta_34; 533 SearchPathDelta SPDelta_35; 534 }; 535 struct 536 { 537 uint32_t Value; 538 }; 539 } DW24; 540 541 // DW25 542 union 543 { 544 struct 545 { 546 SearchPathDelta SPDelta_36; 547 SearchPathDelta SPDelta_37; 548 SearchPathDelta SPDelta_38; 549 SearchPathDelta SPDelta_39; 550 }; 551 struct 552 { 553 uint32_t Value; 554 }; 555 } DW25; 556 557 // DW26 558 union 559 { 560 struct 561 { 562 SearchPathDelta SPDelta_40; 563 SearchPathDelta SPDelta_41; 564 SearchPathDelta SPDelta_42; 565 SearchPathDelta SPDelta_43; 566 }; 567 struct 568 { 569 uint32_t Value; 570 }; 571 } DW26; 572 573 // DW27 574 union 575 { 576 struct 577 { 578 SearchPathDelta SPDelta_44; 579 SearchPathDelta SPDelta_45; 580 SearchPathDelta SPDelta_46; 581 SearchPathDelta SPDelta_47; 582 }; 583 struct 584 { 585 uint32_t Value; 586 }; 587 } DW27; 588 589 // DW28 590 union 591 { 592 struct 593 { 594 SearchPathDelta SPDelta_48; 595 SearchPathDelta SPDelta_49; 596 SearchPathDelta SPDelta_50; 597 SearchPathDelta SPDelta_51; 598 }; 599 struct 600 { 601 uint32_t Value; 602 }; 603 } DW28; 604 605 // DW29 606 union 607 { 608 struct 609 { 610 SearchPathDelta SPDelta_52; 611 SearchPathDelta SPDelta_53; 612 SearchPathDelta SPDelta_54; 613 SearchPathDelta SPDelta_55; 614 }; 615 struct 616 { 617 uint32_t Value; 618 }; 619 } DW29; 620 } SPDelta; 621 622 // DW30 623 union 624 { 625 struct 626 { 627 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 628 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 629 }; 630 struct 631 { 632 uint32_t Value; 633 }; 634 } DW30; 635 636 // DW31 637 union 638 { 639 struct 640 { 641 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 642 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 643 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 644 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 645 uint32_t : MOS_BITFIELD_RANGE(16, 23); 646 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 647 }; 648 struct 649 { 650 uint32_t Value; 651 }; 652 } DW31; 653 654 // DW32 655 union 656 { 657 struct 658 { 659 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 660 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 661 }; 662 struct 663 { 664 uint32_t Value; 665 }; 666 } DW32; 667 668 // DW33 669 union 670 { 671 struct 672 { 673 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 674 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 675 }; 676 struct 677 { 678 uint32_t Value; 679 }; 680 } DW33; 681 682 // DW34 683 union 684 { 685 struct 686 { 687 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 688 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 689 }; 690 struct 691 { 692 uint32_t Value; 693 }; 694 } DW34; 695 696 // DW35 697 union 698 { 699 struct 700 { 701 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 702 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 703 }; 704 struct 705 { 706 uint32_t Value; 707 }; 708 } DW35; 709 710 // DW36 711 union 712 { 713 struct 714 { 715 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 716 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 717 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 718 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 719 uint32_t NumMergeCandidateCu8x8 : MOS_BITFIELD_RANGE(16, 19); 720 uint32_t NumMergeCandidateCu16x16 : MOS_BITFIELD_RANGE(20, 23); 721 uint32_t NumMergeCandidateCu32x32 : MOS_BITFIELD_RANGE(24, 27); 722 uint32_t NumMergeCandidateCu64x64 : MOS_BITFIELD_RANGE(28, 31); 723 }; 724 struct 725 { 726 uint32_t Value; 727 }; 728 } DW36; 729 730 // DW37 731 union 732 { 733 struct 734 { 735 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 736 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 737 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 738 uint32_t : MOS_BITFIELD_RANGE(21, 22); 739 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 740 uint32_t : MOS_BITFIELD_RANGE(24, 31); 741 }; 742 struct 743 { 744 uint32_t Value; 745 }; 746 } DW37; 747 748 // DW38 749 union 750 { 751 struct 752 { 753 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 754 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 755 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 756 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 757 }; 758 struct 759 { 760 uint32_t Value; 761 }; 762 } DW38; 763 764 // DW39 765 union 766 { 767 struct 768 { 769 uint32_t : MOS_BITFIELD_RANGE(0, 31); 770 }; 771 struct 772 { 773 uint32_t Value; 774 }; 775 } DW39; 776 777 // DW40 778 union 779 { 780 struct 781 { 782 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 783 }; 784 struct 785 { 786 uint32_t Value; 787 }; 788 } DW40; 789 790 // DW41 791 union 792 { 793 struct 794 { 795 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 796 }; 797 struct 798 { 799 uint32_t Value; 800 }; 801 } DW41; 802 803 // DW42 804 union 805 { 806 struct 807 { 808 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 809 }; 810 struct 811 { 812 uint32_t Value; 813 }; 814 } DW42; 815 816 // DW43 817 union 818 { 819 struct 820 { 821 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 822 }; 823 struct 824 { 825 uint32_t Value; 826 }; 827 } DW43; 828 829 // DW44 830 union 831 { 832 struct 833 { 834 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 835 }; 836 struct 837 { 838 uint32_t Value; 839 }; 840 } DW44; 841 842 // DW45 843 union 844 { 845 struct 846 { 847 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 848 }; 849 struct 850 { 851 uint32_t Value; 852 }; 853 } DW45; 854 855 // DW46 856 union 857 { 858 struct 859 { 860 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 861 }; 862 struct 863 { 864 uint32_t Value; 865 }; 866 } DW46; 867 868 // DW47 869 union 870 { 871 struct 872 { 873 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 874 }; 875 struct 876 { 877 uint32_t Value; 878 }; 879 } DW47; 880 }; 881 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(MeCurbe)) == 48); 882 883 // ME CURBE init data for G11 Kernel 884 static const uint32_t meCurbeInit[48]; 885 886 struct HucPakIntDmem 887 { 888 uint32_t tileSizeRecordOffset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 889 uint32_t vdencStatOffset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 890 uint32_t hevcPakStatOffset[5]; // needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 891 uint32_t hevcStreamoutOffset[5]; // needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 892 uint32_t vp9PakStatOffset[5]; // needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 893 uint32_t vp9CounterBufferOffset[5]; // needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 894 uint32_t lastTileBSStartInBytes; // last tile in bitstream for region 4 and region 5 895 uint32_t SliceHeaderSizeinBits; // needed for HEVC dual pipe BRC 896 uint16_t totalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 897 uint16_t offsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t ) in the command buffer, 0xffff means unavailable 898 uint16_t picWidthInPixel; // Picture width in pixel 899 uint16_t picHeightInPixel; // Picture hieght in pixel 900 uint16_t totalNumberOfPaks; // [2..4] for Gen11 901 uint16_t numSlices[4]; // this is number of slices in each PAK 902 uint16_t numTiles[4]; // this is number of tiles from each PAK 903 uint16_t picStateStartInBytes; // offset for region 7 and region 8 904 uint8_t codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 905 uint8_t maxPass; // Max number of BRC pass >=1 906 uint8_t currentPass; // Current BRC pass [1..MAXPass] 907 uint8_t minCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 908 uint8_t cabacZeroWordFlag; // Cabac zero flag, HEVC only 909 uint8_t bitdepthLuma; // luma bitdepth, HEVC only 910 uint8_t bitdepthChroma; // chroma bitdepth, HEVC only 911 uint8_t chromaFormatIdc; // chroma format idc, HEVC only 912 uint8_t currFrameBRClevel; // Hevc dual pipe only 913 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 914 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 915 uint8_t reserved1; 916 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 917 uint16_t reserved2; 918 uint32_t BBEndforStitch; 919 uint8_t RSVD[16]; 920 }; 921 922 // Delay between semaphore(barrier) wait and reset 923 static constexpr uint32_t m_numDelay = 15; 924 // VDENC BRC related buffer size 925 static constexpr uint32_t m_brcStatsBufSize = ((48 + 256) * sizeof(uint32_t)); // 48 DWs of statistics data at the end of every tile that will be used by the BRC kernel. 64 byte aligned. 256 DWs of Histogram data at an offset of 3 CLs (48 DWs) 926 static constexpr uint32_t m_brcPakStatsBufSize = (64 * sizeof(uint32_t)); 927 static constexpr uint32_t m_brcHistoryBufSize = 1152; 928 // VDENC Pak Int related constants 929 static constexpr uint32_t m_pakIntDmemOffsetsSize = 120; 930 static constexpr uint32_t m_pakIntVp9CodecId = 3; 931 static constexpr uint32_t m_maxNumPipes = 4; 932 // SHME related 933 static constexpr uint32_t m_hmeMaxMvLength = 511; 934 CODEC_PICTURE m_refPicList0[3]; 935 936 // Virtual engine 937 //Scalability 938 uint8_t m_numPipe = 0; 939 uint8_t m_numPassesInOnePipe = 0; 940 bool m_scalableMode = false; 941 bool m_lastFrameScalableMode = false; 942 bool m_isTilingSupported = false; 943 bool m_enableTileStitchByHW = true; 944 bool m_useVirtualEngine = true; 945 MOS_COMMAND_BUFFER m_veBatchBuffer[m_numUncompressedSurface][CODECHAL_ENCODE_VP9_MAX_NUM_HCP_PIPE][m_brcMaxNumPasses]; 946 MOS_COMMAND_BUFFER m_realCmdBuffer; 947 uint32_t m_sizeOfVEBatchBuffer = 0; 948 uint8_t m_virtualEngineBBIndex = 0; 949 uint32_t m_32BlocksRasterized = 0; 950 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState = nullptr; //!< Scalability state 951 952 // Stats Integration regions 953 CODECHAL_ENCODE_BUFFER m_hcpScalabilitySyncBuffer = {}; 954 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[m_numUncompressedSurface] = {}; 955 CODECHAL_ENCODE_BUFFER m_tileStatsPakIntegrationBuffer[m_numUncompressedSurface] = {}; 956 uint32_t m_tileStatsPakIntegrationBufferSize = 0; 957 CODECHAL_ENCODE_BUFFER m_frameStatsPakIntegrationBuffer = {}; 958 uint32_t m_frameStatsPakIntegrationBufferSize = 0; 959 MOS_RESOURCE m_hucPakIntDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][m_brcMaxNumPasses] = {}; 960 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS m_hpuVirtualAddrParams = {}; 961 MOS_RESOURCE m_hucPakIntDummyBuffer = {}; 962 MOS_RESOURCE m_hucPakIntBrcDataBuffer = {}; 963 StatsInfo m_tileStatsOffset = {}; // Page aligned offsets for HuC PAK Integration kernel input 964 StatsInfo m_frameStatsOffset = {}; // Page aligned offsets for HuC PAK Integration kernel output 965 StatsInfo m_statsSize = {}; // Sizes for the stats for HuC PAK Integration kernel input 966 // Semaphore memory for synchronizing 967 MOS_RESOURCE m_resPipeStartSync = {}; 968 MOS_RESOURCE m_resFrameStartSync = {}; 969 CODECHAL_ENCODE_BUFFER m_stitchWaitSemaphoreMem[m_maxNumPipes] = {}; 970 MOS_RESOURCE m_resDelayMinus = {}; 971 uint16_t m_lastVdencPictureState2ndLevelBBIndex = 0; 972 973 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 m_tileParams = nullptr; //!< Pointer to the Tile params 974 975 //! 976 //! \brief Constructor 977 //! 978 CodechalVdencVp9StateG11(CodechalHwInterface* hwInterface, 979 CodechalDebugInterface* debugInterface, 980 PCODECHAL_STANDARD_INFO standardInfo); 981 982 //! 983 //! \brief Destructor 984 //! 985 virtual ~CodechalVdencVp9StateG11(); 986 GetCurrentPipe()987 int GetCurrentPipe() 988 { 989 return (m_numPipe <= 1) ? 0 : (int)(m_currPass) % (int)m_numPipe; 990 } 991 GetCurrentPass()992 int GetCurrentPass() override 993 { 994 return (m_numPipe <= 1) ? m_currPass : (int)(m_currPass) / (int)m_numPipe; 995 } 996 GetNumPasses()997 int GetNumPasses() override 998 { 999 return m_numPassesInOnePipe; 1000 } 1001 IsLastPipe()1002 bool IsLastPipe() 1003 { 1004 return (GetCurrentPipe() == (m_numPipe - 1)) ? true : false; 1005 } 1006 IsFirstPipe()1007 bool IsFirstPipe() 1008 { 1009 return (GetCurrentPipe() == 0) ? true : false; 1010 } 1011 IsFirstPass()1012 bool IsFirstPass() override 1013 { 1014 return (GetCurrentPass() == 0) ? true : false; 1015 } 1016 IsLastPass()1017 bool IsLastPass() override 1018 { 1019 return (GetCurrentPass() == m_numPassesInOnePipe) ? true : false; 1020 } 1021 UseLegacyCommandBuffer()1022 bool UseLegacyCommandBuffer() 1023 { 1024 return ((!m_scalableMode) || (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext)); 1025 } 1026 IsRenderContext()1027 bool IsRenderContext() 1028 { 1029 return (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext); 1030 } 1031 1032 MOS_STATUS VerifyCommandBufferSize() override; 1033 1034 MOS_STATUS GetSystemPipeNumberCommon(); 1035 1036 MOS_STATUS InitKernelStateMe(); 1037 1038 MOS_STATUS SendMeSurfaces( 1039 PMOS_COMMAND_BUFFER cmdBuffer, 1040 MeSurfaceParams * params); 1041 1042 MOS_STATUS GetCommandBuffer( 1043 PMOS_COMMAND_BUFFER cmdBuffer) override; 1044 1045 MOS_STATUS ReturnCommandBuffer( 1046 PMOS_COMMAND_BUFFER cmdBuffer) override; 1047 1048 MOS_STATUS SubmitCommandBuffer( 1049 PMOS_COMMAND_BUFFER cmdBuffer, 1050 bool bNullRendering) override; 1051 1052 MOS_STATUS SetMeCurbeParams( 1053 MeCurbeParams* meParams); 1054 1055 MOS_STATUS SetMeSurfaceParams( 1056 MeSurfaceParams* meSurfaceParams); 1057 1058 MOS_STATUS SendPrologWithFrameTracking( 1059 PMOS_COMMAND_BUFFER cmdBuffer, 1060 bool frameTrackingRequested, 1061 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr) override; 1062 1063 MOS_STATUS SetSemaphoreMem( 1064 PMOS_RESOURCE semaphoreMem, 1065 PMOS_COMMAND_BUFFER cmdBuffer, 1066 uint32_t value); 1067 1068 MOS_STATUS UserFeatureKeyReport() override; 1069 1070 MOS_STATUS SendMIAtomicCmd( 1071 PMOS_RESOURCE semaMem, 1072 uint32_t immData, 1073 MHW_COMMON_MI_ATOMIC_OPCODE opCode, 1074 PMOS_COMMAND_BUFFER cmdBuffer 1075 ); 1076 1077 MOS_STATUS SendHWWaitCommand( 1078 PMOS_RESOURCE semaphoreMem, 1079 PMOS_COMMAND_BUFFER cmdBuffer, 1080 uint32_t value); 1081 1082 MOS_STATUS ConstructPicStateBatchBuf( 1083 PMOS_RESOURCE picStateBuffer) override; 1084 1085 MOS_STATUS SetDmemHuCPakInt(); 1086 1087 MOS_STATUS HuCVp9PakInt( 1088 PMOS_COMMAND_BUFFER cmdBuffer); 1089 1090 MOS_STATUS HuCVp9Prob() override; 1091 1092 MOS_STATUS HuCBrcUpdate() override; 1093 1094 MOS_STATUS HuCBrcInitReset() override; 1095 1096 MOS_STATUS SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams, 1097 PMOS_SURFACE* refSurface, 1098 PMOS_SURFACE* refSurfaceNonScaled, 1099 PMOS_SURFACE* dsRefSurface4x, 1100 PMOS_SURFACE* dsRefSurface8x) override; 1101 1102 uint16_t GetNumTilesInFrame(); 1103 1104 MOS_STATUS ExecutePictureLevel() override; 1105 1106 MOS_STATUS SetSequenceStructs() override; 1107 1108 MOS_STATUS SetPictureStructs() override; 1109 1110 MOS_STATUS AllocateResources() override; 1111 1112 void FreeResources() override; 1113 1114 MOS_STATUS SetCurbeMe( 1115 MeCurbeParams *params); 1116 1117 MOS_STATUS ExecuteKernelFunctions() override; 1118 1119 MOS_STATUS ExecuteMeKernel( 1120 MeCurbeParams * meParams, 1121 MeSurfaceParams *meSurfaceParams, 1122 HmeLevel hmeLevel) override; 1123 1124 MOS_STATUS SetupSegmentationStreamIn() override; 1125 1126 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; 1127 1128 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams) override; 1129 1130 MOS_STATUS ExecuteSliceLevel() override; 1131 1132 MOS_STATUS ExecuteDysSliceLevel() override; 1133 1134 MOS_STATUS Initialize(CodechalSetting * settings) override; 1135 1136 MOS_STATUS InitKernelStates(); 1137 1138 uint32_t GetMaxBtCount(); 1139 1140 MOS_STATUS InitKernelStateDys(); 1141 1142 MOS_STATUS ExecuteTileLevel(); 1143 1144 MOS_STATUS SetTileData(); 1145 1146 MOS_STATUS SetGpuCtxCreatOption() override; 1147 1148 MOS_STATUS SetTileCommands( 1149 PMOS_COMMAND_BUFFER cmdBuffer); 1150 1151 MOS_STATUS GetStatusReport( 1152 EncodeStatus* encodeStatus, 1153 EncodeStatusReport* encodeStatusReport) override; 1154 1155 MOS_STATUS DecideEncodingPipeNumber(); 1156 1157 MOS_STATUS PlatformCapabilityCheck() override; 1158 1159 uint32_t GetSegmentBlockIndexInFrame( 1160 uint32_t frameWidth, 1161 uint32_t curr32XInTile, 1162 uint32_t curr32YInTile, 1163 uint32_t currTileStartY64aligned, 1164 uint32_t currTileStartX64aligned); 1165 1166 MOS_STATUS InitZigZagToRasterLUTPerTile( 1167 uint32_t tileHeight, 1168 uint32_t tileWidth, 1169 uint32_t currTileStartYInFrame, 1170 uint32_t currTileStartXInFrame); 1171 1172 MOS_STATUS CalculateVdencPictureStateCommandSize() override; 1173 1174 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS CreateHcpPipeBufAddrParams( 1175 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams) override; 1176 1177 MOS_STATUS UpdateCmdBufAttribute( 1178 PMOS_COMMAND_BUFFER cmdBuffer, 1179 bool renderEngineInUse) override; 1180 1181 //! 1182 //! \brief Set And Populate VE Hint parameters 1183 //! \details Set Virtual Engine hint parameter and populate it to primary cmd buffer attributes 1184 //! \param [in] cmdBuffer 1185 //! Pointer to primary cmd buffer 1186 //! \return MOS_STATUS 1187 //! MOS_STATUS_SUCCESS if success, else fail reason 1188 //! 1189 MOS_STATUS SetAndPopulateVEHintParams( 1190 PMOS_COMMAND_BUFFER cmdBuffer); 1191 1192 }; 1193 #endif // __CODECHAL_VDENC_VP9_G11_H__ 1194