1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_vdenc_hevc_g11.h 24 //! \brief HEVC VDEnc encoder for GEN11 platform. 25 //! 26 27 #ifndef __CODECHAL_VDENC_HEVC__G11_H__ 28 #define __CODECHAL_VDENC_HEVC__G11_H__ 29 30 #include "codechal_vdenc_hevc.h" 31 #include "mhw_vdbox_g11_X.h" 32 #include "codechal_encode_singlepipe_virtualengine.h" 33 #include "codechal_encode_scalability.h" 34 35 #define VDBOX_HUC_PAK_INTEGRATION_KERNEL_DESCRIPTOR 15 36 37 struct CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G11 38 { 39 uint32_t BRCFunc_U32; // 0: Init; 2: Reset 40 uint32_t UserMaxFrame; // ProfileLevelMaxFrame_U32 41 uint32_t InitBufFull_U32; 42 uint32_t BufSize_U32; 43 uint32_t TargetBitrate_U32; 44 uint32_t MaxRate_U32; 45 uint32_t MinRate_U32; 46 uint32_t FrameRateM_U32; 47 uint32_t FrameRateD_U32; 48 uint32_t LumaLog2WeightDenom_U32; 49 uint32_t ChromaLog2WeightDenom_U32; 50 uint8_t BRCFlag : 7; // ACQP/ICQ=0, CBR=1, VBR=2, VCM=3, LOWDELAY=4 51 uint8_t SSCFlag : 1; // SSC: 0x80 52 uint8_t Reserved; 53 uint16_t GopP_U16; 54 uint16_t GopB_U16; 55 uint16_t FrameWidth_U16; 56 uint16_t FrameHeight_U16; 57 uint16_t GopB1_U16; 58 uint16_t GopB2_U16; 59 uint8_t MinQP_U8; 60 uint8_t MaxQP_U8; 61 uint8_t MaxBRCLevel_U8; 62 uint8_t LumaBitDepth_U8; 63 uint8_t ChromaBitDepth_U8; 64 uint8_t CuQpCtrl_U8; // 0=No CUQP; 1=CUQP for I-frame; 2=CUQP for P/B-frame 65 66 uint8_t RSVD0[4]; 67 int8_t DevThreshPB0_S8[8]; 68 int8_t DevThreshVBR0_S8[8]; 69 int8_t DevThreshI0_S8[8]; 70 int8_t InstRateThreshP0_S8[4]; 71 int8_t InstRateThreshB0_S8[4]; 72 int8_t InstRateThreshI0_S8[4]; 73 uint8_t LowDelayMode_U8; 74 uint8_t InitQPIP_U8; 75 uint8_t InitQPB_U8; // In CQP mode, InitQPB_U8= InitQPIP_U8 76 uint8_t QPDeltaThrForAdapt2Pass_U8; 77 uint8_t TopFrmSzThrForAdapt2Pass_U8; 78 uint8_t BotFrmSzThrForAdapt2Pass_U8; 79 uint8_t QPSelectForFirstPass_U8; 80 uint8_t MBHeaderCompensation_U8; 81 uint8_t OverShootCarryFlag_U8; 82 uint8_t OverShootSkipFramePct_U8; 83 uint8_t EstRateThreshP0_U8[7]; 84 uint8_t EstRateThreshB0_U8[7]; 85 86 uint8_t EstRateThreshI0_U8[7]; 87 uint8_t QPP_U8; 88 uint8_t StreamInSurfaceEnable_U8; // 0-disabled, 1-enabled 89 uint8_t StreamInROIEnable_U8; // 0-disabled, 1-enabled 90 uint8_t TimingBudget_Enable_U8; // 0-disabled, 1-enabled 91 uint8_t RDOQ_AdaptationEnable_U8; // 0-disabled, 1-enabled 92 uint8_t RDOQ_IntraPctThreshold_U8; // 10 93 uint8_t RDOQ_HighIntraDistanceThreshold_U8; // 1 94 uint8_t TopQPDeltaThrForAdapt2Pass_U8; // 2 95 uint8_t BotQPDeltaThrForAdapt2Pass_U8; // 1 96 uint8_t RESERVED[2]; 97 uint8_t NetworkTraceEnable_U8; // 0-disabled, 1-enabled 98 uint8_t LowDelaySceneChangeXFrameSizeEnable_U8; // 0-disabled, 1-enabled 99 uint32_t ACQP_U32; // 1 100 uint32_t SlidingWindow_Size_U32; // 30 101 uint8_t SlidingWindow_MaxRateRatio_U8; 102 uint8_t RSVD2; 103 104 int8_t CbQPOffset; // -1 105 int8_t CrQPOffset; // -1 106 107 uint32_t ProfileLevelMaxFramePB_U32; 108 uint8_t BRCPyramidEnable_U8; 109 uint8_t LongTermRefEnable_U8; 110 uint16_t LongTermRefInterval_U16; 111 uint32_t RSVD1[6]; 112 }; 113 C_ASSERT(192 == sizeof(CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G11)); 114 115 using PCODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G11 = CODECHAL_VDENC_HEVC_HUC_BRC_INIT_DMEM_G11*; 116 117 struct CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G11 118 { 119 uint32_t TARGETSIZE_U32; 120 uint32_t FrameID_U32; // frame number 121 uint32_t Ref_L0_FrameID_U32[8]; 122 uint32_t Ref_L1_FrameID_U32[8]; 123 uint16_t startGAdjFrame_U16[4]; // 10, 50, 100, 150 124 uint16_t TargetSliceSize_U16; 125 uint16_t SLB_Data_SizeInBytes; // Region12 group 3 batch buffer data size 126 uint16_t PIC_STATE_StartInBytes; // PIC_STATE starts in byte. 0xFFFF means not available in SLB 127 uint16_t CMD2_StartInBytes; 128 uint16_t CMD1_StartInBytes; 129 uint16_t PIPE_MODE_SELECT_StartInBytes; // PIPE Mode select starts in byte. 0xFFFF means not available in SLB 130 uint16_t Current_Data_Offset; // Data block offset of current picture from beginning of the data buffer (region 9) 131 uint16_t Ref_Data_Offset[3]; // Data block offset of ref pictures from beginning of the data buffer (region 9) 132 uint16_t MaxNumSliceAllowed_U16; 133 uint8_t OpMode_U8; // 1: BRC, 2: Weighted prediction 134 uint8_t CurrentFrameType_U8; 135 uint8_t Num_Ref_L0_U8; 136 uint8_t Num_Ref_L1_U8; 137 uint8_t Num_Slices; 138 uint8_t CQP_QPValue_U8; // CQP QP value (needed for ICQ and ACQP) 139 uint8_t CQP_FracQP_U8; 140 uint8_t MaxNumPass_U8; // max number of BRC passes (SAO second pass is not included.) 141 uint8_t gRateRatioThreshold_U8[7]; 142 uint8_t startGAdjMult_U8[5]; 143 uint8_t startGAdjDiv_U8[5]; 144 uint8_t gRateRatioThresholdQP_U8[8]; 145 uint8_t SceneChgPrevIntraPctThreshold_U8; 146 uint8_t SceneChgCurIntraPctThreshold_U8; 147 uint8_t IPAverageCoeff_U8; 148 uint8_t CurrentPass_U8; 149 int8_t DeltaQPForMvZero_S8; 150 int8_t DeltaQPForMvZone0_S8; 151 int8_t DeltaQPForMvZone1_S8; 152 int8_t DeltaQPForMvZone2_S8; 153 int8_t DeltaQPForSadZone0_S8; 154 int8_t DeltaQPForSadZone1_S8; 155 int8_t DeltaQPForSadZone2_S8; 156 int8_t DeltaQPForSadZone3_S8; 157 int8_t DeltaQPForROI0_S8; 158 int8_t DeltaQPForROI1_S8; 159 int8_t DeltaQPForROI2_S8; 160 int8_t DeltaQPForROI3_S8; 161 int8_t LumaLog2WeightDenom_S8; // default: 6 162 int8_t ChromaLog2WeightDenom_S8; // default: 6 163 uint8_t DisabledFeature_U8; 164 uint8_t SlidingWindow_Enable_U8; // 0-disabled, 1-enabled 165 uint8_t LOG_LCU_Size_U8; // 6 166 uint8_t RDOQ_Enable_U8; // 0-disabled, 1-enabled 167 uint16_t NetworkTraceEntry_U16; // default: 0 168 uint16_t LowDelaySceneChangeXFrameSize_U16; // default: 0 169 int8_t ReEncodePositiveQPDeltaThr_S8; // default: 4 170 int8_t ReEncodeNegativeQPDeltaThr_S8; // default: -10 171 uint32_t NumFrameSkipped; 172 uint32_t SkipFrameSize; 173 uint32_t SliceHeaderSize; 174 int8_t EnableMotionAdaptive; 175 uint8_t FrameSizeBoostForSceneChange;// UPD_TCBRC_SCENARIO_U8 176 uint8_t ROMCurrent; // ROM average of current frame 177 uint8_t ROMZero; // ROM zero percentage 178 uint32_t TargetFrameSize; // TR_BRC 179 uint8_t RSVD[8]; // 64-byte alignment 180 }; 181 C_ASSERT(192 == sizeof(CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G11)); 182 183 using PCODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G11 = CODECHAL_VDENC_HEVC_HUC_BRC_UPDATE_DMEM_G11*; 184 185 struct CODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G11 186 { 187 uint16_t SADQPLambdaI[52]; 188 uint16_t SADQPLambdaP[52]; 189 uint16_t RDQPLambdaI[52]; 190 uint16_t RDQPLambdaP[52]; 191 uint16_t SLCSZ_THRDELTAI_U16[52]; 192 uint16_t SLCSZ_THRDELTAP_U16[52]; 193 uint8_t DistThreshldI[9]; 194 uint8_t DistThreshldP[9]; 195 uint8_t DistThreshldB[9]; 196 uint8_t DistQPAdjTabI[81]; 197 uint8_t DistQPAdjTabP[81]; 198 uint8_t DistQPAdjTabB[81]; 199 int8_t FrmSzAdjTabI_S8[72]; 200 int8_t FrmSzAdjTabP_S8[72]; 201 int8_t FrmSzAdjTabB_S8[72]; 202 uint8_t FrmSzMaxTabI[9]; 203 uint8_t FrmSzMaxTabP[9]; 204 uint8_t FrmSzMaxTabB[9]; 205 uint8_t FrmSzMinTabI[9]; 206 uint8_t FrmSzMinTabP[9]; 207 uint8_t FrmSzMinTabB[9]; 208 uint8_t QPAdjTabI[45]; 209 uint8_t QPAdjTabP[45]; 210 uint8_t QPAdjTabB[45]; 211 struct 212 { 213 uint8_t I_INTRA_64X64DC; // added later since I frame needs to be setup differently 214 uint8_t I_INTRA_32x32; 215 uint8_t I_INTRA_16x16; 216 uint8_t I_INTRA_8x8; 217 uint8_t I_INTRA_SADMPM; 218 uint8_t I_INTRA_RDEMPM; 219 uint8_t I_INTRA_NxN; 220 uint8_t INTRA_64X64DC; 221 uint8_t INTRA_32x32; 222 uint8_t INTRA_16x16; 223 uint8_t INTRA_8x8; 224 uint8_t INTRA_SADMPM; 225 uint8_t INTRA_RDEMPM; 226 uint8_t INTRA_NxN; 227 uint8_t INTER_32x32; 228 uint8_t INTER_32x16; 229 uint8_t INTER_16x16; 230 uint8_t INTER_16x8; 231 uint8_t INTER_8x8; 232 uint8_t REF_ID; 233 uint8_t MERGE_64X64; 234 uint8_t MERGE_32X32; 235 uint8_t MERGE_16x16; 236 uint8_t MERGE_8x8; 237 uint8_t SKIP_64X64; 238 uint8_t SKIP_32X32; 239 uint8_t SKIP_16x16; 240 uint8_t SKIP_8x8; 241 } ModeCosts[52]; 242 struct 243 { 244 // Unit in Bytes 245 uint16_t SizeOfCMDs; 246 uint16_t HcpWeightOffsetL0_StartInBytes; // HCP_WEIGHTOFFSET_L0 starts in bytes from beginning of the SLB. 0xFFFF means unavailable in SLB 247 uint16_t HcpWeightOffsetL1_StartInBytes; // HCP_WEIGHTOFFSET_L1 starts in bytes from beginning of the SLB. 0xFFFF means unavailable in SLB 248 uint16_t SliceState_StartInBytes; 249 uint16_t SliceHeaderPIO_StartInBytes; 250 uint16_t VdencWeightOffset_StartInBytes; 251 // Unit in Bits 252 uint16_t SliceHeader_SizeInBits; 253 uint16_t WeightTable_StartInBits; // number of bits from beginning of slice header for weight table first bit, 0xffff means not awailable 254 uint16_t WeightTable_EndInBits; // number of bits from beginning of slice header for weight table last bit, 0xffff means not awailable 255 } Slice[CODECHAL_VDENC_HEVC_MAX_SLICE_NUM]; 256 // motion adaptive 257 uint8_t QPAdaptiveWeight[52]; 258 uint8_t boostTable[52]; 259 uint8_t PenaltyForIntraNonDC32x32PredMode[52]; 260 }; 261 262 using PCODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G11 = CODECHAL_VDENC_HEVC_HUC_BRC_CONSTANT_DATA_G11*; 263 264 //! 265 //! \struct HucPakStitchDmemVdencG11 266 //! \brief The struct of Huc Com Dmem 267 //! 268 struct HucPakStitchDmemVdencG11 269 { 270 uint32_t TileSizeRecord_offset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 271 uint32_t VDENCSTAT_offset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 272 uint32_t HEVC_PAKSTAT_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 273 uint32_t HEVC_Streamout_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 274 uint32_t VP9_PAK_STAT_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 275 uint32_t Vp9CounterBuffer_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 276 uint32_t LastTileBS_StartInBytes;// last tile in bitstream for region 4 and region 5 277 uint32_t SliceHeaderSizeinBits; // needed for HEVC dual pipe BRC 278 uint16_t TotalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 279 uint16_t OffsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t) in the command buffer, 0xffff means unavailable 280 uint16_t PicWidthInPixel; // Picture width in pixel 281 uint16_t PicHeightInPixel; // Picture hieght in pixel 282 uint16_t TotalNumberOfPAKs; // [2..4] 283 uint16_t NumSlices[4]; // this is number of slices from each PAK 284 uint16_t NumTiles[4]; // this is number of tiles from each PAK 285 uint16_t PIC_STATE_StartInBytes;// offset for region 7 and region 8 286 uint8_t Codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 287 uint8_t MAXPass; // Max number of BRC pass >=1 288 uint8_t CurrentPass; // Current BRC pass [1..MAXPass] 289 uint8_t MinCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 290 uint8_t CabacZeroWordFlag; // cabac zero flag, HEVC only 291 uint8_t bitdepth_luma; // luma bitdepth, HEVC only 292 uint8_t bitdepth_chroma; // chroma bitdepth, HEVC only 293 uint8_t ChromaFormatIdc; // chroma format idc, HEVC only 294 uint8_t currFrameBRClevel; // Hevc dual pipe only 295 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 296 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 297 uint8_t reserved1; 298 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 299 uint16_t reserved2; 300 uint32_t BBEndforStitch; 301 uint8_t RSVD[16]; 302 }; 303 304 struct CODECHAL_VDENC_HEVC_STREAMIN_STATE_G11 305 { 306 // DWORD 0 307 union { 308 struct { 309 uint32_t RoiCtrl : MOS_BITFIELD_RANGE( 0,7 ); 310 uint32_t MaxTuSize : MOS_BITFIELD_RANGE( 8,9 ); 311 uint32_t MaxCuSize : MOS_BITFIELD_RANGE( 10,11 ); 312 uint32_t NumImePredictors : MOS_BITFIELD_RANGE( 12,15 ); 313 uint32_t Reserved_0 : MOS_BITFIELD_RANGE( 16,23 ); 314 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE( 24,31 ); 315 }; 316 uint32_t Value; 317 } DW0; 318 319 // DWORD 1-4 320 union { 321 struct { 322 uint32_t ForceMvX : MOS_BITFIELD_RANGE( 0,15 ); 323 uint32_t ForceMvY : MOS_BITFIELD_RANGE( 16,31 ); 324 }; 325 uint32_t Value; 326 } DW1[4]; 327 328 // DWORD 5 329 union { 330 struct { 331 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 ); 332 }; 333 uint32_t Value; 334 } DW5; 335 336 // DWORD 6 337 union { 338 struct { 339 uint32_t ForceRefIdx : MOS_BITFIELD_RANGE( 0,15 ); //4-bits per 16x16 block 340 uint32_t NumMergeCandidateCu8x8 : MOS_BITFIELD_RANGE( 16,19 ); 341 uint32_t NumMergeCandidateCu16x16 : MOS_BITFIELD_RANGE( 20,23 ); 342 uint32_t NumMergeCandidateCu32x32 : MOS_BITFIELD_RANGE( 24,27 ); 343 uint32_t NumMergeCandidateCu64x64 : MOS_BITFIELD_RANGE( 28,31 ); 344 }; 345 uint32_t Value; 346 } DW6; 347 348 // DWORD 7 349 union { 350 struct { 351 uint32_t SegID : MOS_BITFIELD_RANGE( 0,15 ); //4-bits per 16x16 block 352 uint32_t QpEnable : MOS_BITFIELD_RANGE( 16,19 ); 353 uint32_t SegIDEnable : MOS_BITFIELD_RANGE( 20,20 ); 354 uint32_t Reserved : MOS_BITFIELD_RANGE( 21,22 ); 355 uint32_t ForceRefIdEnable : MOS_BITFIELD_RANGE( 23,23 ); 356 uint32_t ImePredictorSelect : MOS_BITFIELD_RANGE( 24,31 ); 357 }; 358 uint32_t Value; 359 } DW7; 360 361 // DWORD 8-11 362 union { 363 struct { 364 uint32_t ImePredictorMvX : MOS_BITFIELD_RANGE( 0,15 ); 365 uint32_t ImePredictorMvY : MOS_BITFIELD_RANGE( 16,31 ); 366 }; 367 uint32_t Value; 368 } DW8[4]; 369 370 // DWORD 12 371 union { 372 struct { 373 uint32_t ImePredictorRefIdx : MOS_BITFIELD_RANGE( 0,15 ); //4-bits per 16x16 block 374 uint32_t Reserved : MOS_BITFIELD_RANGE( 16,31 ); 375 }; 376 uint32_t Value; 377 } DW12; 378 379 // DWORD 13 380 union { 381 struct { 382 uint32_t PanicModeLCUThreshold : MOS_BITFIELD_RANGE( 0,15 ); 383 uint32_t Reserved : MOS_BITFIELD_RANGE( 16,31 ); 384 }; 385 uint32_t Value; 386 } DW13; 387 388 // DWORD 14 389 union { 390 struct { 391 uint32_t ForceQp_0 : MOS_BITFIELD_RANGE( 0,7 ); 392 uint32_t ForceQp_1 : MOS_BITFIELD_RANGE( 8,15 ); 393 uint32_t ForceQp_2 : MOS_BITFIELD_RANGE( 16,23 ); 394 uint32_t ForceQp_3 : MOS_BITFIELD_RANGE( 24,31 ); 395 }; 396 uint32_t Value; 397 } DW14; 398 399 // DWORD 15 400 union { 401 struct { 402 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 ); 403 }; 404 uint32_t Value; 405 } DW15; 406 }; 407 C_ASSERT(SIZE32(CODECHAL_VDENC_HEVC_STREAMIN_STATE_G11) == 16); 408 409 using PCODECHAL_VDENC_HEVC_STREAMIN_STATE_G11 = CODECHAL_VDENC_HEVC_STREAMIN_STATE_G11*; 410 411 struct CODECHAL_VDENC_HEVC_ME_CURBE_G11 412 { 413 // DW0 414 union 415 { 416 struct 417 { 418 uint32_t SkipModeEn : MOS_BITFIELD_BIT( 0 ); 419 uint32_t AdaptiveEn : MOS_BITFIELD_BIT( 1 ); 420 uint32_t BiMixDis : MOS_BITFIELD_BIT( 2 ); 421 uint32_t : MOS_BITFIELD_RANGE( 3, 4 ); 422 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT( 5 ); 423 uint32_t : MOS_BITFIELD_BIT( 6 ); 424 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT( 7 ); 425 uint32_t : MOS_BITFIELD_RANGE( 8,23 ); 426 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE( 24,31 ); 427 }; 428 struct 429 { 430 uint32_t Value; 431 }; 432 } DW0; 433 434 // DW1 435 union 436 { 437 struct 438 { 439 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE( 0, 5 ); 440 uint32_t : MOS_BITFIELD_RANGE( 6,15 ); 441 uint32_t BiWeight : MOS_BITFIELD_RANGE( 16,21 ); 442 uint32_t : MOS_BITFIELD_RANGE( 22,27 ); 443 uint32_t UniMixDisable : MOS_BITFIELD_BIT( 28 ); 444 uint32_t : MOS_BITFIELD_RANGE( 29,31 ); 445 }; 446 struct 447 { 448 uint32_t Value; 449 }; 450 } DW1; 451 452 // DW2 453 union 454 { 455 struct 456 { 457 uint32_t MaxLenSP : MOS_BITFIELD_RANGE( 0, 7 ); 458 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8, 15 ); 459 uint32_t : MOS_BITFIELD_RANGE( 16, 31); 460 }; 461 struct 462 { 463 uint32_t Value; 464 }; 465 } DW2; 466 467 // DW3 468 union 469 { 470 struct 471 { 472 uint32_t SrcSize : MOS_BITFIELD_RANGE( 0, 1 ); 473 uint32_t : MOS_BITFIELD_RANGE( 2, 3 ); 474 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE( 4, 5 ); 475 uint32_t SrcAccess : MOS_BITFIELD_BIT( 6 ); 476 uint32_t RefAccess : MOS_BITFIELD_BIT( 7 ); 477 uint32_t SearchCtrl : MOS_BITFIELD_RANGE( 8,10 ); 478 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT( 11 ); 479 uint32_t SubPelMode : MOS_BITFIELD_RANGE( 12,13 ); 480 uint32_t SkipType : MOS_BITFIELD_BIT( 14 ); 481 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT( 15 ); 482 uint32_t InterChromaMode : MOS_BITFIELD_BIT( 16 ); 483 uint32_t FTEnable : MOS_BITFIELD_BIT( 17 ); 484 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT( 18 ); 485 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT( 19 ); 486 uint32_t InterSAD : MOS_BITFIELD_RANGE( 20,21 ); 487 uint32_t IntraSAD : MOS_BITFIELD_RANGE( 22,23 ); 488 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE( 24,30 ); 489 uint32_t : MOS_BITFIELD_BIT( 31 ); 490 }; 491 struct 492 { 493 uint32_t Value; 494 }; 495 } DW3; 496 497 // DW4 498 union 499 { 500 struct 501 { 502 uint32_t : MOS_BITFIELD_RANGE(0, 7); 503 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 504 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 505 uint32_t : MOS_BITFIELD_RANGE(24, 31); 506 }; 507 struct 508 { 509 uint32_t Value; 510 }; 511 } DW4; 512 513 // DW5 514 union 515 { 516 struct 517 { 518 uint32_t : MOS_BITFIELD_RANGE(0, 7); 519 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 520 uint32_t RefWidth : MOS_BITFIELD_RANGE( 16,23 ); 521 uint32_t RefHeight : MOS_BITFIELD_RANGE( 24,31 ); 522 }; 523 struct 524 { 525 uint32_t Value; 526 }; 527 } DW5; 528 529 // DW6 530 union 531 { 532 struct 533 { 534 uint32_t : MOS_BITFIELD_BIT(0); 535 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 536 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 537 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 538 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 539 uint32_t : MOS_BITFIELD_RANGE(5, 7); 540 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 541 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 542 }; 543 struct 544 { 545 uint32_t Value; 546 }; 547 } DW6; 548 549 // DW7 550 union 551 { 552 struct 553 { 554 uint32_t : MOS_BITFIELD_RANGE(0, 15); 555 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE( 16,17 ); 556 uint32_t BilinearEnable : MOS_BITFIELD_BIT( 18 ); 557 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT( 19 ); 558 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT( 20 ); 559 uint32_t AConlyHAAR : MOS_BITFIELD_BIT( 21 ); 560 uint32_t RefIDCostMode : MOS_BITFIELD_BIT( 22 ); 561 uint32_t : MOS_BITFIELD_BIT( 23 ); 562 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE( 24,31 ); 563 }; 564 struct 565 { 566 uint32_t Value; 567 }; 568 } DW7; 569 570 // DW8 571 union 572 { 573 struct 574 { 575 uint32_t Mode0Cost : MOS_BITFIELD_RANGE( 0, 7 ); 576 uint32_t Mode1Cost : MOS_BITFIELD_RANGE( 8,15 ); 577 uint32_t Mode2Cost : MOS_BITFIELD_RANGE( 16,23 ); 578 uint32_t Mode3Cost : MOS_BITFIELD_RANGE( 24,31 ); 579 }; 580 struct 581 { 582 uint32_t Value; 583 }; 584 } DW8; 585 586 // DW9 587 union 588 { 589 struct 590 { 591 uint32_t Mode4Cost : MOS_BITFIELD_RANGE( 0, 7 ); 592 uint32_t Mode5Cost : MOS_BITFIELD_RANGE( 8,15 ); 593 uint32_t Mode6Cost : MOS_BITFIELD_RANGE( 16,23 ); 594 uint32_t Mode7Cost : MOS_BITFIELD_RANGE( 24,31 ); 595 }; 596 struct 597 { 598 uint32_t Value; 599 }; 600 } DW9; 601 602 // DW10 603 union 604 { 605 struct 606 { 607 uint32_t Mode8Cost : MOS_BITFIELD_RANGE( 0, 7 ); 608 uint32_t Mode9Cost : MOS_BITFIELD_RANGE( 8,15 ); 609 uint32_t RefIDCost : MOS_BITFIELD_RANGE( 16,23 ); 610 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE( 24,31 ); 611 }; 612 struct 613 { 614 uint32_t Value; 615 }; 616 } DW10; 617 618 // DW11 619 union 620 { 621 struct 622 { 623 uint32_t MV0Cost : MOS_BITFIELD_RANGE( 0, 7 ); 624 uint32_t MV1Cost : MOS_BITFIELD_RANGE( 8,15 ); 625 uint32_t MV2Cost : MOS_BITFIELD_RANGE( 16,23 ); 626 uint32_t MV3Cost : MOS_BITFIELD_RANGE( 24,31 ); 627 }; 628 struct 629 { 630 uint32_t Value; 631 }; 632 } DW11; 633 634 // DW12 635 union 636 { 637 struct 638 { 639 uint32_t MV4Cost : MOS_BITFIELD_RANGE( 0, 7 ); 640 uint32_t MV5Cost : MOS_BITFIELD_RANGE( 8,15 ); 641 uint32_t MV6Cost : MOS_BITFIELD_RANGE( 16,23 ); 642 uint32_t MV7Cost : MOS_BITFIELD_RANGE( 24,31 ); 643 }; 644 struct 645 { 646 uint32_t Value; 647 }; 648 } DW12; 649 650 // DW13 651 union 652 { 653 struct 654 { 655 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 656 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 657 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 658 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 659 uint32_t : MOS_BITFIELD_RANGE(27, 31); 660 }; 661 struct 662 { 663 uint32_t Value; 664 }; 665 } DW13; 666 667 // DW14 668 union 669 { 670 struct 671 { 672 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 673 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 674 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 675 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 676 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 677 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 678 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 679 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 680 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 681 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 682 uint32_t : MOS_BITFIELD_RANGE(10, 31); 683 }; 684 struct 685 { 686 uint32_t Value; 687 }; 688 } DW14; 689 690 // DW15 691 union 692 { 693 struct 694 { 695 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 696 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 697 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 698 }; 699 struct 700 { 701 uint32_t Value; 702 }; 703 } DW15; 704 705 struct 706 { 707 // DW16 708 union 709 { 710 struct 711 { 712 SearchPathDelta SPDelta_0; 713 SearchPathDelta SPDelta_1; 714 SearchPathDelta SPDelta_2; 715 SearchPathDelta SPDelta_3; 716 }; 717 struct 718 { 719 uint32_t Value; 720 }; 721 } DW16; 722 723 // DW17 724 union 725 { 726 struct 727 { 728 SearchPathDelta SPDelta_4; 729 SearchPathDelta SPDelta_5; 730 SearchPathDelta SPDelta_6; 731 SearchPathDelta SPDelta_7; 732 }; 733 struct 734 { 735 uint32_t Value; 736 }; 737 } DW17; 738 739 // DW18 740 union 741 { 742 struct 743 { 744 SearchPathDelta SPDelta_8; 745 SearchPathDelta SPDelta_9; 746 SearchPathDelta SPDelta_10; 747 SearchPathDelta SPDelta_11; 748 }; 749 struct 750 { 751 uint32_t Value; 752 }; 753 } DW18; 754 755 // DW19 756 union 757 { 758 struct 759 { 760 SearchPathDelta SPDelta_12; 761 SearchPathDelta SPDelta_13; 762 SearchPathDelta SPDelta_14; 763 SearchPathDelta SPDelta_15; 764 }; 765 struct 766 { 767 uint32_t Value; 768 }; 769 } DW19; 770 771 // DW20 772 union 773 { 774 struct 775 { 776 SearchPathDelta SPDelta_16; 777 SearchPathDelta SPDelta_17; 778 SearchPathDelta SPDelta_18; 779 SearchPathDelta SPDelta_19; 780 }; 781 struct 782 { 783 uint32_t Value; 784 }; 785 } DW20; 786 787 // DW21 788 union 789 { 790 struct 791 { 792 SearchPathDelta SPDelta_20; 793 SearchPathDelta SPDelta_21; 794 SearchPathDelta SPDelta_22; 795 SearchPathDelta SPDelta_23; 796 }; 797 struct 798 { 799 uint32_t Value; 800 }; 801 } DW21; 802 803 // DW22 804 union 805 { 806 struct 807 { 808 SearchPathDelta SPDelta_24; 809 SearchPathDelta SPDelta_25; 810 SearchPathDelta SPDelta_26; 811 SearchPathDelta SPDelta_27; 812 }; 813 struct 814 { 815 uint32_t Value; 816 }; 817 } DW22; 818 819 // DW23 820 union 821 { 822 struct 823 { 824 SearchPathDelta SPDelta_28; 825 SearchPathDelta SPDelta_29; 826 SearchPathDelta SPDelta_30; 827 SearchPathDelta SPDelta_31; 828 }; 829 struct 830 { 831 uint32_t Value; 832 }; 833 } DW23; 834 835 // DW24 836 union 837 { 838 struct 839 { 840 SearchPathDelta SPDelta_32; 841 SearchPathDelta SPDelta_33; 842 SearchPathDelta SPDelta_34; 843 SearchPathDelta SPDelta_35; 844 }; 845 struct 846 { 847 uint32_t Value; 848 }; 849 } DW24; 850 851 // DW25 852 union 853 { 854 struct 855 { 856 SearchPathDelta SPDelta_36; 857 SearchPathDelta SPDelta_37; 858 SearchPathDelta SPDelta_38; 859 SearchPathDelta SPDelta_39; 860 }; 861 struct 862 { 863 uint32_t Value; 864 }; 865 } DW25; 866 867 // DW26 868 union 869 { 870 struct 871 { 872 SearchPathDelta SPDelta_40; 873 SearchPathDelta SPDelta_41; 874 SearchPathDelta SPDelta_42; 875 SearchPathDelta SPDelta_43; 876 }; 877 struct 878 { 879 uint32_t Value; 880 }; 881 } DW26; 882 883 // DW27 884 union 885 { 886 struct 887 { 888 SearchPathDelta SPDelta_44; 889 SearchPathDelta SPDelta_45; 890 SearchPathDelta SPDelta_46; 891 SearchPathDelta SPDelta_47; 892 }; 893 struct 894 { 895 uint32_t Value; 896 }; 897 } DW27; 898 899 // DW28 900 union 901 { 902 struct 903 { 904 SearchPathDelta SPDelta_48; 905 SearchPathDelta SPDelta_49; 906 SearchPathDelta SPDelta_50; 907 SearchPathDelta SPDelta_51; 908 }; 909 struct 910 { 911 uint32_t Value; 912 }; 913 } DW28; 914 915 // DW29 916 union 917 { 918 struct 919 { 920 SearchPathDelta SPDelta_52; 921 SearchPathDelta SPDelta_53; 922 SearchPathDelta SPDelta_54; 923 SearchPathDelta SPDelta_55; 924 }; 925 struct 926 { 927 uint32_t Value; 928 }; 929 } DW29; 930 } SPDelta; 931 932 // DW30 933 union 934 { 935 struct 936 { 937 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 938 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 939 }; 940 struct 941 { 942 uint32_t Value; 943 }; 944 } DW30; 945 946 // DW31 947 union 948 { 949 struct 950 { 951 uint32_t RoiCtrl : MOS_BITFIELD_RANGE( 0, 7 ); 952 uint32_t MaxTuSize : MOS_BITFIELD_RANGE( 8, 9 ); 953 uint32_t MaxCuSize : MOS_BITFIELD_RANGE( 10, 11 ); 954 uint32_t NumImePredictors : MOS_BITFIELD_RANGE( 12, 15 ); 955 uint32_t Reserved : MOS_BITFIELD_RANGE( 16, 23 ); 956 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE( 24, 31 ); 957 }; 958 struct 959 { 960 uint32_t Value; 961 }; 962 } DW31; 963 964 // DW32 965 union 966 { 967 struct 968 { 969 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 970 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 971 }; 972 struct 973 { 974 uint32_t Value; 975 }; 976 } DW32; 977 978 // DW33 979 union 980 { 981 struct 982 { 983 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 984 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 985 }; 986 struct 987 { 988 uint32_t Value; 989 }; 990 } DW33; 991 992 // DW34 993 union 994 { 995 struct 996 { 997 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 998 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 999 }; 1000 struct 1001 { 1002 uint32_t Value; 1003 }; 1004 } DW34; 1005 1006 // DW35 1007 union 1008 { 1009 struct 1010 { 1011 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 1012 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 1013 }; 1014 struct 1015 { 1016 uint32_t Value; 1017 }; 1018 } DW35; 1019 1020 // DW36 1021 union 1022 { 1023 struct 1024 { 1025 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 1026 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 1027 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 1028 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 1029 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 1030 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 1031 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 1032 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 1033 }; 1034 struct 1035 { 1036 uint32_t Value; 1037 }; 1038 } DW36; 1039 1040 // DW37 1041 union 1042 { 1043 struct 1044 { 1045 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 1046 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 1047 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 1048 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 1049 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 1050 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 1051 }; 1052 struct 1053 { 1054 uint32_t Value; 1055 }; 1056 } DW37; 1057 1058 // DW38 1059 union 1060 { 1061 struct 1062 { 1063 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 1064 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 1065 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 1066 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 1067 }; 1068 struct 1069 { 1070 uint32_t Value; 1071 }; 1072 } DW38; 1073 1074 // DW39 1075 union 1076 { 1077 struct 1078 { 1079 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 1080 }; 1081 struct 1082 { 1083 uint32_t Value; 1084 }; 1085 } DW39; 1086 1087 // DW40 1088 union 1089 { 1090 struct 1091 { 1092 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1093 }; 1094 struct 1095 { 1096 uint32_t Value; 1097 }; 1098 } DW40; 1099 1100 // DW41 1101 union 1102 { 1103 struct 1104 { 1105 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1106 }; 1107 struct 1108 { 1109 uint32_t Value; 1110 }; 1111 } DW41; 1112 1113 // DW42 1114 union 1115 { 1116 struct 1117 { 1118 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1119 }; 1120 struct 1121 { 1122 uint32_t Value; 1123 }; 1124 } DW42; 1125 1126 // DW43 1127 union 1128 { 1129 struct 1130 { 1131 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1132 }; 1133 struct 1134 { 1135 uint32_t Value; 1136 }; 1137 } DW43; 1138 1139 // DW44 1140 union 1141 { 1142 struct 1143 { 1144 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1145 }; 1146 struct 1147 { 1148 uint32_t Value; 1149 }; 1150 } DW44; 1151 1152 // DW45 1153 union 1154 { 1155 struct 1156 { 1157 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1158 }; 1159 struct 1160 { 1161 uint32_t Value; 1162 }; 1163 } DW45; 1164 1165 // DW46 1166 union 1167 { 1168 struct 1169 { 1170 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1171 }; 1172 struct 1173 { 1174 uint32_t Value; 1175 }; 1176 } DW46; 1177 1178 // DW47 1179 union 1180 { 1181 struct 1182 { 1183 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1184 }; 1185 struct 1186 { 1187 uint32_t Value; 1188 }; 1189 } DW47; 1190 }; 1191 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_VDENC_HEVC_ME_CURBE_G11)) == 48); 1192 1193 using PCODECHAL_VDENC_HEVC_ME_CURBE_G11 = CODECHAL_VDENC_HEVC_ME_CURBE_G11*; 1194 1195 struct MEDIA_OBJECT_HEVC_VP9_VDENC_ME_CURBE_G11 1196 { 1197 // DW0 1198 union 1199 { 1200 struct 1201 { 1202 uint32_t SkipModeEn : MOS_BITFIELD_BIT(0); 1203 uint32_t AdaptiveEn : MOS_BITFIELD_BIT(1); 1204 uint32_t BiMixDis : MOS_BITFIELD_BIT(2); 1205 uint32_t: MOS_BITFIELD_RANGE(3, 4); 1206 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT(5); 1207 uint32_t: MOS_BITFIELD_BIT(6); 1208 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT(7); 1209 uint32_t: MOS_BITFIELD_RANGE(8, 23); 1210 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 1211 }; 1212 struct 1213 { 1214 uint32_t Value; 1215 }; 1216 } DW0; 1217 1218 // DW1 1219 union 1220 { 1221 struct 1222 { 1223 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE(0, 5); 1224 uint32_t: MOS_BITFIELD_RANGE(6, 15); 1225 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 1226 uint32_t: MOS_BITFIELD_RANGE(22, 27); 1227 uint32_t UniMixDisable : MOS_BITFIELD_BIT(28); 1228 uint32_t: MOS_BITFIELD_RANGE(29, 31); 1229 }; 1230 struct 1231 { 1232 uint32_t Value; 1233 }; 1234 } DW1; 1235 1236 // DW2 1237 union 1238 { 1239 struct 1240 { 1241 uint32_t MaxLenSP : MOS_BITFIELD_RANGE(0, 7); 1242 uint32_t MaxNumSU : MOS_BITFIELD_RANGE(8, 15); 1243 uint32_t: MOS_BITFIELD_RANGE(16, 31); 1244 }; 1245 struct 1246 { 1247 uint32_t Value; 1248 }; 1249 } DW2; 1250 1251 // DW3 1252 union 1253 { 1254 struct 1255 { 1256 uint32_t SrcSize : MOS_BITFIELD_RANGE(0, 1); 1257 uint32_t: MOS_BITFIELD_RANGE(2, 3); 1258 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE(4, 5); 1259 uint32_t SrcAccess : MOS_BITFIELD_BIT(6); 1260 uint32_t RefAccess : MOS_BITFIELD_BIT(7); 1261 uint32_t SearchCtrl : MOS_BITFIELD_RANGE(8, 10); 1262 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT(11); 1263 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 1264 uint32_t SkipType : MOS_BITFIELD_BIT(14); 1265 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT(15); 1266 uint32_t InterChromaMode : MOS_BITFIELD_BIT(16); 1267 uint32_t FTEnable : MOS_BITFIELD_BIT(17); 1268 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT(18); 1269 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT(19); 1270 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 1271 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 1272 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 1273 uint32_t: MOS_BITFIELD_BIT(31); 1274 }; 1275 struct 1276 { 1277 uint32_t Value; 1278 }; 1279 } DW3; 1280 1281 // DW4 1282 union 1283 { 1284 struct 1285 { 1286 uint32_t: MOS_BITFIELD_RANGE(0, 7); 1287 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 1288 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 1289 uint32_t: MOS_BITFIELD_RANGE(24, 31); 1290 }; 1291 struct 1292 { 1293 uint32_t Value; 1294 }; 1295 } DW4; 1296 1297 // DW5 1298 union 1299 { 1300 struct 1301 { 1302 uint32_t: MOS_BITFIELD_RANGE(0, 7); 1303 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 1304 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 1305 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 1306 }; 1307 struct 1308 { 1309 uint32_t Value; 1310 }; 1311 } DW5; 1312 1313 // DW6 1314 union 1315 { 1316 struct 1317 { 1318 uint32_t: MOS_BITFIELD_BIT(0); 1319 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 1320 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 1321 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 1322 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 1323 uint32_t: MOS_BITFIELD_RANGE(5, 7); 1324 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 1325 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 1326 }; 1327 struct 1328 { 1329 uint32_t Value; 1330 }; 1331 } DW6; 1332 1333 // DW7 1334 union 1335 { 1336 struct 1337 { 1338 uint32_t: MOS_BITFIELD_RANGE(0, 15); 1339 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 1340 uint32_t BilinearEnable : MOS_BITFIELD_BIT(18); 1341 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT(19); 1342 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT(20); 1343 uint32_t AConlyHAAR : MOS_BITFIELD_BIT(21); 1344 uint32_t RefIDCostMode : MOS_BITFIELD_BIT(22); 1345 uint32_t: MOS_BITFIELD_BIT(23); 1346 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 1347 }; 1348 struct 1349 { 1350 uint32_t Value; 1351 }; 1352 } DW7; 1353 1354 // DW8 1355 union 1356 { 1357 struct 1358 { 1359 uint32_t Mode0Cost : MOS_BITFIELD_RANGE(0, 7); 1360 uint32_t Mode1Cost : MOS_BITFIELD_RANGE(8, 15); 1361 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 1362 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 1363 }; 1364 struct 1365 { 1366 uint32_t Value; 1367 }; 1368 } DW8; 1369 1370 // DW9 1371 union 1372 { 1373 struct 1374 { 1375 uint32_t Mode4Cost : MOS_BITFIELD_RANGE(0, 7); 1376 uint32_t Mode5Cost : MOS_BITFIELD_RANGE(8, 15); 1377 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 1378 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 1379 }; 1380 struct 1381 { 1382 uint32_t Value; 1383 }; 1384 } DW9; 1385 1386 // DW10 1387 union 1388 { 1389 struct 1390 { 1391 uint32_t Mode8Cost : MOS_BITFIELD_RANGE(0, 7); 1392 uint32_t Mode9Cost : MOS_BITFIELD_RANGE(8, 15); 1393 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 1394 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 1395 }; 1396 struct 1397 { 1398 uint32_t Value; 1399 }; 1400 } DW10; 1401 1402 // DW11 1403 union 1404 { 1405 struct 1406 { 1407 uint32_t MV0Cost : MOS_BITFIELD_RANGE(0, 7); 1408 uint32_t MV1Cost : MOS_BITFIELD_RANGE(8, 15); 1409 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 1410 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 1411 }; 1412 struct 1413 { 1414 uint32_t Value; 1415 }; 1416 } DW11; 1417 1418 // DW12 1419 union 1420 { 1421 struct 1422 { 1423 uint32_t MV4Cost : MOS_BITFIELD_RANGE(0, 7); 1424 uint32_t MV5Cost : MOS_BITFIELD_RANGE(8, 15); 1425 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 1426 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 1427 }; 1428 struct 1429 { 1430 uint32_t Value; 1431 }; 1432 } DW12; 1433 1434 // DW13 1435 union 1436 { 1437 struct 1438 { 1439 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 1440 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 1441 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 1442 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 1443 uint32_t: MOS_BITFIELD_RANGE(27, 31); 1444 }; 1445 struct 1446 { 1447 uint32_t Value; 1448 }; 1449 } DW13; 1450 1451 // DW14 1452 union 1453 { 1454 struct 1455 { 1456 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 1457 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 1458 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 1459 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 1460 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 1461 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 1462 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 1463 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 1464 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 1465 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 1466 uint32_t: MOS_BITFIELD_RANGE(10, 31); 1467 }; 1468 struct 1469 { 1470 uint32_t Value; 1471 }; 1472 } DW14; 1473 1474 // DW15 1475 union 1476 { 1477 struct 1478 { 1479 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 1480 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 1481 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 1482 }; 1483 struct 1484 { 1485 uint32_t Value; 1486 }; 1487 } DW15; 1488 1489 struct 1490 { 1491 // DW16 1492 union 1493 { 1494 struct 1495 { 1496 SearchPathDelta SPDelta_0; 1497 SearchPathDelta SPDelta_1; 1498 SearchPathDelta SPDelta_2; 1499 SearchPathDelta SPDelta_3; 1500 }; 1501 struct 1502 { 1503 uint32_t Value; 1504 }; 1505 } DW16; 1506 1507 // DW17 1508 union 1509 { 1510 struct 1511 { 1512 SearchPathDelta SPDelta_4; 1513 SearchPathDelta SPDelta_5; 1514 SearchPathDelta SPDelta_6; 1515 SearchPathDelta SPDelta_7; 1516 }; 1517 struct 1518 { 1519 uint32_t Value; 1520 }; 1521 } DW17; 1522 1523 // DW18 1524 union 1525 { 1526 struct 1527 { 1528 SearchPathDelta SPDelta_8; 1529 SearchPathDelta SPDelta_9; 1530 SearchPathDelta SPDelta_10; 1531 SearchPathDelta SPDelta_11; 1532 }; 1533 struct 1534 { 1535 uint32_t Value; 1536 }; 1537 } DW18; 1538 1539 // DW19 1540 union 1541 { 1542 struct 1543 { 1544 SearchPathDelta SPDelta_12; 1545 SearchPathDelta SPDelta_13; 1546 SearchPathDelta SPDelta_14; 1547 SearchPathDelta SPDelta_15; 1548 }; 1549 struct 1550 { 1551 uint32_t Value; 1552 }; 1553 } DW19; 1554 1555 // DW20 1556 union 1557 { 1558 struct 1559 { 1560 SearchPathDelta SPDelta_16; 1561 SearchPathDelta SPDelta_17; 1562 SearchPathDelta SPDelta_18; 1563 SearchPathDelta SPDelta_19; 1564 }; 1565 struct 1566 { 1567 uint32_t Value; 1568 }; 1569 } DW20; 1570 1571 // DW21 1572 union 1573 { 1574 struct 1575 { 1576 SearchPathDelta SPDelta_20; 1577 SearchPathDelta SPDelta_21; 1578 SearchPathDelta SPDelta_22; 1579 SearchPathDelta SPDelta_23; 1580 }; 1581 struct 1582 { 1583 uint32_t Value; 1584 }; 1585 } DW21; 1586 1587 // DW22 1588 union 1589 { 1590 struct 1591 { 1592 SearchPathDelta SPDelta_24; 1593 SearchPathDelta SPDelta_25; 1594 SearchPathDelta SPDelta_26; 1595 SearchPathDelta SPDelta_27; 1596 }; 1597 struct 1598 { 1599 uint32_t Value; 1600 }; 1601 } DW22; 1602 1603 // DW23 1604 union 1605 { 1606 struct 1607 { 1608 SearchPathDelta SPDelta_28; 1609 SearchPathDelta SPDelta_29; 1610 SearchPathDelta SPDelta_30; 1611 SearchPathDelta SPDelta_31; 1612 }; 1613 struct 1614 { 1615 uint32_t Value; 1616 }; 1617 } DW23; 1618 1619 // DW24 1620 union 1621 { 1622 struct 1623 { 1624 SearchPathDelta SPDelta_32; 1625 SearchPathDelta SPDelta_33; 1626 SearchPathDelta SPDelta_34; 1627 SearchPathDelta SPDelta_35; 1628 }; 1629 struct 1630 { 1631 uint32_t Value; 1632 }; 1633 } DW24; 1634 1635 // DW25 1636 union 1637 { 1638 struct 1639 { 1640 SearchPathDelta SPDelta_36; 1641 SearchPathDelta SPDelta_37; 1642 SearchPathDelta SPDelta_38; 1643 SearchPathDelta SPDelta_39; 1644 }; 1645 struct 1646 { 1647 uint32_t Value; 1648 }; 1649 } DW25; 1650 1651 // DW26 1652 union 1653 { 1654 struct 1655 { 1656 SearchPathDelta SPDelta_40; 1657 SearchPathDelta SPDelta_41; 1658 SearchPathDelta SPDelta_42; 1659 SearchPathDelta SPDelta_43; 1660 }; 1661 struct 1662 { 1663 uint32_t Value; 1664 }; 1665 } DW26; 1666 1667 // DW27 1668 union 1669 { 1670 struct 1671 { 1672 SearchPathDelta SPDelta_44; 1673 SearchPathDelta SPDelta_45; 1674 SearchPathDelta SPDelta_46; 1675 SearchPathDelta SPDelta_47; 1676 }; 1677 struct 1678 { 1679 uint32_t Value; 1680 }; 1681 } DW27; 1682 1683 // DW28 1684 union 1685 { 1686 struct 1687 { 1688 SearchPathDelta SPDelta_48; 1689 SearchPathDelta SPDelta_49; 1690 SearchPathDelta SPDelta_50; 1691 SearchPathDelta SPDelta_51; 1692 }; 1693 struct 1694 { 1695 uint32_t Value; 1696 }; 1697 } DW28; 1698 1699 // DW29 1700 union 1701 { 1702 struct 1703 { 1704 SearchPathDelta SPDelta_52; 1705 SearchPathDelta SPDelta_53; 1706 SearchPathDelta SPDelta_54; 1707 SearchPathDelta SPDelta_55; 1708 }; 1709 struct 1710 { 1711 uint32_t Value; 1712 }; 1713 } DW29; 1714 } SPDelta; 1715 1716 // DW30 1717 union 1718 { 1719 struct 1720 { 1721 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 1722 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 1723 }; 1724 struct 1725 { 1726 uint32_t Value; 1727 }; 1728 } DW30; 1729 1730 // DW31 1731 union 1732 { 1733 struct 1734 { 1735 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 1736 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 1737 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 1738 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 1739 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 23); 1740 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 1741 }; 1742 struct 1743 { 1744 uint32_t Value; 1745 }; 1746 } DW31; 1747 1748 // DW32 1749 union 1750 { 1751 struct 1752 { 1753 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 1754 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 1755 }; 1756 struct 1757 { 1758 uint32_t Value; 1759 }; 1760 } DW32; 1761 1762 // DW33 1763 union 1764 { 1765 struct 1766 { 1767 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 1768 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 1769 }; 1770 struct 1771 { 1772 uint32_t Value; 1773 }; 1774 } DW33; 1775 1776 // DW34 1777 union 1778 { 1779 struct 1780 { 1781 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 1782 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 1783 }; 1784 struct 1785 { 1786 uint32_t Value; 1787 }; 1788 } DW34; 1789 1790 // DW35 1791 union 1792 { 1793 struct 1794 { 1795 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 1796 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 1797 }; 1798 struct 1799 { 1800 uint32_t Value; 1801 }; 1802 } DW35; 1803 1804 // DW36 1805 union 1806 { 1807 struct 1808 { 1809 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 1810 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 1811 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 1812 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 1813 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 1814 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 1815 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 1816 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 1817 }; 1818 struct 1819 { 1820 uint32_t Value; 1821 }; 1822 } DW36; 1823 1824 // DW37 1825 union 1826 { 1827 struct 1828 { 1829 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 1830 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 1831 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 1832 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 1833 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 1834 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 1835 }; 1836 struct 1837 { 1838 uint32_t Value; 1839 }; 1840 } DW37; 1841 1842 // DW38 1843 union 1844 { 1845 struct 1846 { 1847 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 1848 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 1849 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 1850 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 1851 }; 1852 struct 1853 { 1854 uint32_t Value; 1855 }; 1856 } DW38; 1857 1858 // DW39 1859 union 1860 { 1861 struct 1862 { 1863 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31); 1864 }; 1865 struct 1866 { 1867 uint32_t Value; 1868 }; 1869 } DW39; 1870 1871 // DW40 1872 union 1873 { 1874 struct 1875 { 1876 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1877 }; 1878 struct 1879 { 1880 uint32_t Value; 1881 }; 1882 } DW40; 1883 1884 // DW41 1885 union 1886 { 1887 struct 1888 { 1889 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1890 }; 1891 struct 1892 { 1893 uint32_t Value; 1894 }; 1895 } DW41; 1896 1897 // DW42 1898 union 1899 { 1900 struct 1901 { 1902 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1903 }; 1904 struct 1905 { 1906 uint32_t Value; 1907 }; 1908 } DW42; 1909 1910 // DW43 1911 union 1912 { 1913 struct 1914 { 1915 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1916 }; 1917 struct 1918 { 1919 uint32_t Value; 1920 }; 1921 } DW43; 1922 1923 // DW44 1924 union 1925 { 1926 struct 1927 { 1928 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1929 }; 1930 struct 1931 { 1932 uint32_t Value; 1933 }; 1934 } DW44; 1935 1936 // DW45 1937 union 1938 { 1939 struct 1940 { 1941 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1942 }; 1943 struct 1944 { 1945 uint32_t Value; 1946 }; 1947 } DW45; 1948 1949 // DW46 1950 union 1951 { 1952 struct 1953 { 1954 uint32_t VDEncStreamInOutputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1955 }; 1956 struct 1957 { 1958 uint32_t Value; 1959 }; 1960 } DW46; 1961 1962 // DW47 1963 union 1964 { 1965 struct 1966 { 1967 uint32_t VDEncStreamInInputSurfIndex : MOS_BITFIELD_RANGE(0, 31); 1968 }; 1969 struct 1970 { 1971 uint32_t Value; 1972 }; 1973 } DW47; 1974 }; 1975 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(MEDIA_OBJECT_HEVC_VP9_VDENC_ME_CURBE_G11)) == 48); 1976 1977 enum CODECHAL_BINDING_TABLE_OFFSET_HEVC_VP9_VDENC_KERNEL_G11 1978 { 1979 // VDEnc HME kernel 1980 CODECHAL_VDENC_HME_BEGIN_G11 = 0, 1981 CODECHAL_VDENC_HME_MV_DATA_SURFACE_CM_G11 = CODECHAL_VDENC_HME_BEGIN_G11, 1982 CODECHAL_VDENC_16xME_MV_DATA_SURFACE_CM_G11, 1983 CODECHAL_VDENC_32xME_MV_DATA_SURFACE_CM_G11 = CODECHAL_VDENC_16xME_MV_DATA_SURFACE_CM_G11, 1984 CODECHAL_VDENC_HME_DISTORTION_SURFACE_CM_G11, 1985 CODECHAL_VDENC_HME_BRC_DISTORTION_CM_G11, 1986 CODECHAL_VDENC_HME_CURR_FOR_FWD_REF_CM_G11, 1987 CODECHAL_VDENC_HME_FWD_REF_IDX0_CM_G11, 1988 CODECHAL_VDENC_HME_RESERVED1_CM_G11, 1989 CODECHAL_VDENC_HME_FWD_REF_IDX1_CM_G11, 1990 CODECHAL_VDENC_HME_RESERVED2_CM_G11, 1991 CODECHAL_VDENC_HME_FWD_REF_IDX2_CM_G11, 1992 CODECHAL_VDENC_HME_RESERVED3_CM_G11, 1993 CODECHAL_VDENC_HME_FWD_REF_IDX3_CM_G11, 1994 CODECHAL_VDENC_HME_RESERVED4_CM_G11, 1995 CODECHAL_VDENC_HME_FWD_REF_IDX4_CM_G11, 1996 CODECHAL_VDENC_HME_RESERVED5_CM_G11, 1997 CODECHAL_VDENC_HME_FWD_REF_IDX5_CM_G11, 1998 CODECHAL_VDENC_HME_RESERVED6_CM_G11, 1999 CODECHAL_VDENC_HME_FWD_REF_IDX6_CM_G11, 2000 CODECHAL_VDENC_HME_RESERVED7_CM_G11, 2001 CODECHAL_VDENC_HME_FWD_REF_IDX7_CM_G11, 2002 CODECHAL_VDENC_HME_RESERVED8_CM_G11, 2003 CODECHAL_VDENC_HME_CURR_FOR_BWD_REF_CM_G11, 2004 CODECHAL_VDENC_HME_BWD_REF_IDX0_CM_G11, 2005 CODECHAL_VDENC_HME_RESERVED9_CM_G11, 2006 CODECHAL_VDENC_HME_BWD_REF_IDX1_CM_G11, 2007 CODECHAL_VDENC_HME_RESERVED10_CM_G11, 2008 CODECHAL_VDENC_HME_VDENC_STREAMIN_OUTPUT_CM_G11, 2009 CODECHAL_VDENC_HME_VDENC_STREAMIN_INPUT_CM_G11, 2010 CODECHAL_VDENC_HME_END_G11, 2011 }; 2012 2013 const uint32_t ME_CURBE_INIT[48] = 2014 { 2015 0x00000000, 0x00200010, 0x00003939, 0x77a43000, 0x00000000, 0x28300000, 0x00000000, 0x00000000, 2016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 2017 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2018 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2019 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2020 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff 2021 }; 2022 //! HEVC VDEnc encoder class for GEN11 2023 /*! 2024 This class defines the member fields, functions for GEN11 platform 2025 */ 2026 class CodechalVdencHevcStateG11 : public CodechalVdencHevcState 2027 { 2028 public: 2029 static const uint32_t m_minScaledSurfaceSize = 64; //!< Minimum scaled surface size 2030 static const uint32_t m_brcPakStatsBufSize = 512; //!< Pak statistic buffer size 2031 static const uint32_t m_brcStatsBufSize = 1216; //!< BRC Statistic buf size: 48DWs (3CLs) of HMDC Frame Stats + 256 DWs (16CLs) of Histogram Stats = 1216 bytes 2032 static const uint32_t m_brcConstantSurfaceWidth = 64; //!< BRC constant surface width 2033 static const uint32_t m_brcConstantSurfaceHeight = 35; //!< BRC constant surface height 2034 static const uint32_t m_brcHistoryBufferSize = 832; //!< BRC history buffer size 2035 static const uint32_t m_bframeMeBidirectionalWeight = 32; //!< B frame bidirection weight 2036 static const uint32_t m_insertOffsetAfterCMD1 = 120; //!< Huc Initializer CMD1 delta 2037 static const uint32_t m_insertOffsetAfterCMD2 = 148; //!< Huc Initializer CMD2 delta 2038 2039 // HuC tables, refer to HEVC HuC. 2040 // These Values are diff for each Gen 2041 static const int8_t m_devThreshPB0[8]; 2042 static const int8_t m_lowDelayDevThreshPB0[8]; 2043 static const int8_t m_devThreshVBR0[8]; 2044 static const int8_t m_lowDelayDevThreshVBR0[8]; 2045 static const int8_t m_devThreshI0[8]; 2046 static const int8_t m_lowDelayDevThreshI0[8]; 2047 static const uint32_t m_hucConstantData[]; 2048 2049 static constexpr uint32_t m_numDevThreshlds = 8; 2050 static constexpr double m_devStdFPS = 30.0; 2051 static constexpr double m_bpsRatioLow = 0.1; 2052 static constexpr double m_bpsRatioHigh = 3.5; 2053 static constexpr int32_t m_postMultPB = 50; 2054 static constexpr int32_t m_negMultPB = -50; 2055 static constexpr int32_t m_posMultVBR = 100; 2056 static constexpr int32_t m_negMultVBR = -50; 2057 2058 static const double m_devThreshIFPNEG[m_numDevThreshlds / 2]; 2059 static const double m_devThreshIFPPOS[m_numDevThreshlds / 2]; 2060 static const double m_devThreshPBFPNEG[m_numDevThreshlds / 2]; 2061 static const double m_devThreshPBFPPOS[m_numDevThreshlds / 2]; 2062 static const double m_devThreshVBRNEG[m_numDevThreshlds / 2]; 2063 static const double m_devThreshVBRPOS[m_numDevThreshlds / 2]; 2064 static const int8_t m_lowdelayDevThreshPB[m_numDevThreshlds]; 2065 static const int8_t m_lowdelayDevThreshVBR[m_numDevThreshlds]; 2066 static const int8_t m_lowdelayDevThreshI[m_numDevThreshlds]; 2067 static const int8_t m_lowdelayDeltaFrmszI[][8]; 2068 static const int8_t m_lowdelayDeltaFrmszP[][8]; 2069 static const int8_t m_lowdelayDeltaFrmszB[][8]; 2070 2071 struct CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE 2072 { 2073 union { 2074 uint8_t VdBox[MOS_MAX_ENGINE_INSTANCE_PER_CLASS]; 2075 uint64_t Value; 2076 }; 2077 }; 2078 2079 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 m_tileParams = nullptr; //!< Pointer to the Tile params 2080 2081 bool m_enableTileStitchByHW = false; //!< Enable HW to stitch commands in scalable mode 2082 bool m_enableHWSemaphore = false; //!< Enable HW semaphore 2083 bool m_enableVdBoxHWSemaphore = false; //!< Enable VDBOX HW semaphore 2084 // scalability 2085 unsigned char m_numPipe = 1; //!< Number of pipes 2086 unsigned char m_numPipePre = 1; //!< Number of pipes of previous frame 2087 unsigned char m_numPassesInOnePipe = 1; //!< Number of PAK passes in one pipe 2088 CODECHAL_ENCODE_BUFFER m_resPakSliceLevelStreamoutData; //!< Surface for slice level stream out data from PAK 2089 CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE m_kmdVeOveride = {}; //!< KMD override virtual engine index 2090 uint32_t m_numTiles = 1; //!< Number of tiles 2091 uint32_t m_numLcu = 1; //!< LCU number 2092 CODECHAL_ENCODE_BUFFER m_resHcpScalabilitySyncBuffer = {};//!< Hcp sync buffer for scalability 2093 CODECHAL_ENCODE_BUFFER m_resTileBasedStatisticsBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 2094 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 2095 CODECHAL_ENCODE_BUFFER m_resHuCPakAggregatedFrameStatsBuffer = {}; 2096 HEVC_TILE_STATS_INFO m_hevcTileStatsOffset = {}; //!< Page aligned offsets used to program HCP / VDEnc pipe and HuC PAK Integration kernel input 2097 HEVC_TILE_STATS_INFO m_hevcFrameStatsOffset = {}; //!< Page aligned offsets used to program HuC PAK Integration kernel output, HuC BRC kernel input 2098 HEVC_TILE_STATS_INFO m_hevcStatsSize = {}; //!< HEVC Statistics size 2099 bool m_enableTestMediaReset = 0; //!< enable media reset test. driver will send cmd to make hang happens 2100 2101 // HuC PAK stitch kernel 2102 bool m_hucPakStitchEnabled = false; //!< HuC PAK stitch enabled flag 2103 MOS_RESOURCE m_resHucPakStitchDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_VDENC_BRC_NUM_OF_PASSES] = {}; //!< HuC Pak Integration Dmem data for each pass 2104 MOS_RESOURCE m_resBrcDataBuffer = {}; //!< Resource of bitrate control data buffer 2105 2106 // virtual engine 2107 bool m_useVirtualEngine = false; //!< Virtual engine enable flag 2108 MOS_COMMAND_BUFFER m_veBatchBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC][CODECHAL_HEVC_MAX_NUM_HCP_PIPE][CODECHAL_HEVC_MAX_NUM_BRC_PASSES] = {}; //!< Virtual engine batch buffers 2109 MOS_COMMAND_BUFFER m_realCmdBuffer = {}; //!< Virtual engine command buffer 2110 uint32_t m_sizeOfVeBatchBuffer = 0; //!< Virtual engine batch buffer size 2111 CODECHAL_ENCODE_BUFFER m_resBrcSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE] = {}; //!< BRC HW semaphore 2112 CODECHAL_ENCODE_BUFFER m_resVdBoxSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE] = {}; //!< VDBox HW semaphore 2113 CODECHAL_ENCODE_BUFFER m_resBrcPakSemaphoreMem = {}; //!< BRC PAK HW semaphore 2114 MOS_RESOURCE m_resPipeStartSemaMem = {}; //!< HW semaphore for scalability pipe start at the same time 2115 MOS_RESOURCE m_resSyncSemaMem = {}; //!< HW semaphore for sync 2116 2117 //! 2118 //! \brief Constructor 2119 //! 2120 CodechalVdencHevcStateG11(CodechalHwInterface* hwInterface, 2121 CodechalDebugInterface* debugInterface, 2122 PCODECHAL_STANDARD_INFO standardInfo); 2123 2124 //! 2125 //! \brief Destructor 2126 //! 2127 ~CodechalVdencHevcStateG11(); 2128 //! 2129 //! \brief Help function to get current pipe 2130 //! 2131 //! \return Current pipe value 2132 //! GetCurrentPipe()2133 int GetCurrentPipe() 2134 { 2135 if (m_numPipe <= 1) 2136 { 2137 return 0; 2138 } 2139 2140 return (int)(m_currPass) % (int)m_numPipe; 2141 } 2142 2143 //! 2144 //! \brief Help function to get current PAK pass 2145 //! 2146 //! \return Current PAK pass 2147 //! GetCurrentPass()2148 int GetCurrentPass() 2149 { 2150 if (m_numPipe <= 1) 2151 { 2152 return m_currPass; 2153 } 2154 2155 return (int)(m_currPass) / (int)m_numPipe; 2156 } 2157 2158 //! 2159 //! \brief Help function to check if current pipe is first pipe 2160 //! 2161 //! \return True if current pipe is first pipe, otherwise return false 2162 //! IsFirstPipe()2163 bool IsFirstPipe() 2164 { 2165 return GetCurrentPipe() == 0 ? true : false; 2166 } 2167 2168 //! 2169 //! \brief Help function to check if current pipe is last pipe 2170 //! 2171 //! \return True if current pipe is last pipe, otherwise return false 2172 //! IsLastPipe()2173 bool IsLastPipe() 2174 { 2175 return GetCurrentPipe() == m_numPipe - 1 ? true : false; 2176 } 2177 2178 //! 2179 //! \brief Help function to check if current PAK pass is first pass 2180 //! 2181 //! \return True if current PAK pass is first pass, otherwise return false 2182 //! IsFirstPass()2183 bool IsFirstPass() 2184 { 2185 return GetCurrentPass() == 0 ? true : false; 2186 } 2187 2188 //! 2189 //! \brief Help function to check if current PAK pass is last pass 2190 //! 2191 //! \return True if current PAK pass is last pass, otherwise return false 2192 //! IsLastPass()2193 bool IsLastPass() 2194 { 2195 return GetCurrentPass() == m_numPassesInOnePipe ? true : false; 2196 } 2197 2198 //! 2199 //! \brief Help function to check if legacy command buffer is used 2200 //! 2201 //! \return True if using legacy command buffer, otherwise return false 2202 //! UseLegacyCommandBuffer()2203 bool UseLegacyCommandBuffer() 2204 { 2205 return (m_numPipe == 1) || 2206 (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext); 2207 } 2208 2209 // inherited virtual functions 2210 uint32_t GetMaxBtCount(); 2211 bool CheckSupportedFormat(PMOS_SURFACE surface); 2212 void SetHcpSliceStateCommonParams(MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams); 2213 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams); 2214 MOS_STATUS Initialize(CodechalSetting * settings); 2215 MOS_STATUS InitKernelState(); 2216 MOS_STATUS PlatformCapabilityCheck(); 2217 MOS_STATUS AllocatePakResources(); 2218 MOS_STATUS FreePakResources(); 2219 MOS_STATUS AllocateEncResources(); 2220 MOS_STATUS FreeEncResources(); 2221 MOS_STATUS AllocateBrcResources(); 2222 MOS_STATUS FreeBrcResources(); 2223 MOS_STATUS InitializePicture(const EncoderParams& params); 2224 MOS_STATUS SetPictureStructs(); 2225 MOS_STATUS GetStatusReport(EncodeStatus* encodeStatus, EncodeStatusReport* encodeStatusReport); 2226 MOS_STATUS UserFeatureKeyReport(); 2227 MOS_STATUS EncodeKernelFunctions(); 2228 MOS_STATUS ExecutePictureLevel(); 2229 MOS_STATUS ExecuteSliceLevel(); 2230 MOS_STATUS ConstructBatchBufferHuCCQP(PMOS_RESOURCE batchBuffer); 2231 MOS_STATUS ConstructBatchBufferHuCBRC(PMOS_RESOURCE batchBuffer); 2232 MOS_STATUS ConstructBatchBufferHuCBRCForGroup3(PMOS_RESOURCE batchBuffer); 2233 MOS_STATUS ConstructHucCmdForBRC(PMOS_RESOURCE batchBuffer); 2234 MOS_STATUS SetDmemHuCBrcInitReset(); 2235 MOS_STATUS SetConstDataHuCBrcUpdate(); 2236 MOS_STATUS SetDmemHuCBrcUpdate(); 2237 MOS_STATUS SetRegionsHuCBrcUpdate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 2238 MOS_STATUS SetDmemHuCPakIntegrate(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 2239 MOS_STATUS SetRegionsHuCPakIntegrate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 2240 MOS_STATUS PrepareVDEncStreamInData(); 2241 MOS_STATUS SetGpuCtxCreatOption(); 2242 MOS_STATUS ReadSliceSize(PMOS_COMMAND_BUFFER cmdBuffer); 2243 void GetTileInfo(uint32_t xPosition, uint32_t yPosition, uint32_t* tileId, uint32_t* tileEndLCUX, uint32_t* tileEndLCUY); 2244 void SetStreaminDataPerRegion( 2245 uint32_t streamInWidth, 2246 uint32_t top, 2247 uint32_t bottom, 2248 uint32_t left, 2249 uint32_t right, 2250 PMHW_VDBOX_VDENC_STREAMIN_STATE_PARAMS streaminParams, 2251 void* streaminData); 2252 void SetBrcRoiDeltaQpMap( 2253 uint32_t streamInWidth, 2254 uint32_t top, 2255 uint32_t bottom, 2256 uint32_t left, 2257 uint32_t right, 2258 uint8_t regionId, 2259 PDeltaQpForROI deltaQpMap); 2260 void CreateMhwParams(); 2261 void SetStreaminDataPerLcu( 2262 PMHW_VDBOX_VDENC_STREAMIN_STATE_PARAMS streaminParams, 2263 void* streaminData); 2264 2265 MOS_STATUS VerifyCommandBufferSize(); 2266 2267 MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 2268 2269 MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 2270 2271 MOS_STATUS SubmitCommandBuffer( 2272 PMOS_COMMAND_BUFFER cmdBuffer, 2273 bool bNullRendering); 2274 2275 MOS_STATUS SendPrologWithFrameTracking( 2276 PMOS_COMMAND_BUFFER cmdBuffer, 2277 bool frameTrackingRequested, 2278 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr); 2279 2280 MOS_STATUS SetSliceStructs(); 2281 2282 MOS_STATUS AllocateTileStatistics(); 2283 2284 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams); 2285 2286 void SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams); 2287 2288 MOS_STATUS ReadSseStatistics(PMOS_COMMAND_BUFFER cmdBuffer); 2289 2290 MOS_STATUS HuCBrcInitReset(); 2291 2292 MOS_STATUS HuCLookaheadInit(); 2293 2294 MOS_STATUS HuCLookaheadUpdate(); 2295 2296 void SetVdencPipeBufAddrParams( 2297 MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams); 2298 2299 //! 2300 //! \brief Encode at tile level 2301 //! 2302 //! \return MOS_STATUS 2303 //! MOS_STATUS_SUCCESS if success, else fail reason 2304 //! 2305 MOS_STATUS EncTileLevel(); 2306 2307 //! 2308 //! \brief Decide number of pipes used for encoding 2309 //! \details called inside PlatformCapabilityCheck 2310 //! 2311 //! \return MOS_STATUS 2312 //! MOS_STATUS_SUCCESS if success, else fail reason 2313 //! 2314 MOS_STATUS DecideEncodingPipeNumber(); 2315 2316 // overload with more input params 2317 void SetHcpSliceStateParams( 2318 MHW_VDBOX_HEVC_SLICE_STATE& sliceState, 2319 PCODEC_ENCODER_SLCDATA slcData, 2320 uint16_t slcCount, 2321 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 tileCodingParams, 2322 bool lastSliceInTile, 2323 uint32_t idx); 2324 2325 //! 2326 //! \brief Get encoder kernel header and kernel size 2327 //! 2328 //! \param [in] binary 2329 //! Pointer to kernel binary 2330 //! \param [in] operation 2331 //! Enc kernel operation 2332 //! \param [in] krnStateIdx 2333 //! Kernel state index 2334 //! \param [out] krnHeader 2335 //! Pointer to kernel header 2336 //! \param [out] krnSize 2337 //! Pointer to kernel size 2338 //! 2339 //! \return MOS_STATUS 2340 //! MOS_STATUS_SUCCESS if success, else fail reason 2341 //! 2342 static MOS_STATUS GetKernelHeaderAndSize( 2343 void *binary, 2344 EncOperation operation, 2345 uint32_t krnStateIdx, 2346 void *krnHeader, 2347 uint32_t *krnSize); 2348 2349 //! 2350 //! \brief Init kernel state for HME kernel 2351 //! 2352 //! \return MOS_STATUS 2353 //! MOS_STATUS_SUCCESS if success, else fail reason 2354 //! 2355 MOS_STATUS InitKernelStateMe(); 2356 2357 //! 2358 //! \brief Init kernel state for streamin kernel 2359 //! 2360 //! \return MOS_STATUS 2361 //! MOS_STATUS_SUCCESS if success, else fail reason 2362 //! 2363 MOS_STATUS InitKernelStateStreamIn(); 2364 2365 //! 2366 //! \brief Set kernel parameters for specific kernel operation 2367 //! 2368 //! \param [in] operation 2369 //! Kernel operation 2370 //! \param [out] kernelParams 2371 //! Pointer to kernel parameters 2372 //! 2373 //! \return MOS_STATUS 2374 //! MOS_STATUS_SUCCESS if success, else fail reason 2375 //! 2376 MOS_STATUS SetKernelParams( 2377 EncOperation operation, 2378 MHW_KERNEL_PARAM* kernelParams); 2379 2380 //! 2381 //! \brief Set binding table for specific kernel operation 2382 //! 2383 //! \param [in] operation 2384 //! Kernel operation 2385 //! \param [out] bindingTable 2386 //! Pointer to binding table 2387 //! 2388 //! \return MOS_STATUS 2389 //! MOS_STATUS_SUCCESS if success, else fail reason 2390 //! 2391 MOS_STATUS SetBindingTable( 2392 EncOperation operation, 2393 PCODECHAL_ENCODE_BINDING_TABLE_GENERIC bindingTable); 2394 2395 //! 2396 //! \brief Invoke HME kernel 2397 //! 2398 //! \param [in] hmeLevel 2399 //! HME level like 4x, 16x 32x 2400 //! 2401 //! \return MOS_STATUS 2402 //! MOS_STATUS_SUCCESS if success, else fail reason 2403 //! 2404 MOS_STATUS EncodeMeKernel( 2405 HmeLevel hmeLevel); 2406 2407 //! 2408 //! \brief Set curbe for HME kernel 2409 //! 2410 //! \param [in] hmeLevel 2411 //! HME level like 4x, 16x 32x 2412 //! 2413 //! \return MOS_STATUS 2414 //! MOS_STATUS_SUCCESS if success, else fail reason 2415 //! 2416 MOS_STATUS SetMeCurbe( 2417 HmeLevel hmeLevel); 2418 2419 //! 2420 //! \brief Set surface state for HME kernel 2421 //! 2422 //! \param [in] hmeLevel 2423 //! HME level like 4x, 16x 32x 2424 //! \param [in] cmdBuffer 2425 //! Pointer to command buffer that surface states are added 2426 //! 2427 //! \return MOS_STATUS 2428 //! MOS_STATUS_SUCCESS if success, else fail reason 2429 //! 2430 MOS_STATUS SendMeSurfaces( 2431 HmeLevel hmeLevel, 2432 PMOS_COMMAND_BUFFER cmdBuffer); 2433 2434 //! 2435 //! \brief Dump HuC based debug output buffers 2436 //! 2437 //! \return MOS_STATUS 2438 //! MOS_STATUS_SUCCESS if success, else fail reason 2439 //! 2440 MOS_STATUS DumpHucDebugOutputBuffers(); 2441 2442 MOS_STATUS AddVdencWalkerStateCmd( 2443 PMOS_COMMAND_BUFFER cmdBuffer, 2444 PMHW_VDBOX_HEVC_SLICE_STATE params); 2445 2446 MOS_STATUS CalculatePictureStateCommandSize(); 2447 2448 protected: 2449 2450 //! 2451 //! \brief Set pipe buffer address parameter 2452 //! \details Set pipe buffer address parameter in MMC case 2453 //! 2454 //! \param [in] cmdBuffer 2455 //! Pointer to MOS command buffer 2456 //! 2457 //! \return MOS_STATUS 2458 //! MOS_STATUS_SUCCESS if success, else fail reason 2459 //! 2460 virtual MOS_STATUS SetPipeBufAddr( 2461 PMOS_COMMAND_BUFFER cmdBuffer); 2462 2463 //! 2464 //! \brief Is slice in the current tile 2465 //! 2466 //! \param [in] sliceNumber 2467 //! Slice number 2468 //! \param [in] currentTile 2469 //! Pointer to current tile coding params 2470 //! \param [out] sliceInTile 2471 //! Pointer to return if slice in tile 2472 //! \param [out] lastSliceInTile 2473 //! Pointer to return if last slice in tile 2474 //! 2475 //! \return MOS_STATUS 2476 //! MOS_STATUS_SUCCESS if success, else fail reason 2477 //! 2478 MOS_STATUS IsSliceInTile( 2479 uint32_t sliceNumber, 2480 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 currentTile, 2481 bool *sliceInTile, 2482 bool *lastSliceInTile); 2483 2484 //! 2485 //! \brief Invoke HuC BRC update 2486 //! 2487 //! \return MOS_STATUS 2488 //! MOS_STATUS_SUCCESS if success, else fail reason 2489 //! 2490 MOS_STATUS HuCBrcUpdate(); 2491 2492 //! 2493 //! \brief Set tile data 2494 //! 2495 //! \param [in] tileCodingParams 2496 //! Pointer to tile coding params 2497 //! \return MOS_STATUS 2498 //! MOS_STATUS_SUCCESS if success, else fail reason 2499 //! 2500 MOS_STATUS SetTileData(MHW_VDBOX_HCP_TILE_CODING_PARAMS_G11* tileCodingParams); 2501 2502 //! 2503 //! \brief Check whether Scalability is enabled or not, 2504 //! Set number of VDBoxes accordingly 2505 //! 2506 //! \return MOS_STATUS 2507 //! MOS_STATUS_SUCCESS if success, else fail reason 2508 //! 2509 MOS_STATUS GetSystemPipeNumberCommon(); 2510 2511 //! 2512 //! \brief HuC PAK integrate 2513 //! 2514 //! \param [in] cmdBuffer 2515 //! Pointer to command buffer 2516 //! 2517 //! \return MOS_STATUS 2518 //! MOS_STATUS_SUCCESS if success, else fail reason 2519 //! 2520 MOS_STATUS HucPakIntegrate( 2521 PMOS_COMMAND_BUFFER cmdBuffer); 2522 2523 MOS_STATUS UpdateCmdBufAttribute( 2524 PMOS_COMMAND_BUFFER cmdBuffer, 2525 bool renderEngineInUse); 2526 2527 //! 2528 //! \brief Set And Populate VE Hint parameters 2529 //! \details Set Virtual Engine hint parameter and populate it to primary cmd buffer attributes 2530 //! \param [in] cmdBuffer 2531 //! Pointer to primary cmd buffer 2532 //! \return MOS_STATUS 2533 //! MOS_STATUS_SUCCESS if success, else fail reason 2534 //! 2535 MOS_STATUS SetAndPopulateVEHintParams( 2536 PMOS_COMMAND_BUFFER cmdBuffer); 2537 2538 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState; //!< Scalability state 2539 2540 //! 2541 //! \brief Lookahead analysis 2542 //! 2543 //! \return MOS_STATUS 2544 //! MOS_STATUS_SUCCESS if success, else fail reason 2545 //! 2546 virtual MOS_STATUS AnalyzeLookaheadStats(); 2547 2548 #if USE_CODECHAL_DEBUG_TOOL 2549 virtual MOS_STATUS DumpHucPakIntegrate(); 2550 virtual MOS_STATUS DumpVdencOutputs(); 2551 virtual MOS_STATUS DumpHucCqp(); 2552 #endif 2553 2554 }; 2555 2556 //! \brief typedef of class CodechalVdencHevcStateG11* 2557 using PCODECHAL_VDENC_HEVC__STATE_G11 = class CodechalVdencHevcStateG11*; 2558 2559 #endif // __CODECHAL_VDENC_HEVC__G11_H__ 2560