1 /*
2 * Copyright (c) 2017-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_vdenc_avc_g9_kbl.cpp
24 //! \brief This file implements the C++ class/interface for KBL 's AVC
25 //! VDEnc encoding to be used CODECHAL components.
26 //!
27
28 #include "codechal_vdenc_avc_g9_kbl.h"
29 #if USE_CODECHAL_DEBUG_TOOL
30 #include "mhw_vdbox_mfx_hwcmd_g9_kbl.h"
31 #include "mhw_vdbox_vdenc_hwcmd_g9_kbl.h"
32 #endif
33
34 typedef struct _CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL {
35 int nKernelCount;
36
37 // Quality mode for Frame/Field
38 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_I;
39 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_P;
40 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_B;
41 // Normal mode for Frame/Field
42 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_I;
43 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_P;
44 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_B;
45 // Performance modes for Frame/Field
46 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_I;
47 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_P;
48 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_B;
49 // Modes for Frame/Field
50 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_I;
51 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_P;
52 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_B;
53
54 // HME
55 CODECHAL_KERNEL_HEADER AVC_ME_P;
56 CODECHAL_KERNEL_HEADER AVC_ME_B;
57
58 // DownScaling
59 CODECHAL_KERNEL_HEADER PLY_DScale_PLY;
60 CODECHAL_KERNEL_HEADER PLY_DScale_2f_PLY_2f;
61
62 // BRC init frame
63 CODECHAL_KERNEL_HEADER InitFrameBRC;
64
65 // Frame BRC update
66 CODECHAL_KERNEL_HEADER FrameENCUpdate;
67
68 // BRC Reset frame
69 CODECHAL_KERNEL_HEADER BRC_ResetFrame;
70
71 // BRC I Frame Distortion
72 CODECHAL_KERNEL_HEADER BRC_IFrame_Dist;
73
74 // BRCBlockCopy
75 CODECHAL_KERNEL_HEADER BRCBlockCopy;
76
77 // MbBRC Update
78 CODECHAL_KERNEL_HEADER MbBRCUpdate;
79
80 // 2x DownScaling
81 CODECHAL_KERNEL_HEADER PLY_2xDScale_PLY;
82 CODECHAL_KERNEL_HEADER PLY_2xDScale_2f_PLY_2f;
83
84 //Motion estimation kernel for the VDENC StreamIN
85 CODECHAL_KERNEL_HEADER AVC_ME_VDENC;
86
87 //Weighted Prediction Kernel
88 CODECHAL_KERNEL_HEADER AVC_WeightedPrediction;
89
90 // Static frame detection Kernel
91 CODECHAL_KERNEL_HEADER AVC_StaticFrameDetection;
92
93 } CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL, *PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL;
94
95 typedef struct _CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL
96 {
97 uint8_t BRCFunc_U8; // 0: Init; 2: Reset
98 uint8_t OpenSourceEnable_U8; // 0: disable opensource, 1: enable opensource
99 uint8_t RVSD[2];
100 uint16_t INIT_BRCFlag_U16; // ICQ or CQP with slice size control: 0x00 CBR: 0x10; VBR: 0x20; VCM: 0x40; LOWDELAY: 0x80.
101 uint16_t Reserved;
102 uint16_t INIT_FrameWidth_U16; // Luma width in bytes
103 uint16_t INIT_FrameHeight_U16; // Luma height in bytes
104 uint32_t INIT_TargetBitrate_U32; // target bitrate, set by application
105 uint32_t INIT_MinRate_U32; // 0
106 uint32_t INIT_MaxRate_U32; // Maximum bit rate in bits per second (bps).
107 uint32_t INIT_BufSize_U32; // buffer size
108 uint32_t INIT_InitBufFull_U32; // initial buffer fullness
109 uint32_t INIT_ProfileLevelMaxFrame_U32; // user defined. refer to AVC BRC for conformance check and correction
110 uint32_t INIT_FrameRateM_U32; // FrameRateM is the number of frames in FrameRateD
111 uint32_t INIT_FrameRateD_U32; // If driver gets this FrameRateD from VUI, it is the num_units_in_tick field (32 bits unsigned integer).
112 uint16_t INIT_GopP_U16; // number of P frames in a GOP
113 uint16_t INIT_GopB_U16; // number of B frames in a GOP
114 uint16_t INIT_MinQP_U16; // 10
115 uint16_t INIT_MaxQP_U16; // 51
116 int8_t INIT_DevThreshPB0_S8[8]; // lowdelay ? (-45, -33, -23, -15, -8, 0, 15, 25) : (-46, -38, -30, -23, 23, 30, 40, 46)
117 int8_t INIT_DevThreshVBR0_S8[8]; // lowdelay ? (-45, -35, -25, -15, -8, 0, 20, 40) : (-46, -40, -32, -23, 56, 64, 83, 93)
118 int8_t INIT_DevThreshI0_S8[8]; // lowdelay ? (-40, -30, -17, -10, -5, 0, 10, 20) : (-43, -36, -25, -18, 18, 28, 38, 46)
119 uint8_t INIT_InitQPIP; // Initial QP for I and P
120
121 uint8_t INIT_NotUseRhoDm_U8; // Reserved
122 uint8_t INIT_InitQPB; // Initial QP for B
123 uint8_t INIT_MbQpCtrl_U8; // Enable MB level QP control (global)
124 uint8_t INIT_SliceSizeCtrlEn_U8; // Enable slice size control
125 int8_t INIT_IntraQPDelta_I8[3]; // set to zero for all by default
126 int8_t INIT_SkipQPDelta_I8; // Reserved
127 int8_t INIT_DistQPDelta_I8[4]; // lowdelay ? (-5, -2, 2, 5) : (0, 0, 0, 0)
128 uint8_t INIT_OscillationQpDelta_U8; // BRCFLAG_ISVCM ? 16 : 0
129 uint8_t INIT_HRDConformanceCheckDisable_U8; // BRCFLAG_ISAVBR ? 1 : 0
130 uint8_t INIT_SkipFrameEnableFlag;
131 uint8_t INIT_TopQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
132 uint8_t INIT_TopFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 50. Top frame size threshold for second pass
133 uint8_t INIT_BotFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 200. Bottom frame size threshold for second pass
134 uint8_t INIT_QPSelectForFirstPass_U8; // lowdelay ? 0 : 1. =0 to use previous frame final QP; or =1 to use (targetQP + previousQP) / 2.
135 uint8_t INIT_MBHeaderCompensation_U8; // Reserved
136 uint8_t INIT_OverShootCarryFlag_U8; // set to zero by default
137 uint8_t INIT_OverShootSkipFramePct_U8; // set to zero by default
138 uint8_t INIT_EstRateThreshP0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
139 uint8_t INIT_EstRateThreshB0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
140 uint8_t INIT_EstRateThreshI0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
141 uint8_t INIT_FracQPEnable_U8; // ExtendedRhoDomainEn from par file
142 uint8_t INIT_ScenarioInfo_U8; // 0: UNKNOWN, 1: DISPLAYREMOTING, 2: VIDEOCONFERENCE, 3: ARCHIVE, 4: LIVESTREAMING.
143 uint8_t INIT_StaticRegionStreamIn_U8; // should be programmed from par file
144 uint8_t INIT_DeltaQP_Adaptation_U8; // =1, should be programmed from par file
145 uint8_t INIT_MaxCRFQualityFactor_U8; // =52, should be programmed from par file
146 uint8_t INIT_CRFQualityFactor_U8; // =25, should be programmed from par file
147 uint8_t INIT_BotQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
148 uint8_t INIT_SlidingWindowSize_U8; // =30, the window size (in frames) used to compute bit rate
149 uint8_t INIT_SlidingWidowRCEnable_U8; // =0, sliding window based rate control (SWRC) disabled, 1: enabled
150 uint8_t INIT_SlidingWindowMaxRateRatio_U8; // =120, ratio between the max rate within the window and average target bitrate
151 uint8_t INIT_LowDelayGoldenFrameBoost_U8; // only for lowdelay mode, 0 (default): no boost for I and scene change frames, 1: boost
152 uint8_t INIT_AdaptiveCostEnable_U8; // 0: disabled, 1: enabled
153 uint8_t INIT_AdaptiveHMEExtensionEnable_U8; // 0: disabled, 1: enabled
154 uint8_t INIT_ICQReEncode_U8; // 0: disabled, 1: enabled
155 uint8_t INIT_SliceSizeCtrlWA; // 0: disabled, 1: enabled
156 uint8_t INIT_SinglePassOnly; // 0: disabled, 1: enabled
157 uint8_t RSVD2[56]; // must be zero
158 } CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL, *PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL;
159
160 typedef struct __CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL
161 {
162 uint8_t BRCFunc_U8; // =1 for Update, other values are reserved for future use
163 uint8_t RSVD[3];
164 uint32_t UPD_TARGETSIZE_U32; // refer to AVC BRC for calculation
165 uint32_t UPD_FRAMENUM_U32; // frame number
166 uint32_t UPD_PeakTxBitsPerFrame_U32; // current global target bits - previous global target bits (global target bits += input bits per frame)
167 uint32_t UPD_FrameBudget_U32; // target time counter
168 uint32_t FrameByteCount; // PAK output via MMIO
169 uint32_t TimingBudgetOverflow; // PAK output via MMIO
170 uint32_t ImgStatusCtrl; // PAK output via MMIO
171 uint32_t IPCMNonConformant; // PAK output via MMIO
172
173 uint16_t UPD_startGAdjFrame_U16[4]; // 10, 50, 100, 150
174 uint16_t UPD_MBBudget_U16[52]; // MB bugdet for QP 0 � 51.
175 uint16_t UPD_SLCSZ_TARGETSLCSZ_U16; // target slice size
176 uint16_t UPD_SLCSZ_UPD_THRDELTAI_U16[42]; // slice size threshold delta for I frame
177 uint16_t UPD_SLCSZ_UPD_THRDELTAP_U16[42]; // slice size threshold delta for P frame
178 uint16_t UPD_NumOfFramesSkipped_U16; // Recording how many frames have been skipped.
179 uint16_t UPD_SkipFrameSize_U16; // Recording the skip frame size for one frame. =NumMBs * 1, assuming one bit per mb for skip frame.
180 uint16_t UPD_StaticRegionPct_U16; // One entry, recording the percentage of static region
181 uint8_t UPD_gRateRatioThreshold_U8[7]; // 80,95,99,101,105,125,160
182 uint8_t UPD_CurrFrameType_U8; // I frame: 2; P frame: 0; B frame: 1.
183 uint8_t UPD_startGAdjMult_U8[5]; // 1, 1, 3, 2, 1
184 uint8_t UPD_startGAdjDiv_U8[5]; // 40, 5, 5, 3, 1
185 uint8_t UPD_gRateRatioThresholdQP_U8[8]; // 253,254,255,0,1,1,2,3
186 uint8_t UPD_PAKPassNum_U8; // current pak pass number
187 uint8_t UPD_MaxNumPass_U8; // 2
188 uint8_t UPD_SceneChgWidth_U8[2]; // set both to MIN((NumP + 1) / 5, 6)
189 uint8_t UPD_SceneChgDetectEn_U8; // Enable scene change detection
190 uint8_t UPD_SceneChgPrevIntraPctThreshold_U8; // =96. scene change previous intra percentage threshold
191 uint8_t UPD_SceneChgCurIntraPctThreshold_U8; // =192. scene change current intra percentage threshold
192 uint8_t UPD_IPAverageCoeff_U8; // lowdelay ? 0 : 128
193 uint8_t UPD_MinQpAdjustment_U8; // Minimum QP increase step
194 uint8_t UPD_TimingBudgetCheck_U8; // Flag indicating if kernel will check timing budget.
195 int8_t reserved_I8[4]; // must be zero
196 uint8_t UPD_CQP_QpValue_U8; // Application specified target QP in BRC_ICQ mode
197 uint8_t UPD_CQP_FracQp_U8; // Application specified fine position in BRC_ICQ mode
198 uint8_t UPD_HMEDetectionEnable_U8; // 0: default, 1: HuC BRC kernel requires information from HME detection kernel output
199 uint8_t UPD_HMECostEnable_U8; // 0: default, 1: driver provides HME cost table
200 uint8_t UPD_DisablePFrame8x8Transform_U8; // 0: enable, 1: disable
201 uint8_t UPD_SklCabacWAEnable_U8; // 0: disable, 1: enable
202 uint8_t UPD_ROISource_U8; // =0: disable, 1: ROIMap from HME Static Region or from App dirty rectangle, 2: ROIMap from App
203 uint8_t UPD_SLCSZ_ConsertativeThreshold_U8; // =0, 0: do not set conservative threshold (suggested for video conference) 1: set conservative threshold for non-video conference
204 uint16_t UPD_TargetSliceSize_U16; // default: 1498, max target slice size from app DDI
205 uint16_t UPD_MaxNumSliceAllowed_U16; // computed by driver based on level idc
206 uint16_t UPD_SLBB_Size_U16; // second level batch buffer (SLBB) size in bytes, the input buffer will contain two SLBBs A and B, A followed by B, A and B have the same structure.
207 uint16_t UPD_SLBB_B_Offset_U16; // offset in bytes from the beginning of the input buffer, it points to the start of SLBB B, set by driver for skip frame support
208 uint16_t UPD_AvcImgStateOffset_U16; // offset in bytes from the beginning of SLBB A
209 uint16_t reserved_u16;
210 uint32_t NumOfSlice; // PAK output via MMIO
211
212 /* HME distortion based QP adjustment */
213 uint16_t AveHmeDist_U16; // default: 0, in HME detection kernel output
214 uint8_t HmeDistAvailable_U8; // 0: disabled, 1: enabled
215 uint8_t reserved_u8; // must be zero
216 uint16_t AdditionalFrameSize_U16; // for slice size control improvement
217 uint8_t AddNALHeaderSizeInternally_U8;
218 uint8_t UPD_RoiQpViaForceQp_U8; // HuC does not update StreamIn Buffer, 1: HuC updates StreamIn Buffer
219 uint32_t CABACZeroInsertionSize_U32; // PAK output via MMIO
220 uint32_t MiniFramePaddingSize_U32; // PAK output via MMIO
221 uint16_t UPD_WidthInMB_U16; // width in MB
222 uint16_t UPD_HeightInMB_U16; // height in MB
223 int8_t UPD_ROIQpDelta_I8[8]; // Application specified ROI QP Adjustment for Zone0, Zone1, Zone2 and Zone3, Zone4, Zone5, Zone6 and Zone7.
224 uint32_t UPD_TR_TargetSize_U32; // target frame size in TCBRC mode. If zero, TCBRC is disabled.
225 uint8_t RSVD2[28];
226 } _CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL, *P_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL;
227
228 const uint32_t CodechalVdencAvcStateG9Kbl::MV_Cost_SkipBias_QPel[3][8] =
229 {
230 // for normal case
231 { 0, 6, 6, 9, 10, 13, 14, 16 },
232 // for QP = 47,48,49
233 { 0, 6, 6, 6, 6, 7, 8, 8 },
234 // for QP = 50,51
235 { 0, 6, 6, 6, 6, 7, 7, 7 }
236 };
237
238 const uint32_t CodechalVdencAvcStateG9Kbl::HmeCost_DisplayRemote[8][CODEC_AVC_NUM_QP] =
239 {
240 //mv=0
241 {
242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
246 },
247 //mv<=16
248 {
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
253 },
254 //mv<=32
255 {
256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[0 ~12]
257 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[13 ~25]
258 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[26 ~38]
259 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 //QP=[39 ~51]
260 },
261 //mv<=64
262 {
263 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
264 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[13 ~25]
265 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[26 ~38]
266 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 //QP=[39 ~51]
267 },
268 //mv<=128
269 {
270 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
271 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
272 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
273 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
274 },
275 //mv<=256
276 {
277 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
278 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
279 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
280 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
281 },
282 //mv<=512
283 {
284 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
285 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
286 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
287 20, 20, 20, 20, 20, 30, 30, 30, 30, 30, 30, 30, 30 //QP=[39 ~51]
288 },
289 //mv<=1024
290 {
291 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
292 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
293 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
294 20, 20, 20, 30, 40, 50, 50, 50, 50, 50, 50, 50, 50 //QP=[39 ~51]
295 }
296 };
297
298 const uint32_t CodechalVdencAvcStateG9Kbl::HmeCost[8][CODEC_AVC_NUM_QP] =
299 {
300 //mv=0
301 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
302 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
303 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
304 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
305 },
306 //mv<=16
307 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
308 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
310 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
311 },
312 //mv<=32
313 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[0 ~12]
314 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[13 ~25]
315 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[26 ~38]
316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 //QP=[39 ~51]
317 },
318 //mv<=64
319 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
320 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[13 ~25]
321 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[26 ~38]
322 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 //QP=[39 ~51]
323 },
324 //mv<=128
325 { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
326 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
327 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
328 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
329 },
330 //mv<=256
331 { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
332 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
333 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
334 10, 10, 10, 10, 20, 30, 40, 50, 50, 50, 50, 50, 50 //QP=[39 ~51]
335 },
336 //mv<=512
337 { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
338 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
339 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
340 20, 20, 20, 40, 60, 80, 100, 100, 100, 100, 100, 100, 100 //QP=[39 ~51]
341 },
342 //mv<=1024
343 { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
344 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
345 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
346 20, 20, 30, 50, 100, 200, 200, 200, 200, 200, 200, 200, 200 //QP=[39 ~51]
347 }
348 };
349
350 const int8_t CodechalVdencAvcStateG9Kbl::BRC_INIT_DistQPDelta_I8[4] =
351 {
352 0, 0, 0, 0
353 };
354
355 const int8_t CodechalVdencAvcStateG9Kbl::BRC_INIT_DistQPDelta_I8_LowDelay[4] =
356 {
357 -5, -2, 2, 5
358 };
359
CodechalVdencAvcStateG9Kbl(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)360 CodechalVdencAvcStateG9Kbl::CodechalVdencAvcStateG9Kbl(
361 CodechalHwInterface * hwInterface,
362 CodechalDebugInterface *debugInterface,
363 PCODECHAL_STANDARD_INFO standardInfo) : CodechalVdencAvcStateG9(hwInterface, debugInterface, standardInfo)
364 {
365 CODECHAL_ENCODE_FUNCTION_ENTER;
366
367 this->pfnGetKernelHeaderAndSize = EncodeGetKernelHeaderAndSize;
368
369 m_vdencBrcInitDmemBufferSize = sizeof(CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL);
370 m_vdencBrcUpdateDmemBufferSize = sizeof(_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL);
371 m_vdencBrcNumOfSliceOffset = CODECHAL_OFFSETOF(_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL, NumOfSlice);
372 }
373
~CodechalVdencAvcStateG9Kbl()374 CodechalVdencAvcStateG9Kbl::~CodechalVdencAvcStateG9Kbl()
375 {
376 }
377
InitializeState()378 MOS_STATUS CodechalVdencAvcStateG9Kbl::InitializeState()
379 {
380 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
381
382 CODECHAL_ENCODE_FUNCTION_ENTER;
383
384 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::InitializeState());
385
386 m_sliceSizeStreamoutSupported = true;
387
388 return eStatus;
389 }
390
EncodeGetKernelHeaderAndSize(void * binary,EncOperation operation,uint32_t krnStateIdx,void * krnHeader,uint32_t * krnSize)391 MOS_STATUS CodechalVdencAvcStateG9Kbl::EncodeGetKernelHeaderAndSize(void *binary, EncOperation operation, uint32_t krnStateIdx, void *krnHeader, uint32_t *krnSize)
392 {
393 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
394
395 CODECHAL_ENCODE_FUNCTION_ENTER;
396
397 CODECHAL_ENCODE_CHK_NULL_RETURN(binary);
398 CODECHAL_ENCODE_CHK_NULL_RETURN(krnHeader);
399 CODECHAL_ENCODE_CHK_NULL_RETURN(krnSize);
400
401 auto kernelHeaderTable = (PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL)binary;
402 PCODECHAL_KERNEL_HEADER invalidEntry = &(kernelHeaderTable->AVC_StaticFrameDetection) + 1;
403 PCODECHAL_KERNEL_HEADER nextKrnHeader = nullptr;
404 PCODECHAL_KERNEL_HEADER currKrnHeader = nullptr;
405 if (operation == ENC_SCALING4X)
406 {
407 currKrnHeader = &kernelHeaderTable->PLY_DScale_PLY;
408 }
409 else if (operation == ENC_SCALING2X)
410 {
411 currKrnHeader = &kernelHeaderTable->PLY_2xDScale_PLY;
412 }
413 else if (operation == ENC_ME)
414 {
415 currKrnHeader = &kernelHeaderTable->AVC_ME_P;
416 }
417 else if (operation == VDENC_ME)
418 {
419 currKrnHeader = &kernelHeaderTable->AVC_ME_VDENC;
420 }
421 else if (operation == ENC_SFD)
422 {
423 currKrnHeader = &kernelHeaderTable->AVC_StaticFrameDetection;
424 }
425 else
426 {
427 CODECHAL_ENCODE_ASSERTMESSAGE("Unsupported ENC mode requested");
428 eStatus = MOS_STATUS_INVALID_PARAMETER;
429 return eStatus;
430 }
431
432 currKrnHeader += krnStateIdx;
433 *((PCODECHAL_KERNEL_HEADER)krnHeader) = *currKrnHeader;
434
435 nextKrnHeader = (currKrnHeader + 1);
436 uint32_t nextKrnOffset = *krnSize;
437 if (nextKrnHeader < invalidEntry)
438 {
439 nextKrnOffset = nextKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT;
440 }
441 *krnSize = nextKrnOffset - (currKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
442
443 return eStatus;
444 }
445
CheckSupportedFormat(PMOS_SURFACE surface)446 bool CodechalVdencAvcStateG9Kbl::CheckSupportedFormat(PMOS_SURFACE surface)
447 {
448 CODECHAL_ENCODE_FUNCTION_ENTER;
449
450 bool isColorFormatSupported = true;
451 if (IS_Y_MAJOR_TILE_FORMAT(surface->TileType))
452 {
453 switch (surface->Format)
454 {
455 case Format_NV12:
456 break;
457 default:
458 isColorFormatSupported = false;
459 break;
460 }
461 }
462 else if (surface->TileType == MOS_TILE_LINEAR)
463 {
464 switch (surface->Format)
465 {
466 case Format_NV12:
467 case Format_YUY2:
468 case Format_YUYV:
469 case Format_YVYU:
470 case Format_UYVY:
471 case Format_VYUY:
472 case Format_AYUV:
473 break;
474 default:
475 isColorFormatSupported = false;
476 break;
477 }
478 }
479 else
480 {
481 isColorFormatSupported = false;
482 }
483
484 return isColorFormatSupported;
485 }
486
GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params,PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)487 MOS_STATUS CodechalVdencAvcStateG9Kbl::GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params, PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)
488 {
489 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
490
491 CODECHAL_ENCODE_FUNCTION_ENTER;
492
493 CODECHAL_ENCODE_CHK_NULL(params);
494 CODECHAL_ENCODE_CHK_NULL(trellisQuantParams);
495
496 trellisQuantParams->dwTqEnabled = TrellisQuantizationEnable[params->ucTargetUsage];
497 trellisQuantParams->dwTqRounding =
498 trellisQuantParams->dwTqEnabled ? TrellisQuantizationRounding[params->ucTargetUsage] : 0;
499
500 finish:
501 return eStatus;
502 }
503
SetDmemHuCBrcInitReset()504 MOS_STATUS CodechalVdencAvcStateG9Kbl::SetDmemHuCBrcInitReset()
505 {
506 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
507
508 CODECHAL_ENCODE_FUNCTION_ENTER;
509
510 // Setup BRC DMEM
511 MOS_LOCK_PARAMS lockFlagsWriteOnly;
512 MOS_ZeroMemory(&lockFlagsWriteOnly, sizeof(MOS_LOCK_PARAMS));
513 lockFlagsWriteOnly.WriteOnly = 1;
514 auto pHucVDEncBrcInitDmem = (PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL)m_osInterface->pfnLockResource(
515 m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx], &lockFlagsWriteOnly);
516
517 CODECHAL_ENCODE_CHK_NULL_RETURN(pHucVDEncBrcInitDmem);
518 MOS_ZeroMemory(pHucVDEncBrcInitDmem, sizeof(CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL));
519
520 SetDmemHuCBrcInitResetImpl<CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL>(pHucVDEncBrcInitDmem);
521
522 // fractional QP enable for extended rho domain
523 pHucVDEncBrcInitDmem->INIT_FracQPEnable_U8 = (uint8_t)m_vdencInterface->IsRhoDomainStatsEnabled();
524 pHucVDEncBrcInitDmem->INIT_SliceSizeCtrlWA = 1;
525
526 pHucVDEncBrcInitDmem->INIT_SinglePassOnly = m_vdencSinglePassEnable ? true : false;
527
528 if (((m_avcSeqParam->TargetUsage & 0x07) == TARGETUSAGE_BEST_SPEED) &&
529 (m_avcSeqParam->FrameWidth >= SINGLE_PASS_MIN_FRAME_WIDTH) &&
530 (m_avcSeqParam->FrameHeight >= SINGLE_PASS_MIN_FRAME_HEIGHT) &&
531 (m_avcSeqParam->FramesPer100Sec >= SINGLE_PASS_MIN_FRAME_PER100S))
532 {
533 pHucVDEncBrcInitDmem->INIT_SinglePassOnly = true;
534 }
535
536 //Override the DistQPDelta setting.
537 if (m_mbBrcEnabled)
538 {
539 if (m_avcSeqParam->FrameSizeTolerance == EFRAMESIZETOL_EXTREMELY_LOW)
540 {
541 MOS_SecureMemcpy(pHucVDEncBrcInitDmem->INIT_DistQPDelta_I8, 4 * sizeof(int8_t), (void*)BRC_INIT_DistQPDelta_I8_LowDelay, 4 * sizeof(int8_t));
542 }
543 else
544 {
545 MOS_SecureMemcpy(pHucVDEncBrcInitDmem->INIT_DistQPDelta_I8, 4 * sizeof(int8_t), (void*)BRC_INIT_DistQPDelta_I8, 4 * sizeof(int8_t));
546 }
547 }
548
549 CODECHAL_DEBUG_TOOL(
550 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcInitParam(
551 pHucVDEncBrcInitDmem));
552 )
553
554 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx]);
555
556 return eStatus;
557 }
558
SetDmemHuCBrcUpdate()559 MOS_STATUS CodechalVdencAvcStateG9Kbl::SetDmemHuCBrcUpdate()
560 {
561 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
562
563 CODECHAL_ENCODE_FUNCTION_ENTER;
564
565 // Program update DMEM
566 MOS_LOCK_PARAMS lockFlags;
567 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
568 lockFlags.WriteOnly = 1;
569 auto pHucVDEncBrcDmem = (P_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL)m_osInterface->pfnLockResource(
570 m_osInterface, &m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass], &lockFlags);
571 CODECHAL_ENCODE_CHK_NULL_RETURN(pHucVDEncBrcDmem);
572 SetDmemHuCBrcUpdateImpl<_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL>(pHucVDEncBrcDmem);
573
574 if (m_avcSeqParam->EnableSliceLevelRateCtrl)
575 {
576 pHucVDEncBrcDmem->UPD_SLCSZ_ConsertativeThreshold_U8 = (uint8_t)(m_avcSeqParam->RateControlMethod != RATECONTROL_VCM);
577 }
578 else
579 {
580 pHucVDEncBrcDmem->UPD_SLCSZ_ConsertativeThreshold_U8 = 0;
581 }
582
583 if (m_16xMeSupported && (m_pictureCodingType == P_TYPE))
584 {
585 pHucVDEncBrcDmem->HmeDistAvailable_U8 = 1;
586 }
587 pHucVDEncBrcDmem->UPD_WidthInMB_U16 = m_picWidthInMb;
588 pHucVDEncBrcDmem->UPD_HeightInMB_U16 = m_picHeightInMb;
589
590 pHucVDEncBrcDmem->UPD_TR_TargetSize_U32 = m_avcPicParam->TargetFrameSize * 8; // convert bytes to bits
591
592 CODECHAL_DEBUG_TOOL(
593 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcUpdateParam(
594 pHucVDEncBrcDmem));
595 )
596
597 m_osInterface->pfnUnlockResource(m_osInterface, &(m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass]));
598
599 return eStatus;
600 }
601
LoadMvCost(uint8_t qp)602 MOS_STATUS CodechalVdencAvcStateG9Kbl::LoadMvCost(uint8_t qp)
603 {
604 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
605
606 CODECHAL_ENCODE_FUNCTION_ENTER;
607
608 m_vdEncMvCost[0] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][0]), 0x6f);
609 m_vdEncMvCost[1] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][1]), 0x6f);
610 m_vdEncMvCost[2] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][2]), 0x6f);
611 m_vdEncMvCost[3] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][3]), 0x6f);
612 m_vdEncMvCost[4] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][4]), 0x6f);
613 m_vdEncMvCost[5] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][5]), 0x6f);
614 m_vdEncMvCost[6] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][6]), 0x6f);
615 m_vdEncMvCost[7] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0][7]), 0x6f);
616
617 if (!m_vdencBrcEnabled)
618 {
619 if (qp == 47 || qp == 48 || qp == 49)
620 {
621 m_vdEncMvCost[3] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1][3]), 0x6f);
622 m_vdEncMvCost[4] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1][4]), 0x6f);
623 m_vdEncMvCost[5] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1][5]), 0x6f);
624 m_vdEncMvCost[6] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1][6]), 0x6f);
625 m_vdEncMvCost[7] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1][7]), 0x6f);
626 }
627 if (qp == 50 || qp == 51)
628 {
629 m_vdEncMvCost[3] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2][3]), 0x6f);
630 m_vdEncMvCost[4] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2][4]), 0x6f);
631 m_vdEncMvCost[5] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2][5]), 0x6f);
632 m_vdEncMvCost[6] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2][6]), 0x6f);
633 m_vdEncMvCost[7] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2][7]), 0x6f);
634 }
635 }
636
637 return eStatus;
638 }
639
LoadHmeMvCost(uint8_t qp)640 MOS_STATUS CodechalVdencAvcStateG9Kbl::LoadHmeMvCost(uint8_t qp)
641 {
642 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
643
644 CODECHAL_ENCODE_FUNCTION_ENTER;
645
646 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS avcSeqParams = m_avcSeqParam;
647 const uint32_t(*puiVdencHmeCostTable)[CODEC_AVC_NUM_QP];
648 if (avcSeqParams->ScenarioInfo == ESCENARIO_DISPLAYREMOTING)
649 {
650 puiVdencHmeCostTable = HmeCost_DisplayRemote;
651 }
652 else
653 {
654 puiVdencHmeCostTable = HmeCost;
655 }
656
657 m_vdEncHmeMvCost[0] = Map44LutValue(*(puiVdencHmeCostTable[0] + qp), 0x6f);
658 m_vdEncHmeMvCost[1] = Map44LutValue(*(puiVdencHmeCostTable[1] + qp), 0x6f);
659 m_vdEncHmeMvCost[2] = Map44LutValue(*(puiVdencHmeCostTable[2] + qp), 0x6f);
660 m_vdEncHmeMvCost[3] = Map44LutValue(*(puiVdencHmeCostTable[3] + qp), 0x6f);
661 m_vdEncHmeMvCost[4] = Map44LutValue(*(puiVdencHmeCostTable[4] + qp), 0x6f);
662 m_vdEncHmeMvCost[5] = Map44LutValue(*(puiVdencHmeCostTable[5] + qp), 0x6f);
663 m_vdEncHmeMvCost[6] = Map44LutValue(*(puiVdencHmeCostTable[6] + qp), 0x6f);
664 m_vdEncHmeMvCost[7] = Map44LutValue(*(puiVdencHmeCostTable[7] + qp), 0x6f);
665
666 return eStatus;
667 }
668
LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams,uint8_t HMEMVCostTable[8][42])669 MOS_STATUS CodechalVdencAvcStateG9Kbl::LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams, uint8_t HMEMVCostTable[8][42])
670 {
671 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
672
673 CODECHAL_ENCODE_FUNCTION_ENTER;
674
675 const uint32_t(*puiVdencHmeCostTable)[CODEC_AVC_NUM_QP];
676 if ((m_avcSeqParam->ScenarioInfo == ESCENARIO_DISPLAYREMOTING) || (m_avcSeqParam->RateControlMethod == RATECONTROL_QVBR))
677 {
678 puiVdencHmeCostTable = HmeCost_DisplayRemote;
679 }
680 else
681 {
682 puiVdencHmeCostTable = HmeCost;
683 }
684
685 for (int i = 0; i < 8; i++)
686 {
687 for (int j = 0; j < 42; j++)
688 {
689 HMEMVCostTable[i][j] = Map44LutValue(*(puiVdencHmeCostTable[i] + j + 10), 0x6f);
690 }
691 }
692
693 return eStatus;
694 }
695
696 #if USE_CODECHAL_DEBUG_TOOL
PopulateBrcInitParam(void * cmd)697 MOS_STATUS CodechalVdencAvcStateG9Kbl::PopulateBrcInitParam(
698 void *cmd)
699 {
700 CODECHAL_DEBUG_FUNCTION_ENTER;
701
702 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
703
704 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
705 {
706 return MOS_STATUS_SUCCESS;
707 }
708
709 PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL dmem = (PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_KBL)cmd;
710
711 if (m_pictureCodingType == I_TYPE)
712 {
713 m_avcPar->MBBRCEnable = m_mbBrcEnabled;
714 m_avcPar->MBRC = m_mbBrcEnabled;
715 m_avcPar->BitRate = dmem->INIT_TargetBitrate_U32;
716 m_avcPar->InitVbvFullnessInBit = dmem->INIT_InitBufFull_U32;
717 m_avcPar->MaxBitRate = dmem->INIT_MaxRate_U32;
718 m_avcPar->VbvSzInBit = dmem->INIT_BufSize_U32;
719 m_avcPar->UserMaxFrame = dmem->INIT_ProfileLevelMaxFrame_U32;
720 m_avcPar->SlidingWindowEnable = dmem->INIT_SlidingWidowRCEnable_U8;
721 m_avcPar->SlidingWindowSize = dmem->INIT_SlidingWindowSize_U8;
722 m_avcPar->SlidingWindowMaxRateRatio = dmem->INIT_SlidingWindowMaxRateRatio_U8;
723 m_avcPar->LowDelayGoldenFrameBoost = dmem->INIT_LowDelayGoldenFrameBoost_U8;
724 m_avcPar->TopQPDeltaThrforAdaptive2Pass = dmem->INIT_TopQPDeltaThrForAdapt2Pass_U8;
725 m_avcPar->BotQPDeltaThrforAdaptive2Pass = dmem->INIT_BotQPDeltaThrForAdapt2Pass_U8;
726 m_avcPar->TopFrmSzPctThrforAdaptive2Pass = dmem->INIT_TopFrmSzThrForAdapt2Pass_U8;
727 m_avcPar->BotFrmSzPctThrforAdaptive2Pass = dmem->INIT_BotFrmSzThrForAdapt2Pass_U8;
728 m_avcPar->MBHeaderCompensation = dmem->INIT_MBHeaderCompensation_U8;
729 m_avcPar->QPSelectMethodforFirstPass = dmem->INIT_QPSelectForFirstPass_U8;
730 m_avcPar->MBQpCtrl = (dmem->INIT_MbQpCtrl_U8 > 0) ? true : false;
731 m_avcPar->QPMax = dmem->INIT_MaxQP_U16;
732 m_avcPar->QPMin = dmem->INIT_MinQP_U16;
733 m_avcPar->HrdConformanceCheckDisable = (dmem->INIT_HRDConformanceCheckDisable_U8 > 0) ? true : false;
734 m_avcPar->ICQReEncode = (dmem->INIT_ICQReEncode_U8 > 0) ? true : false;
735 m_avcPar->AdaptiveCostAdjustEnable = (dmem->INIT_AdaptiveCostEnable_U8 > 0) ? true : false;
736 m_avcPar->AdaptiveHMEExtension = (dmem->INIT_AdaptiveHMEExtensionEnable_U8 > 0) ? true : false;
737 m_avcPar->StreamInStaticRegion = dmem->INIT_StaticRegionStreamIn_U8;
738 ;
739 m_avcPar->ScenarioInfo = dmem->INIT_ScenarioInfo_U8;
740 ;
741 m_avcPar->SliceSizeWA = (dmem->INIT_SliceSizeCtrlWA > 0) ? true : false;
742 }
743
744 return MOS_STATUS_SUCCESS;
745 }
746
PopulateBrcUpdateParam(void * cmd)747 MOS_STATUS CodechalVdencAvcStateG9Kbl::PopulateBrcUpdateParam(
748 void *cmd)
749 {
750 CODECHAL_DEBUG_FUNCTION_ENTER;
751
752 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
753
754 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
755 {
756 return MOS_STATUS_SUCCESS;
757 }
758
759 P_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL dmem = (P_CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_KBL)cmd;
760
761 if (m_pictureCodingType == I_TYPE)
762 {
763 m_avcPar->EnableMultipass = (dmem->UPD_MaxNumPass_U8 > 0) ? true : false;
764 m_avcPar->MaxNumPakPasses = dmem->UPD_MaxNumPass_U8;
765 m_avcPar->SceneChgDetectEn = (dmem->UPD_SceneChgDetectEn_U8 > 0) ? true : false;
766 m_avcPar->SceneChgPrevIntraPctThresh = dmem->UPD_SceneChgPrevIntraPctThreshold_U8;
767 m_avcPar->SceneChgCurIntraPctThresh = dmem->UPD_SceneChgCurIntraPctThreshold_U8;
768 m_avcPar->SceneChgWidth0 = dmem->UPD_SceneChgWidth_U8[0];
769 m_avcPar->SceneChgWidth1 = dmem->UPD_SceneChgWidth_U8[1];
770 m_avcPar->SliceSizeThr = dmem->UPD_SLCSZ_TARGETSLCSZ_U16;
771 m_avcPar->SliceMaxSize = dmem->UPD_TargetSliceSize_U16;
772 }
773 else if (m_pictureCodingType == P_TYPE)
774 {
775 m_avcPar->Transform8x8PDisable = (dmem->UPD_DisablePFrame8x8Transform_U8 > 0) ? true : false;
776 }
777
778 return MOS_STATUS_SUCCESS;
779 }
780
PopulateEncParam(uint8_t meMethod,void * cmd)781 MOS_STATUS CodechalVdencAvcStateG9Kbl::PopulateEncParam(
782 uint8_t meMethod,
783 void *cmd)
784 {
785 CODECHAL_DEBUG_FUNCTION_ENTER;
786
787 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
788
789 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
790 {
791 return MOS_STATUS_SUCCESS;
792 }
793
794 uint8_t *data = nullptr;
795 MOS_LOCK_PARAMS lockFlags;
796 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
797 lockFlags.ReadOnly = 1;
798
799 if (m_vdencBrcEnabled)
800 {
801 // BRC case: VDENC IMG STATE is updated by HuC FW
802 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
803 data = data + mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD::byteSize;
804 }
805 else
806 {
807 // CQP case: VDENC IMG STATE is updated by driver or SFD kernel
808 if (!m_staticFrameDetectionInUse)
809 {
810 data = m_batchBufferForVdencImgStat[m_currRecycledBufIdx].pData;
811 data = data + mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD::byteSize;
812 }
813 else
814 {
815 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencSfdImageStateReadBuffer, &lockFlags);
816 }
817 }
818
819 CODECHAL_DEBUG_CHK_NULL(data);
820
821 mhw_vdbox_vdenc_g9_kbl::VDENC_IMG_STATE_CMD vdencCmd;
822 vdencCmd = *(mhw_vdbox_vdenc_g9_kbl::VDENC_IMG_STATE_CMD *)(data);
823
824 if (m_pictureCodingType == I_TYPE)
825 {
826 m_avcPar->BlockBasedSkip = vdencCmd.DW4.BlockBasedSkipEnabled;
827 m_avcPar->VDEncPerfMode = vdencCmd.DW1.VdencPerfmode;
828 }
829 else if (m_pictureCodingType == P_TYPE)
830 {
831 m_avcPar->SubPelMode = vdencCmd.DW4.SubPelMode;
832 m_avcPar->FTQBasedSkip = vdencCmd.DW4.ForwardTransformSkipCheckEnable;
833 m_avcPar->BiMixDisable = vdencCmd.DW1.BidirectionalMixDisable;
834 m_avcPar->SurvivedSkipCost = (vdencCmd.DW8.NonSkipZeroMvCostAdded << 1) + vdencCmd.DW8.NonSkipMbModeCostAdded;
835 m_avcPar->UniMixDisable = vdencCmd.DW2.UnidirectionalMixDisable;
836 m_avcPar->VdencExtPakObjDisable = !vdencCmd.DW1.VdencExtendedPakObjCmdEnable;
837 m_avcPar->PPMVDisable = vdencCmd.DW34.PpmvDisable;
838 }
839
840 if (data)
841 {
842 if (m_vdencBrcEnabled)
843 {
844 m_osInterface->pfnUnlockResource(
845 m_osInterface,
846 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
847 }
848 else
849 {
850 if (m_staticFrameDetectionInUse)
851 {
852 m_osInterface->pfnUnlockResource(
853 m_osInterface,
854 &m_resVdencSfdImageStateReadBuffer);
855 }
856 }
857 }
858
859 return MOS_STATUS_SUCCESS;
860 }
861
PopulatePakParam(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER secondLevelBatchBuffer)862 MOS_STATUS CodechalVdencAvcStateG9Kbl::PopulatePakParam(
863 PMOS_COMMAND_BUFFER cmdBuffer,
864 PMHW_BATCH_BUFFER secondLevelBatchBuffer)
865 {
866 CODECHAL_DEBUG_FUNCTION_ENTER;
867
868 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
869
870 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
871 {
872 return MOS_STATUS_SUCCESS;
873 }
874
875 uint8_t *data = nullptr;
876 MOS_LOCK_PARAMS lockFlags;
877 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
878 lockFlags.ReadOnly = 1;
879
880 if (cmdBuffer != nullptr)
881 {
882 data = (uint8_t*)(cmdBuffer->pCmdPtr - (mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD::byteSize / sizeof(uint32_t)));
883 }
884 else if (secondLevelBatchBuffer != nullptr)
885 {
886 data = secondLevelBatchBuffer->pData;
887 }
888 else
889 {
890 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
891 }
892
893 CODECHAL_DEBUG_CHK_NULL(data);
894
895 mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD mfxCmd;
896 mfxCmd = *(mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD *)(data);
897
898 if (m_pictureCodingType == I_TYPE)
899 {
900 m_avcPar->TrellisQuantizationEnable = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
901 m_avcPar->EnableAdaptiveTrellisQuantization = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
902 m_avcPar->TrellisQuantizationRounding = mfxCmd.DW5.TrellisQuantizationRoundingTqr;
903 m_avcPar->TrellisQuantizationChromaDisable = mfxCmd.DW5.TrellisQuantizationChromaDisableTqchromadisable;
904 m_avcPar->ExtendedRhoDomainEn = mfxCmd.DW16_17.ExtendedRhodomainStatisticsEnable;
905 }
906
907 if (data && (cmdBuffer == nullptr) && (secondLevelBatchBuffer == nullptr))
908 {
909 m_osInterface->pfnUnlockResource(
910 m_osInterface,
911 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
912 }
913
914 return MOS_STATUS_SUCCESS;
915 }
916 #endif
917