1 //*****************************************************************************
2 //
3 // Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4 //
5 // Redistribution and use in source and binary forms, with or without
6 // modification, are permitted provided that the following conditions
7 // are met:
8 //
9 // Redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer.
11 //
12 // Redistributions in binary form must reproduce the above copyright
13 // notice, this list of conditions and the following disclaimer in the
14 // documentation and/or other materials provided with the
15 // distribution.
16 //
17 // Neither the name of Texas Instruments Incorporated nor the names of
18 // its contributors may be used to endorse or promote products derived
19 // from this software without specific prior written permission.
20 //
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 //
33 // MSP432 Family CMSIS Definitions
34 //
35 //****************************************************************************
36
37 #ifndef CMSIS_CCS_H_
38 #define CMSIS_CCS_H_
39
40 //*****************************************************************************
41 // CMSIS-compatible instruction calls
42 //*****************************************************************************
43
44 #ifndef __cplusplus
45 // No Operation
__nop(void)46 __attribute__( ( always_inline ) ) static inline void __nop(void)
47 {
48 __asm(" nop");
49 }
50
__NOP(void)51 __attribute__( ( always_inline ) ) static inline void __NOP(void)
52 {
53 __asm(" nop");
54 }
55
56 // Wait For Interrupt
__wfi(void)57 __attribute__( ( always_inline ) ) static inline void __wfi(void)
58 {
59 __asm(" wfi");
60 }
61
62 // Wait For Event
__wfe(void)63 __attribute__( ( always_inline ) ) static inline void __wfe(void)
64 {
65 __asm(" wfe");
66 }
67 #endif
68
69 // Enable Interrupts
__enable_irq(void)70 __attribute__( ( always_inline ) ) static inline void __enable_irq(void)
71 {
72 __asm(" cpsie i");
73 }
74
75 // Disable Interrupts
__disable_irq(void)76 __attribute__( ( always_inline ) ) static inline void __disable_irq(void)
77 {
78 __asm(" cpsid i");
79 }
80
81 // Data Synchronization Barrier
__DSB(void)82 __attribute__( ( always_inline ) ) static inline void __DSB(void)
83 {
84 __asm(" dsb");
85 }
86
87 #if (0)
88 // Get Main Stack Pointer
__get_MSP(void)89 static inline uint32_t __get_MSP(void)
90 {
91 register uint32_t result;
92 //__asm (" mrs result, msp");
93 return(result);
94 }
95
96 // Set Main Stack Pointer
__set_MSP(uint32_t topOfMainStack)97 static inline void __set_MSP(uint32_t topOfMainStack)
98 {
99 asm(" .global topOfMainStack");
100 __asm (" msr msp, topOfMainStack");
101 }
102
103
104 // Get Priority Mask
__get_PRIMASK(void)105 static inline uint32_t __get_PRIMASK(void)
106 {
107 uint32_t result;
108 __asm (" mrs result, primask");
109 return(result);
110 }
111
112
113 // Set Priority Mask
__set_PRIMASK(uint32_t priMask)114 static inline void __set_PRIMASK(uint32_t priMask)
115 {
116 __asm (" msr primask, priMask");
117 }
118 #endif
119
120
121 //
122 // v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
123 //
124 #define __CLZ _norm
125 #define __SXTB _sxtb
126 #define __SXTH _sxth
127 #define __UXTB _uxtb
128 #define __UXTH _uxth
129 // CCS supports intrinsics to take advantage of the shift operand left/right
130 // before saturation extension of SSAT, but CMSIS does not take advantage
131 // of those, so tell the compiler to use a sat & shift left with a shift
132 // value of 0 whenever it encounters an SSAT
133 #define __SSAT(VAL, BITPOS) \
134 _ssatl(VAL , 0, BITPOS)
135
136 //
137 // Only define M4 based intrinsics if we're not using an M4
138 //
139 #if defined (__TI_TMS470_V7M4__)
140 //
141 // V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
142 //
143 #define __QADD _sadd
144 #define __QDADD _sdadd
145 #define __QDSUB _sdsub
146 #define __SMLABB _smlabb
147 #define __SMLABT _smlabt
148 #define __SMLALBB _smlalbb
149 #define __SMLALBT _smlalbt
150 #define __SMLALTB _smlaltb
151 #define __SMLALTT _smlaltt
152 #define __SMLATB _smlatb
153 #define __SMLATT _smlatt
154 #define __SMLAWB _smlawb
155 #define __SMLAWT _smlawt
156
157 #define __SMULBB _smulbb
158 #define __SMULBT _smulbt
159 #define __SMULTB _smultb
160 #define __SMULTT _smultt
161 #define __SMULWB _smulwb
162 #define __SMULWT _smulwt
163 #define __QSUB _ssub
164 #define __SUBC _subc
165
166 //
167 // v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
168 //
169 #define __SHASX _shaddsubx
170 #define __SHSAX _shsubaddx
171 #define __PKHBT _pkhbt
172 #define __PKHTB _pkhtb
173 #define __QADD16 _qadd16
174 #define __QADD8 _qadd8
175 #define __QSUB16 _qsub16
176 #define __QSUB8 _qsub8
177 #define __QASX _saddsubx
178 #define __QSAX _qsubaddx
179 #define __SADD16 _sadd16
180 #define __SADD8 _sadd8
181 #define __SASX _saddsubx
182 #define __SEL _sel
183 #define __SHADD16 _shadd16
184 #define __SHADD8 _shadd8
185 #define __SHSUB16 _shsub16
186 #define __SHSUB8 _shsub8
187 #define __SMLAD _smlad
188 #define __SMLADX _smladx
189 #define __SMLALD _smlald
190 #define __SMLALDX _smlaldx
191 #define __SMLSD _smlsd
192 #define __SMLSDX _smlsdx
193 #define __SMLSLD _smlsld
194 #define __SMLSLDX _smlsldx
195 #define __SMMLA _smmla
196 #define __SMMLAR _smmlar
197 #define __SMMLS _smmls
198 #define __SMMLSR _smmlsr
199 #define __SMMUL _smmul
200 #define __SMMULR _smmulr
201 #define __SMUAD _smuad
202 #define __SMUADX _smuadx
203 #define __SMUSD _smusd
204 #define __SMUSDX _smusdx
205 #define __SSAT16 _ssat16
206 #define __SSUB16 _ssub16
207 #define __SSUB8 _ssub8
208 #define __SSAX _ssubaddx
209 #define __SXTAB _sxtab
210 #define __SXTAB16 _sxtab16
211 #define __SXTAH _sxtah
212 #define __UMAAL _umaal
213 #define __UADD16 _uadd16
214 #define __UADD8 _uadd8
215 #define __UHADD16 _uhadd16
216 #define __UHADD8 _uhadd8
217 #define __UASX _uaddsubx
218 #define __UHSUB16 _uhsub16
219 #define __UHSUB8 _uhsub8
220 #define __UQADD16 _uqadd16
221 #define __UQADD8 _uqadd8
222 #define __UQASX _uqaddsubx
223 #define __UQSUB16 _uqsub16
224 #define __UQSUB8 _uqsub8
225 #define __UQSAX _uqsubaddx
226 #define __USAD8 _usad8
227 #define __USAT16 _usat16
228 #define __USUB16 _usub16
229 #define __USUB8 _usub8
230 #define __USAX _usubaddx
231 #define __UXTAB _uxtab
232 #define __UXTAB16 _uxtab16
233 #define __UXTAH _uxtah
234 #define __UXTB16 _uxtb16
235 #endif /*__TI_TMS470_V7M4__*/
236
237 #endif /*CMSIS_CCS_H_*/
238