xref: /aosp_15_r20/external/coreboot/src/arch/x86/include/cf9_reset.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef X86_CF9_RESET_H
4 #define X86_CF9_RESET_H
5 
6 /* Reset control port */
7 #define RST_CNT			0xcf9
8 #define FULL_RST		(1 << 3)
9 #define RST_CPU			(1 << 2)
10 #define SYS_RST			(1 << 1)
11 
12 /* Implement the bare reset, i.e. write to cf9. */
13 void do_system_reset(void);
14 void do_full_reset(void);
15 
16 /* Called by functions below before reset. */
17 #if CONFIG(HAVE_CF9_RESET_PREPARE)
18 void cf9_reset_prepare(void);
19 #else
cf9_reset_prepare(void)20 static inline void cf9_reset_prepare(void) {}
21 #endif
22 
23 /* Prepare for reset, run do_*_reset(), halt. */
24 __noreturn void system_reset(void);
25 __noreturn void full_reset(void);
26 
27 #endif	/* X86_CF9_RESET_H */
28