1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6 #ifndef _DPU_1_14_MSM8917_H 7 #define _DPU_1_14_MSM8917_H 8 9 static const struct dpu_caps msm8917_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 11 .max_mixer_blendstages = 0x4, 12 .max_linewidth = DEFAULT_DPU_LINE_WIDTH, 13 .pixel_ram_size = 16 * 1024, 14 .max_hdeci_exp = MAX_HORZ_DECIMATION, 15 .max_vdeci_exp = MAX_VERT_DECIMATION, 16 }; 17 18 static const struct dpu_mdp_cfg msm8917_mdp[] = { 19 { 20 .name = "top_0", 21 .base = 0x0, .len = 0x454, 22 .features = BIT(DPU_MDP_VSYNC_SEL), 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, 26 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 }, 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 28 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 29 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg msm8917_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x64, 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x1200, .len = 0x64, 40 }, { 41 .name = "ctl_2", .id = CTL_2, 42 .base = 0x1400, .len = 0x64, 43 }, 44 }; 45 46 static const struct dpu_sspp_cfg msm8917_sspp[] = { 47 { 48 .name = "sspp_0", .id = SSPP_VIG0, 49 .base = 0x4000, .len = 0x150, 50 .features = VIG_MSM8953_MASK, 51 .sblk = &dpu_vig_sblk_qseed2, 52 .xin_id = 0, 53 .type = SSPP_TYPE_VIG, 54 .clk_ctrl = DPU_CLK_CTRL_VIG0, 55 }, { 56 .name = "sspp_4", .id = SSPP_RGB0, 57 .base = 0x14000, .len = 0x150, 58 .features = RGB_MSM8953_MASK, 59 .sblk = &dpu_rgb_sblk, 60 .xin_id = 1, 61 .type = SSPP_TYPE_RGB, 62 .clk_ctrl = DPU_CLK_CTRL_RGB0, 63 }, { 64 .name = "sspp_5", .id = SSPP_RGB1, 65 .base = 0x16000, .len = 0x150, 66 .features = RGB_MSM8953_MASK, 67 .sblk = &dpu_rgb_sblk, 68 .xin_id = 5, 69 .type = SSPP_TYPE_RGB, 70 .clk_ctrl = DPU_CLK_CTRL_RGB1, 71 }, { 72 .name = "sspp_8", .id = SSPP_DMA0, 73 .base = 0x24000, .len = 0x150, 74 .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), 75 .sblk = &dpu_dma_sblk, 76 .xin_id = 2, 77 .type = SSPP_TYPE_DMA, 78 .clk_ctrl = DPU_CLK_CTRL_DMA0, 79 }, 80 }; 81 82 static const struct dpu_lm_cfg msm8917_lm[] = { 83 { 84 .name = "lm_0", .id = LM_0, 85 .base = 0x44000, .len = 0x320, 86 .sblk = &msm8998_lm_sblk, 87 .pingpong = PINGPONG_0, 88 .dspp = DSPP_0, 89 }, 90 }; 91 92 static const struct dpu_pingpong_cfg msm8917_pp[] = { 93 { 94 .name = "pingpong_0", .id = PINGPONG_0, 95 .base = 0x70000, .len = 0xd4, 96 .features = PINGPONG_MSM8996_MASK, 97 .sblk = &msm8996_pp_sblk, 98 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 99 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 100 }, 101 }; 102 103 static const struct dpu_dspp_cfg msm8917_dspp[] = { 104 { 105 .name = "dspp_0", .id = DSPP_0, 106 .base = 0x54000, .len = 0x1800, 107 .features = DSPP_SC7180_MASK, 108 .sblk = &msm8998_dspp_sblk, 109 }, 110 }; 111 112 static const struct dpu_intf_cfg msm8917_intf[] = { 113 { 114 .name = "intf_1", .id = INTF_1, 115 .base = 0x6a800, .len = 0x268, 116 .type = INTF_DSI, 117 .controller_id = MSM_DSI_CONTROLLER_0, 118 .prog_fetch_lines_worst_case = 14, 119 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 120 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 121 }, 122 }; 123 124 static const struct dpu_perf_cfg msm8917_perf_data = { 125 .max_bw_low = 1800000, 126 .max_bw_high = 1800000, 127 .min_core_ib = 2400000, 128 .min_llcc_ib = 0, /* No LLCC on this SoC */ 129 .min_dram_ib = 800000, 130 .undersized_prefill_lines = 2, 131 .xtra_prefill_lines = 2, 132 .dest_scale_prefill_lines = 3, 133 .macrotile_prefill_lines = 4, 134 .yuv_nv12_prefill_lines = 8, 135 .linear_prefill_lines = 1, 136 .downscaling_prefill_lines = 1, 137 .amortizable_threshold = 25, 138 .min_prefill_lines = 21, 139 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 140 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 141 .qos_lut_tbl = { 142 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 143 .entries = msm8998_qos_linear 144 }, 145 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 146 .entries = msm8998_qos_macrotile 147 }, 148 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 149 .entries = msm8998_qos_nrt 150 }, 151 }, 152 .cdp_cfg = { 153 {.rd_enable = 1, .wr_enable = 1}, 154 {.rd_enable = 1, .wr_enable = 0} 155 }, 156 .clk_inefficiency_factor = 105, 157 .bw_inefficiency_factor = 120, 158 }; 159 160 static const struct dpu_mdss_version msm8917_mdss_ver = { 161 .core_major_ver = 1, 162 .core_minor_ver = 15, 163 }; 164 165 const struct dpu_mdss_cfg dpu_msm8917_cfg = { 166 .mdss_ver = &msm8917_mdss_ver, 167 .caps = &msm8917_dpu_caps, 168 .mdp = msm8917_mdp, 169 .ctl_count = ARRAY_SIZE(msm8917_ctl), 170 .ctl = msm8917_ctl, 171 .sspp_count = ARRAY_SIZE(msm8917_sspp), 172 .sspp = msm8917_sspp, 173 .mixer_count = ARRAY_SIZE(msm8917_lm), 174 .mixer = msm8917_lm, 175 .dspp_count = ARRAY_SIZE(msm8917_dspp), 176 .dspp = msm8917_dspp, 177 .pingpong_count = ARRAY_SIZE(msm8917_pp), 178 .pingpong = msm8917_pp, 179 .intf_count = ARRAY_SIZE(msm8917_intf), 180 .intf = msm8917_intf, 181 .vbif_count = ARRAY_SIZE(msm8996_vbif), 182 .vbif = msm8996_vbif, 183 .perf = &msm8917_perf_data, 184 }; 185 186 #endif 187