1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6 #ifndef _DPU_1_14_MSM8937_H 7 #define _DPU_1_14_MSM8937_H 8 9 static const struct dpu_caps msm8937_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 11 .max_mixer_blendstages = 0x4, 12 .max_linewidth = DEFAULT_DPU_LINE_WIDTH, 13 .pixel_ram_size = 40 * 1024, 14 .max_hdeci_exp = MAX_HORZ_DECIMATION, 15 .max_vdeci_exp = MAX_VERT_DECIMATION, 16 }; 17 18 static const struct dpu_mdp_cfg msm8937_mdp[] = { 19 { 20 .name = "top_0", 21 .base = 0x0, .len = 0x454, 22 .features = BIT(DPU_MDP_VSYNC_SEL), 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, 26 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 }, 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 28 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 29 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg msm8937_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x64, 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x1200, .len = 0x64, 40 }, { 41 .name = "ctl_2", .id = CTL_2, 42 .base = 0x1400, .len = 0x64, 43 }, 44 }; 45 46 static const struct dpu_sspp_cfg msm8937_sspp[] = { 47 { 48 .name = "sspp_0", .id = SSPP_VIG0, 49 .base = 0x4000, .len = 0x150, 50 .features = VIG_MSM8953_MASK, 51 .sblk = &dpu_vig_sblk_qseed2, 52 .xin_id = 0, 53 .type = SSPP_TYPE_VIG, 54 .clk_ctrl = DPU_CLK_CTRL_VIG0, 55 }, { 56 .name = "sspp_4", .id = SSPP_RGB0, 57 .base = 0x14000, .len = 0x150, 58 .features = RGB_MSM8953_MASK, 59 .sblk = &dpu_rgb_sblk, 60 .xin_id = 1, 61 .type = SSPP_TYPE_RGB, 62 .clk_ctrl = DPU_CLK_CTRL_RGB0, 63 }, { 64 .name = "sspp_5", .id = SSPP_RGB1, 65 .base = 0x16000, .len = 0x150, 66 .features = RGB_MSM8953_MASK, 67 .sblk = &dpu_rgb_sblk, 68 .xin_id = 5, 69 .type = SSPP_TYPE_RGB, 70 .clk_ctrl = DPU_CLK_CTRL_RGB1, 71 }, { 72 .name = "sspp_8", .id = SSPP_DMA0, 73 .base = 0x24000, .len = 0x150, 74 .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), 75 .sblk = &dpu_dma_sblk, 76 .xin_id = 2, 77 .type = SSPP_TYPE_DMA, 78 .clk_ctrl = DPU_CLK_CTRL_DMA0, 79 }, 80 }; 81 82 static const struct dpu_lm_cfg msm8937_lm[] = { 83 { 84 .name = "lm_0", .id = LM_0, 85 .base = 0x44000, .len = 0x320, 86 .sblk = &msm8998_lm_sblk, 87 .lm_pair = LM_1, 88 .pingpong = PINGPONG_0, 89 .dspp = DSPP_0, 90 }, { 91 .name = "lm_1", .id = LM_1, 92 .base = 0x45000, .len = 0x320, 93 .sblk = &msm8998_lm_sblk, 94 .lm_pair = LM_0, 95 .pingpong = PINGPONG_1, 96 }, 97 }; 98 99 static const struct dpu_pingpong_cfg msm8937_pp[] = { 100 { 101 .name = "pingpong_0", .id = PINGPONG_0, 102 .base = 0x70000, .len = 0xd4, 103 .features = PINGPONG_MSM8996_MASK, 104 .sblk = &msm8996_pp_sblk, 105 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 106 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 107 }, { 108 .name = "pingpong_1", .id = PINGPONG_1, 109 .base = 0x70800, .len = 0xd4, 110 .features = PINGPONG_MSM8996_MASK, 111 .sblk = &msm8996_pp_sblk, 112 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 113 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 114 }, 115 }; 116 117 static const struct dpu_dspp_cfg msm8937_dspp[] = { 118 { 119 .name = "dspp_0", .id = DSPP_0, 120 .base = 0x54000, .len = 0x1800, 121 .features = DSPP_SC7180_MASK, 122 .sblk = &msm8998_dspp_sblk, 123 }, 124 }; 125 126 static const struct dpu_intf_cfg msm8937_intf[] = { 127 { 128 .name = "intf_1", .id = INTF_1, 129 .base = 0x6a800, .len = 0x268, 130 .type = INTF_DSI, 131 .controller_id = MSM_DSI_CONTROLLER_0, 132 .prog_fetch_lines_worst_case = 14, 133 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 134 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 135 }, { 136 .name = "intf_2", .id = INTF_2, 137 .base = 0x6b000, .len = 0x268, 138 .type = INTF_DSI, 139 .controller_id = MSM_DSI_CONTROLLER_1, 140 .prog_fetch_lines_worst_case = 14, 141 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 142 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 143 }, 144 }; 145 146 static const struct dpu_perf_cfg msm8937_perf_data = { 147 .max_bw_low = 3100000, 148 .max_bw_high = 3100000, 149 .min_core_ib = 2400000, 150 .min_llcc_ib = 0, /* No LLCC on this SoC */ 151 .min_dram_ib = 800000, 152 .undersized_prefill_lines = 2, 153 .xtra_prefill_lines = 2, 154 .dest_scale_prefill_lines = 3, 155 .macrotile_prefill_lines = 4, 156 .yuv_nv12_prefill_lines = 8, 157 .linear_prefill_lines = 1, 158 .downscaling_prefill_lines = 1, 159 .amortizable_threshold = 25, 160 .min_prefill_lines = 14, 161 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 162 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 163 .qos_lut_tbl = { 164 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 165 .entries = msm8998_qos_linear 166 }, 167 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 168 .entries = msm8998_qos_macrotile 169 }, 170 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 171 .entries = msm8998_qos_nrt 172 }, 173 }, 174 .cdp_cfg = { 175 {.rd_enable = 1, .wr_enable = 1}, 176 {.rd_enable = 1, .wr_enable = 0} 177 }, 178 .clk_inefficiency_factor = 105, 179 .bw_inefficiency_factor = 120, 180 }; 181 182 static const struct dpu_mdss_version msm8937_mdss_ver = { 183 .core_major_ver = 1, 184 .core_minor_ver = 14, 185 }; 186 187 const struct dpu_mdss_cfg dpu_msm8937_cfg = { 188 .mdss_ver = &msm8937_mdss_ver, 189 .caps = &msm8937_dpu_caps, 190 .mdp = msm8937_mdp, 191 .ctl_count = ARRAY_SIZE(msm8937_ctl), 192 .ctl = msm8937_ctl, 193 .sspp_count = ARRAY_SIZE(msm8937_sspp), 194 .sspp = msm8937_sspp, 195 .mixer_count = ARRAY_SIZE(msm8937_lm), 196 .mixer = msm8937_lm, 197 .dspp_count = ARRAY_SIZE(msm8937_dspp), 198 .dspp = msm8937_dspp, 199 .pingpong_count = ARRAY_SIZE(msm8937_pp), 200 .pingpong = msm8937_pp, 201 .intf_count = ARRAY_SIZE(msm8937_intf), 202 .intf = msm8937_intf, 203 .vbif_count = ARRAY_SIZE(msm8996_vbif), 204 .vbif = msm8996_vbif, 205 .perf = &msm8937_perf_data, 206 }; 207 208 #endif 209