1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
3
4 #ifndef HWS_BWC_H_
5 #define HWS_BWC_H_
6
7 #define MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG 1
8 #define MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP 1
9 #define MLX5HWS_BWC_MATCHER_REHASH_PERCENT_TH 70
10 #define MLX5HWS_BWC_MATCHER_REHASH_BURST_TH 32
11
12 /* Max number of AT attach operations for the same matcher.
13 * When the limit is reached, next attempt to attach new AT
14 * will result in creation of a new matcher and moving all
15 * the rules to this matcher.
16 */
17 #define MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM 8
18
19 #define MLX5HWS_BWC_MAX_ACTS 16
20
21 #define MLX5HWS_BWC_POLLING_TIMEOUT 60
22
23 struct mlx5hws_bwc_matcher {
24 struct mlx5hws_matcher *matcher;
25 struct mlx5hws_match_template *mt;
26 struct mlx5hws_action_template *at[MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM];
27 u32 priority;
28 u8 num_of_at;
29 u8 size_log;
30 atomic_t num_of_rules;
31 struct list_head *rules;
32 };
33
34 struct mlx5hws_bwc_rule {
35 struct mlx5hws_bwc_matcher *bwc_matcher;
36 struct mlx5hws_rule *rule;
37 u16 bwc_queue_idx;
38 struct list_head list_node;
39 };
40
41 int
42 mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_matcher *bwc_matcher,
43 struct mlx5hws_table *table,
44 u32 priority,
45 u8 match_criteria_enable,
46 struct mlx5hws_match_parameters *mask,
47 enum mlx5hws_action_type action_types[]);
48
49 int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws_bwc_matcher *bwc_matcher);
50
51 struct mlx5hws_bwc_rule *mlx5hws_bwc_rule_alloc(struct mlx5hws_bwc_matcher *bwc_matcher);
52
53 void mlx5hws_bwc_rule_free(struct mlx5hws_bwc_rule *bwc_rule);
54
55 int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule,
56 u32 *match_param,
57 struct mlx5hws_rule_action rule_actions[],
58 u32 flow_source,
59 u16 bwc_queue_idx);
60
61 int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule);
62
63 void mlx5hws_bwc_rule_fill_attr(struct mlx5hws_bwc_matcher *bwc_matcher,
64 u16 bwc_queue_idx,
65 u32 flow_source,
66 struct mlx5hws_rule_attr *rule_attr);
67
mlx5hws_bwc_queues(struct mlx5hws_context * ctx)68 static inline u16 mlx5hws_bwc_queues(struct mlx5hws_context *ctx)
69 {
70 /* Besides the control queue, half of the queues are
71 * regular HWS queues, and the other half are BWC queues.
72 */
73 if (mlx5hws_context_bwc_supported(ctx))
74 return (ctx->queues - 1) / 2;
75 return 0;
76 }
77
mlx5hws_bwc_get_queue_id(struct mlx5hws_context * ctx,u16 idx)78 static inline u16 mlx5hws_bwc_get_queue_id(struct mlx5hws_context *ctx, u16 idx)
79 {
80 return idx + mlx5hws_bwc_queues(ctx);
81 }
82
83 #endif /* HWS_BWC_H_ */
84