xref: /aosp_15_r20/external/mesa3d/src/intel/blorp/blorp_nir_builder.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "compiler/nir/nir_builder.h"
25 #include "blorp_priv.h"
26 
27 static inline void
blorp_nir_init_shader(nir_builder * b,struct blorp_context * blorp,void * mem_ctx,gl_shader_stage stage,const char * name)28 blorp_nir_init_shader(nir_builder *b,
29                       struct blorp_context *blorp,
30                       void *mem_ctx,
31                       gl_shader_stage stage,
32                       const char *name)
33 {
34    const nir_shader_compiler_options *nir_options =
35       blorp->compiler->nir_options(blorp, stage);
36 
37    *b = nir_builder_init_simple_shader(stage, nir_options,
38                                        "%s", name ? name : "");
39    ralloc_steal(mem_ctx, b->shader);
40    if (stage == MESA_SHADER_FRAGMENT)
41       b->shader->info.fs.origin_upper_left = true;
42 }
43 
44 static inline nir_def *
blorp_nir_txf_ms_mcs(nir_builder * b,nir_def * xy_pos,nir_def * layer)45 blorp_nir_txf_ms_mcs(nir_builder *b, nir_def *xy_pos, nir_def *layer)
46 {
47    nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
48    tex->op = nir_texop_txf_ms_mcs_intel;
49    tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
50    tex->dest_type = nir_type_int32;
51 
52    nir_def *coord;
53    if (layer) {
54       tex->is_array = true;
55       tex->coord_components = 3;
56       coord = nir_vec3(b, nir_channel(b, xy_pos, 0),
57                           nir_channel(b, xy_pos, 1),
58                           layer);
59    } else {
60       tex->is_array = false;
61       tex->coord_components = 2;
62       coord = nir_trim_vector(b, xy_pos, 2);
63    }
64    tex->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord, coord);
65 
66    /* Blorp only has one texture and it's bound at unit 0 */
67    tex->texture_index = 0;
68    tex->sampler_index = 0;
69 
70    nir_def_init(&tex->instr, &tex->def, 4, 32);
71    nir_builder_instr_insert(b, &tex->instr);
72 
73    return &tex->def;
74 }
75 
76 static inline nir_def *
blorp_nir_mcs_is_clear_color(nir_builder * b,nir_def * mcs,uint32_t samples)77 blorp_nir_mcs_is_clear_color(nir_builder *b,
78                              nir_def *mcs,
79                              uint32_t samples)
80 {
81    switch (samples) {
82    case 2:
83       /* Empirical evidence suggests that the value returned from the
84        * sampler is not always 0x3 for clear color so we need to mask it.
85        */
86       return nir_ieq_imm(b, nir_iand(b, nir_channel(b, mcs, 0),
87                                         nir_imm_int(b, 0x3)),
88                             0x3);
89 
90    case 4:
91       return nir_ieq_imm(b, nir_channel(b, mcs, 0), 0xff);
92 
93    case 8:
94       return nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0);
95 
96    case 16:
97       /* For 16x MSAA, the MCS is actually an ivec2 */
98       return nir_iand(b, nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0),
99                          nir_ieq_imm(b, nir_channel(b, mcs, 1), ~0));
100 
101    default:
102       unreachable("Invalid sample count");
103    }
104 }
105 
106 static inline nir_def *
blorp_check_in_bounds(nir_builder * b,nir_def * bounds_rect,nir_def * pos)107 blorp_check_in_bounds(nir_builder *b,
108                       nir_def *bounds_rect,
109                       nir_def *pos)
110 {
111    nir_def *x0 = nir_channel(b, bounds_rect, 0);
112    nir_def *x1 = nir_channel(b, bounds_rect, 1);
113    nir_def *y0 = nir_channel(b, bounds_rect, 2);
114    nir_def *y1 = nir_channel(b, bounds_rect, 3);
115 
116    nir_def *c0 = nir_uge(b, nir_channel(b, pos, 0), x0);
117    nir_def *c1 = nir_ult(b, nir_channel(b, pos, 0), x1);
118    nir_def *c2 = nir_uge(b, nir_channel(b, pos, 1), y0);
119    nir_def *c3 = nir_ult(b, nir_channel(b, pos, 1), y1);
120 
121    nir_def *in_bounds =
122       nir_iand(b, nir_iand(b, c0, c1), nir_iand(b, c2, c3));
123 
124    return in_bounds;
125 }
126