1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "brcm,bcm6846", "brcm,bcmbca"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 CA7_0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a7"; 23 reg = <0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 CA7_1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 L2_0: l2-cache0 { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 timer { 44 compatible = "arm,armv7-timer"; 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 49 arm,cpu-registers-not-fw-configured; 50 }; 51 52 pmu: pmu { 53 compatible = "arm,cortex-a7-pmu"; 54 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-affinity = <&CA7_0>, <&CA7_1>; 57 }; 58 59 clocks: clocks { 60 periph_clk: periph-clk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <200000000>; 64 }; 65 66 hsspi_pll: hsspi-pll { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <400000000>; 70 }; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 axi@81000000 { 79 compatible = "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0 0x81000000 0x8000>; 83 84 gic: interrupt-controller@1000 { 85 compatible = "arm,cortex-a7-gic"; 86 #interrupt-cells = <3>; 87 interrupt-controller; 88 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 89 reg = <0x1000 0x1000>, 90 <0x2000 0x2000>, 91 <0x4000 0x2000>, 92 <0x6000 0x2000>; 93 }; 94 }; 95 96 bus@ff800000 { 97 compatible = "simple-bus"; 98 #address-cells = <1>; 99 #size-cells = <1>; 100 ranges = <0 0xff800000 0x800000>; 101 102 watchdog@480 { 103 compatible = "brcm,bcm6345-wdt"; 104 reg = <0x480 0x10>; 105 }; 106 107 /* GPIOs 0 .. 31 */ 108 gpio0: gpio@500 { 109 compatible = "brcm,bcm6345-gpio"; 110 reg = <0x500 0x04>, <0x520 0x04>; 111 reg-names = "dirout", "dat"; 112 gpio-controller; 113 #gpio-cells = <2>; 114 status = "disabled"; 115 }; 116 117 /* GPIOs 32 .. 63 */ 118 gpio1: gpio@504 { 119 compatible = "brcm,bcm6345-gpio"; 120 reg = <0x504 0x04>, <0x524 0x04>; 121 reg-names = "dirout", "dat"; 122 gpio-controller; 123 #gpio-cells = <2>; 124 status = "disabled"; 125 }; 126 127 /* GPIOs 64 .. 95 */ 128 gpio2: gpio@508 { 129 compatible = "brcm,bcm6345-gpio"; 130 reg = <0x508 0x04>, <0x528 0x04>; 131 reg-names = "dirout", "dat"; 132 gpio-controller; 133 #gpio-cells = <2>; 134 status = "disabled"; 135 }; 136 137 /* GPIOs 96 .. 127 */ 138 gpio3: gpio@50c { 139 compatible = "brcm,bcm6345-gpio"; 140 reg = <0x50c 0x04>, <0x52c 0x04>; 141 reg-names = "dirout", "dat"; 142 gpio-controller; 143 #gpio-cells = <2>; 144 status = "disabled"; 145 }; 146 147 /* GPIOs 128 .. 159 */ 148 gpio4: gpio@510 { 149 compatible = "brcm,bcm6345-gpio"; 150 reg = <0x510 0x04>, <0x530 0x04>; 151 reg-names = "dirout", "dat"; 152 gpio-controller; 153 #gpio-cells = <2>; 154 status = "disabled"; 155 }; 156 157 /* GPIOs 160 .. 191 */ 158 gpio5: gpio@514 { 159 compatible = "brcm,bcm6345-gpio"; 160 reg = <0x514 0x04>, <0x534 0x04>; 161 reg-names = "dirout", "dat"; 162 gpio-controller; 163 #gpio-cells = <2>; 164 status = "disabled"; 165 }; 166 167 /* GPIOs 192 .. 223 */ 168 gpio6: gpio@518 { 169 compatible = "brcm,bcm6345-gpio"; 170 reg = <0x518 0x04>, <0x538 0x04>; 171 reg-names = "dirout", "dat"; 172 gpio-controller; 173 #gpio-cells = <2>; 174 status = "disabled"; 175 }; 176 177 /* GPIOs 224 .. 255 */ 178 gpio7: gpio@51c { 179 compatible = "brcm,bcm6345-gpio"; 180 reg = <0x51c 0x04>, <0x53c 0x04>; 181 reg-names = "dirout", "dat"; 182 gpio-controller; 183 #gpio-cells = <2>; 184 status = "disabled"; 185 }; 186 187 uart0: serial@640 { 188 compatible = "brcm,bcm6345-uart"; 189 reg = <0x640 0x1b>; 190 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&periph_clk>; 192 clock-names = "refclk"; 193 status = "disabled"; 194 }; 195 196 rng@b80 { 197 compatible = "brcm,iproc-rng200"; 198 reg = <0xb80 0x28>; 199 }; 200 201 leds: led-controller@800 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "brcm,bcm63138-leds"; 205 reg = <0x800 0xdc>; 206 status = "disabled"; 207 }; 208 209 hsspi: spi@1000 { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0"; 213 reg = <0x1000 0x600>; 214 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&hsspi_pll &hsspi_pll>; 216 clock-names = "hsspi", "pll"; 217 num-cs = <8>; 218 status = "disabled"; 219 }; 220 221 nand_controller: nand-controller@1800 { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 225 reg = <0x1800 0x600>, <0x2000 0x10>; 226 reg-names = "nand", "nand-int-base"; 227 status = "disabled"; 228 229 nandcs: nand@0 { 230 compatible = "brcm,nandcs"; 231 reg = <0>; 232 }; 233 }; 234 235 mdio: mdio@2060 { 236 compatible = "brcm,bcm6846-mdio"; 237 reg = <0x02060 0x10>, <0x5a068 0x4>; 238 reg-names = "mdio", "mdio_indir_rw"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 pl081_dma: dma-controller@59000 { 245 compatible = "arm,pl081", "arm,primecell"; 246 // The magic B105F00D info is missing 247 arm,primecell-periphid = <0x00041081>; 248 reg = <0x59000 0x1000>; 249 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 250 memcpy-burst-size = <256>; 251 memcpy-bus-width = <32>; 252 clocks = <&periph_clk>; 253 clock-names = "apb_pclk"; 254 #dma-cells = <2>; 255 }; 256 }; 257}; 258