1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/phy/phy.h>
6#include <dt-bindings/soc/bcm-pmb.h>
7
8/dts-v1/;
9
10/ {
11	interrupt-parent = <&gic>;
12
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	aliases {
17		serial0 = &uart0;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "brcm,brahma-b53";
31			reg = <0x0>;
32			enable-method = "spin-table";
33			cpu-release-addr = <0x0 0xff8>;
34			next-level-cache = <&l2>;
35		};
36
37		cpu1: cpu@1 {
38			device_type = "cpu";
39			compatible = "brcm,brahma-b53";
40			reg = <0x1>;
41			enable-method = "spin-table";
42			cpu-release-addr = <0x0 0xff8>;
43			next-level-cache = <&l2>;
44		};
45
46		cpu2: cpu@2 {
47			device_type = "cpu";
48			compatible = "brcm,brahma-b53";
49			reg = <0x2>;
50			enable-method = "spin-table";
51			cpu-release-addr = <0x0 0xff8>;
52			next-level-cache = <&l2>;
53		};
54
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "brcm,brahma-b53";
58			reg = <0x3>;
59			enable-method = "spin-table";
60			cpu-release-addr = <0x0 0xff8>;
61			next-level-cache = <&l2>;
62		};
63
64		l2: l2-cache0 {
65			compatible = "cache";
66			cache-level = <2>;
67			cache-unified;
68		};
69	};
70
71	reserved-memory {
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		cfe-stub@0 {
77			reg = <0x0 0x0 0x0 0x1000>;
78		};
79	};
80
81	axi@81000000 {
82		compatible = "simple-bus";
83		#address-cells = <1>;
84		#size-cells = <1>;
85		ranges = <0x00 0x00 0x81000000 0x4000>;
86
87		gic: interrupt-controller@1000 {
88			compatible = "arm,gic-400";
89			#interrupt-cells = <3>;
90			#address-cells = <0>;
91			interrupt-controller;
92			reg = <0x1000 0x1000>,
93			      <0x2000 0x2000>;
94		};
95	};
96
97	timer {
98		compatible = "arm,armv8-timer";
99		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
101			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
102			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
103	};
104
105	pmu {
106		compatible = "arm,cortex-a53-pmu";
107		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
109			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
110			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
111		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
112	};
113
114	clocks {
115		periph_clk: periph_clk {
116			compatible = "fixed-clock";
117			#clock-cells = <0>;
118			clock-frequency = <50000000>;
119			clock-output-names = "periph";
120		};
121
122		hsspi_pll: hsspi-pll {
123			compatible = "fixed-clock";
124			#clock-cells = <0>;
125			clock-frequency = <400000000>;
126		};
127	};
128
129	soc {
130		compatible = "simple-bus";
131		#address-cells = <1>;
132		#size-cells = <1>;
133		ranges = <0x00 0x00 0x80000000 0x281000>;
134
135		enet: ethernet@2000 {
136			compatible = "brcm,bcm4908-enet";
137			reg = <0x2000 0x1000>;
138
139			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
140				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
141			interrupt-names = "rx", "tx";
142		};
143
144		usb_phy: usb-phy@c200 {
145			compatible = "brcm,bcm4908-usb-phy";
146			reg = <0xc200 0x100>;
147			reg-names = "ctrl";
148			power-domains = <&pmb BCM_PMB_HOST_USB>;
149			dr_mode = "host";
150			brcm,has-xhci;
151			brcm,has-eohci;
152			#phy-cells = <1>;
153			status = "disabled";
154		};
155
156		ehci: usb@c300 {
157			compatible = "generic-ehci";
158			reg = <0xc300 0x100>;
159			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
160			phys = <&usb_phy PHY_TYPE_USB2>;
161			status = "disabled";
162
163			#address-cells = <1>;
164			#size-cells = <0>;
165
166			ehci_port1: port@1 {
167				reg = <1>;
168				#trigger-source-cells = <0>;
169			};
170
171			ehci_port2: port@2 {
172				reg = <2>;
173				#trigger-source-cells = <0>;
174			};
175		};
176
177		ohci: usb@c400 {
178			compatible = "generic-ohci";
179			reg = <0xc400 0x100>;
180			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
181			phys = <&usb_phy PHY_TYPE_USB2>;
182			status = "disabled";
183
184			#address-cells = <1>;
185			#size-cells = <0>;
186
187			ohci_port1: port@1 {
188				reg = <1>;
189				#trigger-source-cells = <0>;
190			};
191
192			ohci_port2: port@2 {
193				reg = <2>;
194				#trigger-source-cells = <0>;
195			};
196		};
197
198		xhci: usb@d000 {
199			compatible = "generic-xhci";
200			reg = <0xd000 0x8c8>;
201			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
202			phys = <&usb_phy PHY_TYPE_USB3>;
203			status = "disabled";
204
205			#address-cells = <1>;
206			#size-cells = <0>;
207
208			xhci_port1: port@1 {
209				reg = <1>;
210				#trigger-source-cells = <0>;
211			};
212
213			xhci_port2: port@2 {
214				reg = <2>;
215				#trigger-source-cells = <0>;
216			};
217		};
218
219		bus@80000 {
220			compatible = "simple-bus";
221			#size-cells = <1>;
222			#address-cells = <1>;
223			ranges = <0 0x80000 0x50000>;
224
225			ethernet-switch@0 {
226				compatible = "brcm,bcm4908-switch";
227				reg = <0x0 0x40000>,
228				      <0x40000 0x110>,
229				      <0x40340 0x30>,
230				      <0x40380 0x30>,
231				      <0x40600 0x34>,
232				      <0x40800 0x208>;
233				reg-names = "core", "reg", "intrl2_0",
234					    "intrl2_1", "fcb", "acb";
235				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
236					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
237				brcm,num-gphy = <5>;
238				brcm,num-rgmii-ports = <2>;
239
240				ports: ports {
241					#address-cells = <1>;
242					#size-cells = <0>;
243
244					port@0 {
245						reg = <0>;
246						phy-mode = "internal";
247						phy-handle = <&phy8>;
248					};
249
250					port@1 {
251						reg = <1>;
252						phy-mode = "internal";
253						phy-handle = <&phy9>;
254					};
255
256					port@2 {
257						reg = <2>;
258						phy-mode = "internal";
259						phy-handle = <&phy10>;
260					};
261
262					port@3 {
263						reg = <3>;
264						phy-mode = "internal";
265						phy-handle = <&phy11>;
266					};
267
268					port@8 {
269						reg = <8>;
270						phy-mode = "internal";
271						ethernet = <&enet>;
272
273						fixed-link {
274							speed = <1000>;
275							full-duplex;
276						};
277					};
278				};
279			};
280
281			mdio: mdio@405c0 {
282				compatible = "brcm,unimac-mdio";
283				reg = <0x405c0 0x8>;
284				reg-names = "mdio";
285				#size-cells = <0>;
286				#address-cells = <1>;
287
288				phy8: ethernet-phy@8 {
289					reg = <8>;
290				};
291
292				phy9: ethernet-phy@9 {
293					reg = <9>;
294				};
295
296				phy10: ethernet-phy@a {
297					reg = <10>;
298				};
299
300				phy11: ethernet-phy@b {
301					reg = <11>;
302				};
303
304				phy12: ethernet-phy@c {
305					reg = <12>;
306				};
307			};
308		};
309
310		procmon: bus@280000 {
311			compatible = "simple-bus";
312			reg = <0x280000 0x1000>;
313			ranges;
314
315			#address-cells = <1>;
316			#size-cells = <1>;
317
318			pmb: power-controller@2800c0 {
319				compatible = "brcm,bcm4908-pmb";
320				reg = <0x2800c0 0x40>;
321				#power-domain-cells = <1>;
322			};
323		};
324	};
325
326	bus@ff800000 {
327		compatible = "simple-bus";
328		#address-cells = <1>;
329		#size-cells = <1>;
330		ranges = <0x00 0x00 0xff800000 0x3000>;
331
332		twd: timer-mfd@400 {
333			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
334			reg = <0x400 0x4c>;
335			ranges = <0x0 0x400 0x4c>;
336
337			#address-cells = <1>;
338			#size-cells = <1>;
339
340			timer@0 {
341				compatible = "brcm,bcm63138-timer";
342				reg = <0x0 0x28>;
343			};
344
345			watchdog@28 {
346				compatible = "brcm,bcm6345-wdt";
347				reg = <0x28 0x8>;
348			};
349		};
350
351		gpio0: gpio-controller@500 {
352			compatible = "brcm,bcm6345-gpio";
353			reg-names = "dirout", "dat";
354			reg = <0x500 0x28>, <0x528 0x28>;
355
356			#gpio-cells = <2>;
357			gpio-controller;
358		};
359
360		pinctrl@560 {
361			compatible = "brcm,bcm4908-pinctrl";
362			reg = <0x560 0x10>;
363
364			pins_led_0_a: led_0-a-pins {
365				function = "led_0";
366				groups = "led_0_grp_a";
367			};
368
369			pins_led_1_a: led_1-a-pins {
370				function = "led_1";
371				groups = "led_1_grp_a";
372			};
373
374			pins_led_2_a: led_2-a-pins {
375				function = "led_2";
376				groups = "led_2_grp_a";
377			};
378
379			pins_led_3_a: led_3-a-pins {
380				function = "led_3";
381				groups = "led_3_grp_a";
382			};
383
384			pins_led_4_a: led_4-a-pins {
385				function = "led_4";
386				groups = "led_4_grp_a";
387			};
388
389			pins_led_5_a: led_5-a-pins {
390				function = "led_5";
391				groups = "led_5_grp_a";
392			};
393
394			pins_led_6_a: led_6-a-pins {
395				function = "led_6";
396				groups = "led_6_grp_a";
397			};
398
399			pins_led_7_a: led_7-a-pins {
400				function = "led_7";
401				groups = "led_7_grp_a";
402			};
403
404			pins_led_8_a: led_8-a-pins {
405				function = "led_8";
406				groups = "led_8_grp_a";
407			};
408
409			pins_led_9_a: led_9-a-pins {
410				function = "led_9";
411				groups = "led_9_grp_a";
412			};
413
414			pins_led_10_a: led_10-a-pins {
415				function = "led_10";
416				groups = "led_10_grp_a";
417			};
418
419			pins_led_11_a: led_11-a-pins {
420				function = "led_11";
421				groups = "led_11_grp_a";
422			};
423
424			pins_led_12_a: led_12-a-pins {
425				function = "led_12";
426				groups = "led_12_grp_a";
427			};
428
429			pins_led_13_a: led_13-a-pins {
430				function = "led_13";
431				groups = "led_13_grp_a";
432			};
433
434			pins_led_14_a: led_14-a-pins {
435				function = "led_14";
436				groups = "led_14_grp_a";
437			};
438
439			pins_led_15_a: led_15-a-pins {
440				function = "led_15";
441				groups = "led_15_grp_a";
442			};
443
444			pins_led_16_a: led_16-a-pins {
445				function = "led_16";
446				groups = "led_16_grp_a";
447			};
448
449			pins_led_17_a: led_17-a-pins {
450				function = "led_17";
451				groups = "led_17_grp_a";
452			};
453
454			pins_led_18_a: led_18-a-pins {
455				function = "led_18";
456				groups = "led_18_grp_a";
457			};
458
459			pins_led_19_a: led_19-a-pins {
460				function = "led_19";
461				groups = "led_19_grp_a";
462			};
463
464			pins_led_20_a: led_20-a-pins {
465				function = "led_20";
466				groups = "led_20_grp_a";
467			};
468
469			pins_led_21_a: led_21-a-pins {
470				function = "led_21";
471				groups = "led_21_grp_a";
472			};
473
474			pins_led_22_a: led_22-a-pins {
475				function = "led_22";
476				groups = "led_22_grp_a";
477			};
478
479			pins_led_23_a: led_23-a-pins {
480				function = "led_23";
481				groups = "led_23_grp_a";
482			};
483
484			pins_led_24_a: led_24-a-pins {
485				function = "led_24";
486				groups = "led_24_grp_a";
487			};
488
489			pins_led_25_a: led_25-a-pins {
490				function = "led_25";
491				groups = "led_25_grp_a";
492			};
493
494			pins_led_26_a: led_26-a-pins {
495				function = "led_26";
496				groups = "led_26_grp_a";
497			};
498
499			pins_led_27_a: led_27-a-pins {
500				function = "led_27";
501				groups = "led_27_grp_a";
502			};
503
504			pins_led_28_a: led_28-a-pins {
505				function = "led_28";
506				groups = "led_28_grp_a";
507			};
508
509			pins_led_29_a: led_29-a-pins {
510				function = "led_29";
511				groups = "led_29_grp_a";
512			};
513
514			pins_led_30_a: led_30-a-pins {
515				function = "led_30";
516				groups = "led_30_grp_a";
517			};
518
519			pins_led_31_a: led_31-a-pins {
520				function = "led_31";
521				groups = "led_31_grp_a";
522			};
523
524			pins_hs_uart: hs_uart-pins {
525				function = "hs_uart";
526				groups = "hs_uart_grp";
527			};
528
529			pins_i2c_a: i2c-a-pins {
530				function = "i2c";
531				groups = "i2c_grp_a";
532			};
533
534			pins_i2c_b: i2c-b-pins {
535				function = "i2c";
536				groups = "i2c_grp_b";
537			};
538
539			pins_i2s: i2s-pins {
540				function = "i2s";
541				groups = "i2s_grp";
542			};
543
544			pins_nand_ctrl: nand_ctrl-pins {
545				function = "nand_ctrl";
546				groups = "nand_ctrl_grp";
547			};
548
549			pins_nand_data: nand_data-pins {
550				function = "nand_data";
551				groups = "nand_data_grp";
552			};
553
554			pins_emmc_ctrl: emmc_ctrl-pins {
555				function = "emmc_ctrl";
556				groups = "emmc_ctrl_grp";
557			};
558
559			pins_usb0_pwr: usb0_pwr-pins {
560				function = "usb0_pwr";
561				groups = "usb0_pwr_grp";
562			};
563
564			pins_usb1_pwr: usb1_pwr-pins {
565				function = "usb1_pwr";
566				groups = "usb1_pwr_grp";
567			};
568		};
569
570		uart0: serial@640 {
571			compatible = "brcm,bcm6345-uart";
572			reg = <0x640 0x18>;
573			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
574			clocks = <&periph_clk>;
575			clock-names = "refclk";
576			status = "okay";
577		};
578
579		leds: leds@800 {
580			compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
581			reg = <0x800 0xdc>;
582
583			#address-cells = <1>;
584			#size-cells = <0>;
585		};
586
587		hsspi: spi@1000 {
588			#address-cells = <1>;
589			#size-cells = <0>;
590			compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
591			reg = <0x1000 0x600>;
592			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
593			clocks = <&hsspi_pll &hsspi_pll>;
594			clock-names = "hsspi", "pll";
595			num-cs = <8>;
596			status = "disabled";
597		};
598
599		nand_controller: nand-controller@1800 {
600			#address-cells = <1>;
601			#size-cells = <0>;
602			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
603			reg = <0x1800 0x600>, <0x2000 0x10>;
604			reg-names = "nand", "nand-int-base";
605			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
606			interrupt-names = "nand_ctlrdy";
607			brcm,wp-not-connected;
608			status = "disabled";
609
610			nandcs: nand@0 {
611				compatible = "brcm,nandcs";
612				reg = <0>;
613			};
614		};
615
616		i2c@2100 {
617			compatible = "brcm,brcmper-i2c";
618			reg = <0x2100 0x58>;
619			clock-frequency = <97500>;
620			pinctrl-names = "default";
621			pinctrl-0 = <&pins_i2c_a>;
622			status = "disabled";
623		};
624
625		misc@2600 {
626			compatible = "brcm,misc", "simple-mfd";
627			reg = <0x2600 0xe4>;
628
629			#address-cells = <1>;
630			#size-cells = <1>;
631			ranges = <0x00 0x2600 0xe4>;
632
633			reset-controller@2644 {
634				compatible = "brcm,bcm4908-misc-pcie-reset";
635				reg = <0x44 0x04>;
636				#reset-cells = <1>;
637			};
638		};
639	};
640
641	reboot {
642		compatible = "syscon-reboot";
643		regmap = <&twd>;
644		offset = <0x34>;
645		mask = <1>;
646	};
647};
648