1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2012 Intel Corporation. All Rights Reserved. 6 */ 7 8 #ifndef ATOMISP_REGS_H 9 #define ATOMISP_REGS_H 10 11 /* common register definitions */ 12 #define PCICMDSTS 0x01 13 #define INTR 0x0f 14 #define MSI_CAPID 0x24 15 #define MSI_ADDRESS 0x25 16 #define MSI_DATA 0x26 17 #define INTR_CTL 0x27 18 19 #define PCI_MSI_CAPID 0x90 20 #define PCI_MSI_ADDR 0x94 21 #define PCI_MSI_DATA 0x98 22 #define PCI_INTERRUPT_CTRL 0x9C 23 #define PCI_I_CONTROL 0xfc 24 25 /* MRFLD specific register definitions */ 26 #define MRFLD_CSI_AFE 0x39 27 #define MRFLD_CSI_CONTROL 0x3a 28 #define MRFLD_CSI_RCOMP 0x3d 29 30 #define MRFLD_PCI_PMCS 0x84 31 #define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4 32 #define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc 33 #define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0 34 #define MRFLD_PCI_CSI_CONTROL 0xe8 35 #define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4 36 #define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec 37 #define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4 38 39 /* Select Arasan (legacy)/Intel input system */ 40 #define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24) 41 /* Enable CSI interface (ANN B0/K0) */ 42 #define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25) 43 44 /* 45 * Enables the combining of adjacent 32-byte read requests to the same 46 * cache line. When cleared, each 32-byte read request is sent as a 47 * separate request on the IB interface. 48 */ 49 #define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1 50 51 /* 52 * Register: MRFLD_PCI_CSI_RCOMP_CONTROL 53 * If cleared, the high speed clock going to the digital logic is gated when 54 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec. 55 * If this bit is set, then the high speed clock is not gated during the 56 * update cycle. 57 */ 58 #define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000 59 60 /* 61 * Enables the combining of adjacent 32-byte write requests to the same 62 * cache line. When cleared, each 32-byte write request is sent as a 63 * separate request on the IB interface. 64 */ 65 #define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2 66 67 #define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc 68 69 #define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2 70 #define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16 71 #define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3 72 #define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24 73 #define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2 74 #define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28 75 #define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf 76 77 /* 78 * This register is IUINT MMIO register, it is used to select the CSI 79 * receiver backend. 80 * 1: SH CSI backend 81 * 0: Arasan CSI backend 82 */ 83 #define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c 84 85 #define MRFLD_INTR_CLEAR_REG 0x50c 86 #define MRFLD_INTR_STATUS_REG 0x508 87 #define MRFLD_INTR_ENABLE_REG 0x510 88 89 #define MRFLD_MAX_ZOOM_FACTOR 1024 90 91 /* MRFLD ISP POWER related */ 92 #define MRFLD_ISPSSPM0 0x39 93 #define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0 94 #define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24 95 #define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3 96 #define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0 97 #define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3 98 #define MRFLD_ISPSSDVFS 0x13F 99 #define MRFLD_BIT0 0x0001 100 #define MRFLD_BIT1 0x0002 101 102 /* MRFLD CSI lane configuration related */ 103 #define MRFLD_PORT_CONFIG_NUM 8 104 #define MRFLD_PORT1_ENABLE_SHIFT 0 105 #define MRFLD_PORT2_ENABLE_SHIFT 1 106 #define MRFLD_PORT3_ENABLE_SHIFT 2 107 #define MRFLD_PORT1_LANES_SHIFT 3 108 #define MRFLD_PORT2_LANES_SHIFT 7 109 #define MRFLD_PORT3_LANES_SHIFT 8 110 #define MRFLD_PORT_CONFIG_MASK 0x000f03ff 111 #define MRFLD_PORT_CONFIGCODE_SHIFT 16 112 #define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7 113 114 #define CHV_PORT3_LANES_SHIFT 9 115 #define CHV_PORT_CONFIG_MASK 0x1f07ff 116 117 #define ISPSSPM1 0x3a 118 #define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET) 119 #define ISP_REQ_FREQ_MASK 0x1f 120 #define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET) 121 #define ISP_FREQ_STAT_OFFSET 0x18 122 #define ISP_REQ_GUAR_FREQ_OFFSET 0x8 123 #define ISP_REQ_FREQ_OFFSET 0x0 124 #define ISP_FREQ_VALID_OFFSET 0x7 125 #define ISP_FREQ_RULE_ANY 0x0 126 127 #define ISP_FREQ_457MHZ 0x1C9 128 #define ISP_FREQ_400MHZ 0x190 129 #define ISP_FREQ_356MHZ 0x164 130 #define ISP_FREQ_320MHZ 0x140 131 #define ISP_FREQ_266MHZ 0x10a 132 #define ISP_FREQ_200MHZ 0xc8 133 #define ISP_FREQ_100MHZ 0x64 134 135 #define HPLL_FREQ_800MHZ 0x320 136 #define HPLL_FREQ_1600MHZ 0x640 137 #define HPLL_FREQ_2000MHZ 0x7D0 138 139 #define CCK_FUSE_REG_0 0x08 140 #define CCK_FUSE_HPLL_FREQ_MASK 0x03 141 142 /* ISP2401 CSI2+ receiver delay settings */ 143 #define CSI2_PORT_A_BASE 0xC0000 144 #define CSI2_PORT_B_BASE 0xC2000 145 #define CSI2_PORT_C_BASE 0xC4000 146 147 #define CSI2_LANE_CL_BASE 0x418 148 #define CSI2_LANE_D0_BASE 0x420 149 #define CSI2_LANE_D1_BASE 0x428 150 #define CSI2_LANE_D2_BASE 0x430 151 #define CSI2_LANE_D3_BASE 0x438 152 153 #define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0 154 #define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4 155 156 #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418 157 #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C 158 #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420 159 #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424 160 #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428 161 #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C 162 #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430 163 #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434 164 #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438 165 #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C 166 167 #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418 168 #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C 169 #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420 170 #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424 171 #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428 172 #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C 173 174 #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418 175 #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C 176 #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420 177 #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424 178 #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428 179 #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C 180 181 #define DMA_BURST_SIZE_REG 0xCD408 182 183 #define ISP_DFS_TRY_TIMES 2 184 185 #endif /* ATOMISP_REGS_H */ 186