1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __ARCH_ROMSTAGE_H__ 4 #define __ARCH_ROMSTAGE_H__ 5 6 #include <stddef.h> 7 #include <stdint.h> 8 #include <cpu/x86/mtrr.h> 9 10 void mainboard_romstage_entry(void); 11 12 /* 13 * Support setting up a stack frame consisting of MTRR information 14 * for use in bootstrapping the caching attributes after cache-as-ram 15 * is torn down. 16 */ 17 18 struct postcar_frame { 19 int skip_common_mtrr; 20 struct var_mtrr_context *mtrr; 21 }; 22 23 /* 24 * Add variable MTRR covering the provided range with MTRR type. 25 */ 26 void postcar_frame_add_mtrr(struct postcar_frame *pcf, 27 uintptr_t addr, size_t size, int type); 28 29 /* 30 * Add variable MTRR covering the memory-mapped ROM with given MTRR type. 31 */ 32 void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); 33 34 /* 35 * fill_postcar_frame() is called after raminit completes and right before 36 * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() 37 * to tag memory ranges as cacheable to speed up execution of postcar and 38 * early ramstage. 39 */ 40 void fill_postcar_frame(struct postcar_frame *pcf); 41 42 /* 43 * prepare_and_run_postcar() determines the stack to use after 44 * cache-as-ram is torn down as well as the MTRR settings to use. 45 */ 46 void __noreturn prepare_and_run_postcar(void); 47 48 /* 49 * Systems without a native coreboot cache-as-ram teardown may implement 50 * this to use an alternate method. 51 */ 52 void late_car_teardown(void); 53 54 /* 55 * Cache the TSEG region at the top of ram. This region is 56 * not restricted to SMM mode until SMM has been relocated. 57 * By setting the region to cacheable it provides faster access 58 * when relocating the SMM handler as well as using the TSEG 59 * region for other purposes. 60 */ 61 void postcar_enable_tseg_cache(struct postcar_frame *pcf); 62 63 #endif /* __ARCH_ROMSTAGE_H__ */ 64