1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef ARCH_PIRQ_ROUTING_H 4 #define ARCH_PIRQ_ROUTING_H 5 6 /* This is the maximum number on interrupt entries that a PCI device may have. 7 * This is NOT the number of slots or devices in the system 8 * This is NOT the number of entries in the PIRQ table 9 * This tells us that in the PIRQ table, we are going to have 4 link-bitmap 10 * entries per PCI device 11 * It is fixed at 4: INTA, INTB, INTC, and INTD 12 * CAUTION: If you change this, pirq_routing will not work correctly */ 13 #define MAX_INTX_ENTRIES 4 14 15 #include <stdint.h> 16 17 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 18 #define PIRQ_VERSION 0x0100 19 20 struct irq_info { 21 u8 bus, devfn; /* Bus, device and function */ 22 struct { 23 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */ 24 u16 bitmap; /* Available IRQs */ 25 } __packed irq[4]; 26 u8 slot; /* Slot number, 0=onboard */ 27 u8 rfu; 28 } __packed; 29 30 struct irq_routing_table { 31 u32 signature; /* PIRQ_SIGNATURE should be here */ 32 u16 version; /* PIRQ_VERSION */ 33 u16 size; /* Table size in bytes */ 34 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ 35 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ 36 u16 rtr_vendor, rtr_device;/* Vendor/device ID of interrupt router */ 37 u32 miniport_data; 38 u8 rfu[11]; 39 u8 checksum; /* Modulo 256 checksum must give zero */ 40 struct irq_info slots[CONFIG_IRQ_SLOT_COUNT]; 41 } __packed; 42 43 unsigned long copy_pirq_routing_table(unsigned long addr, 44 const struct irq_routing_table *routing_table); 45 unsigned long write_pirq_routing_table(unsigned long start); 46 47 void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]); 48 49 #endif /* ARCH_PIRQ_ROUTING_H */ 50