1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sc7280.h> 21#include <dt-bindings/interrupt-controller/arm-gic.h> 22#include <dt-bindings/mailbox/qcom-ipcc.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sdm845-aoss.h> 26#include <dt-bindings/reset/qcom,sdm845-pdc.h> 27#include <dt-bindings/soc/qcom,apr.h> 28#include <dt-bindings/soc/qcom,rpmh-rsc.h> 29#include <dt-bindings/sound/qcom,lpass.h> 30#include <dt-bindings/thermal/thermal.h> 31 32/ { 33 interrupt-parent = <&intc>; 34 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 chosen { }; 39 40 aliases { 41 i2c0 = &i2c0; 42 i2c1 = &i2c1; 43 i2c2 = &i2c2; 44 i2c3 = &i2c3; 45 i2c4 = &i2c4; 46 i2c5 = &i2c5; 47 i2c6 = &i2c6; 48 i2c7 = &i2c7; 49 i2c8 = &i2c8; 50 i2c9 = &i2c9; 51 i2c10 = &i2c10; 52 i2c11 = &i2c11; 53 i2c12 = &i2c12; 54 i2c13 = &i2c13; 55 i2c14 = &i2c14; 56 i2c15 = &i2c15; 57 mmc1 = &sdhc_1; 58 mmc2 = &sdhc_2; 59 spi0 = &spi0; 60 spi1 = &spi1; 61 spi2 = &spi2; 62 spi3 = &spi3; 63 spi4 = &spi4; 64 spi5 = &spi5; 65 spi6 = &spi6; 66 spi7 = &spi7; 67 spi8 = &spi8; 68 spi9 = &spi9; 69 spi10 = &spi10; 70 spi11 = &spi11; 71 spi12 = &spi12; 72 spi13 = &spi13; 73 spi14 = &spi14; 74 spi15 = &spi15; 75 }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 clock-frequency = <76800000>; 81 #clock-cells = <0>; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 clock-frequency = <32764>; 87 #clock-cells = <0>; 88 }; 89 }; 90 91 reserved-memory { 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 wlan_ce_mem: wlan-ce@4cd000 { 97 no-map; 98 reg = <0x0 0x004cd000 0x0 0x1000>; 99 }; 100 101 hyp_mem: hyp@80000000 { 102 reg = <0x0 0x80000000 0x0 0x600000>; 103 no-map; 104 }; 105 106 xbl_mem: xbl@80600000 { 107 reg = <0x0 0x80600000 0x0 0x200000>; 108 no-map; 109 }; 110 111 aop_mem: aop@80800000 { 112 reg = <0x0 0x80800000 0x0 0x60000>; 113 no-map; 114 }; 115 116 aop_cmd_db_mem: aop-cmd-db@80860000 { 117 reg = <0x0 0x80860000 0x0 0x20000>; 118 compatible = "qcom,cmd-db"; 119 no-map; 120 }; 121 122 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 123 reg = <0x0 0x80884000 0x0 0x10000>; 124 no-map; 125 }; 126 127 sec_apps_mem: sec-apps@808ff000 { 128 reg = <0x0 0x808ff000 0x0 0x1000>; 129 no-map; 130 }; 131 132 smem_mem: smem@80900000 { 133 reg = <0x0 0x80900000 0x0 0x200000>; 134 no-map; 135 }; 136 137 cpucp_mem: cpucp@80b00000 { 138 no-map; 139 reg = <0x0 0x80b00000 0x0 0x100000>; 140 }; 141 142 wlan_fw_mem: wlan-fw@80c00000 { 143 reg = <0x0 0x80c00000 0x0 0xc00000>; 144 no-map; 145 }; 146 147 adsp_mem: adsp@86700000 { 148 reg = <0x0 0x86700000 0x0 0x2800000>; 149 no-map; 150 }; 151 152 video_mem: video@8b200000 { 153 reg = <0x0 0x8b200000 0x0 0x500000>; 154 no-map; 155 }; 156 157 cdsp_mem: cdsp@88f00000 { 158 reg = <0x0 0x88f00000 0x0 0x1e00000>; 159 no-map; 160 }; 161 162 ipa_fw_mem: ipa-fw@8b700000 { 163 reg = <0 0x8b700000 0 0x10000>; 164 no-map; 165 }; 166 167 gpu_zap_mem: zap@8b71a000 { 168 reg = <0 0x8b71a000 0 0x2000>; 169 no-map; 170 }; 171 172 mpss_mem: mpss@8b800000 { 173 reg = <0x0 0x8b800000 0x0 0xf600000>; 174 no-map; 175 }; 176 177 wpss_mem: wpss@9ae00000 { 178 reg = <0x0 0x9ae00000 0x0 0x1900000>; 179 no-map; 180 }; 181 182 rmtfs_mem: rmtfs@9c900000 { 183 compatible = "qcom,rmtfs-mem"; 184 reg = <0x0 0x9c900000 0x0 0x280000>; 185 no-map; 186 187 qcom,client-id = <1>; 188 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 189 }; 190 }; 191 192 cpus { 193 #address-cells = <2>; 194 #size-cells = <0>; 195 196 cpu0: cpu@0 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo"; 199 reg = <0x0 0x0>; 200 clocks = <&cpufreq_hw 0>; 201 enable-method = "psci"; 202 power-domains = <&cpu_pd0>; 203 power-domain-names = "psci"; 204 next-level-cache = <&l2_0>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <100>; 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 209 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 210 qcom,freq-domain = <&cpufreq_hw 0>; 211 #cooling-cells = <2>; 212 l2_0: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 l3_0: l3-cache { 218 compatible = "cache"; 219 cache-level = <3>; 220 cache-unified; 221 }; 222 }; 223 }; 224 225 cpu1: cpu@100 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo"; 228 reg = <0x0 0x100>; 229 clocks = <&cpufreq_hw 0>; 230 enable-method = "psci"; 231 power-domains = <&cpu_pd1>; 232 power-domain-names = "psci"; 233 next-level-cache = <&l2_100>; 234 operating-points-v2 = <&cpu0_opp_table>; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <100>; 237 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 238 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 l2_100: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_0>; 246 }; 247 }; 248 249 cpu2: cpu@200 { 250 device_type = "cpu"; 251 compatible = "qcom,kryo"; 252 reg = <0x0 0x200>; 253 clocks = <&cpufreq_hw 0>; 254 enable-method = "psci"; 255 power-domains = <&cpu_pd2>; 256 power-domain-names = "psci"; 257 next-level-cache = <&l2_200>; 258 operating-points-v2 = <&cpu0_opp_table>; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <100>; 261 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 262 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 263 qcom,freq-domain = <&cpufreq_hw 0>; 264 #cooling-cells = <2>; 265 l2_200: l2-cache { 266 compatible = "cache"; 267 cache-level = <2>; 268 cache-unified; 269 next-level-cache = <&l3_0>; 270 }; 271 }; 272 273 cpu3: cpu@300 { 274 device_type = "cpu"; 275 compatible = "qcom,kryo"; 276 reg = <0x0 0x300>; 277 clocks = <&cpufreq_hw 0>; 278 enable-method = "psci"; 279 power-domains = <&cpu_pd3>; 280 power-domain-names = "psci"; 281 next-level-cache = <&l2_300>; 282 operating-points-v2 = <&cpu0_opp_table>; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <100>; 285 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 286 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 287 qcom,freq-domain = <&cpufreq_hw 0>; 288 #cooling-cells = <2>; 289 l2_300: l2-cache { 290 compatible = "cache"; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&l3_0>; 294 }; 295 }; 296 297 cpu4: cpu@400 { 298 device_type = "cpu"; 299 compatible = "qcom,kryo"; 300 reg = <0x0 0x400>; 301 clocks = <&cpufreq_hw 1>; 302 enable-method = "psci"; 303 power-domains = <&cpu_pd4>; 304 power-domain-names = "psci"; 305 next-level-cache = <&l2_400>; 306 operating-points-v2 = <&cpu4_opp_table>; 307 capacity-dmips-mhz = <1946>; 308 dynamic-power-coefficient = <520>; 309 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 310 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 311 qcom,freq-domain = <&cpufreq_hw 1>; 312 #cooling-cells = <2>; 313 l2_400: l2-cache { 314 compatible = "cache"; 315 cache-level = <2>; 316 cache-unified; 317 next-level-cache = <&l3_0>; 318 }; 319 }; 320 321 cpu5: cpu@500 { 322 device_type = "cpu"; 323 compatible = "qcom,kryo"; 324 reg = <0x0 0x500>; 325 clocks = <&cpufreq_hw 1>; 326 enable-method = "psci"; 327 power-domains = <&cpu_pd5>; 328 power-domain-names = "psci"; 329 next-level-cache = <&l2_500>; 330 operating-points-v2 = <&cpu4_opp_table>; 331 capacity-dmips-mhz = <1946>; 332 dynamic-power-coefficient = <520>; 333 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 334 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 335 qcom,freq-domain = <&cpufreq_hw 1>; 336 #cooling-cells = <2>; 337 l2_500: l2-cache { 338 compatible = "cache"; 339 cache-level = <2>; 340 cache-unified; 341 next-level-cache = <&l3_0>; 342 }; 343 }; 344 345 cpu6: cpu@600 { 346 device_type = "cpu"; 347 compatible = "qcom,kryo"; 348 reg = <0x0 0x600>; 349 clocks = <&cpufreq_hw 1>; 350 enable-method = "psci"; 351 power-domains = <&cpu_pd6>; 352 power-domain-names = "psci"; 353 next-level-cache = <&l2_600>; 354 operating-points-v2 = <&cpu4_opp_table>; 355 capacity-dmips-mhz = <1946>; 356 dynamic-power-coefficient = <520>; 357 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 358 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 359 qcom,freq-domain = <&cpufreq_hw 1>; 360 #cooling-cells = <2>; 361 l2_600: l2-cache { 362 compatible = "cache"; 363 cache-level = <2>; 364 cache-unified; 365 next-level-cache = <&l3_0>; 366 }; 367 }; 368 369 cpu7: cpu@700 { 370 device_type = "cpu"; 371 compatible = "qcom,kryo"; 372 reg = <0x0 0x700>; 373 clocks = <&cpufreq_hw 2>; 374 enable-method = "psci"; 375 power-domains = <&cpu_pd7>; 376 power-domain-names = "psci"; 377 next-level-cache = <&l2_700>; 378 operating-points-v2 = <&cpu7_opp_table>; 379 capacity-dmips-mhz = <1985>; 380 dynamic-power-coefficient = <552>; 381 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 382 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 383 qcom,freq-domain = <&cpufreq_hw 2>; 384 #cooling-cells = <2>; 385 l2_700: l2-cache { 386 compatible = "cache"; 387 cache-level = <2>; 388 cache-unified; 389 next-level-cache = <&l3_0>; 390 }; 391 }; 392 393 cpu-map { 394 cluster0 { 395 core0 { 396 cpu = <&cpu0>; 397 }; 398 399 core1 { 400 cpu = <&cpu1>; 401 }; 402 403 core2 { 404 cpu = <&cpu2>; 405 }; 406 407 core3 { 408 cpu = <&cpu3>; 409 }; 410 411 core4 { 412 cpu = <&cpu4>; 413 }; 414 415 core5 { 416 cpu = <&cpu5>; 417 }; 418 419 core6 { 420 cpu = <&cpu6>; 421 }; 422 423 core7 { 424 cpu = <&cpu7>; 425 }; 426 }; 427 }; 428 429 idle-states { 430 entry-method = "psci"; 431 432 little_cpu_sleep_0: cpu-sleep-0-0 { 433 compatible = "arm,idle-state"; 434 idle-state-name = "little-power-down"; 435 arm,psci-suspend-param = <0x40000003>; 436 entry-latency-us = <549>; 437 exit-latency-us = <901>; 438 min-residency-us = <1774>; 439 local-timer-stop; 440 }; 441 442 little_cpu_sleep_1: cpu-sleep-0-1 { 443 compatible = "arm,idle-state"; 444 idle-state-name = "little-rail-power-down"; 445 arm,psci-suspend-param = <0x40000004>; 446 entry-latency-us = <702>; 447 exit-latency-us = <915>; 448 min-residency-us = <4001>; 449 local-timer-stop; 450 }; 451 452 big_cpu_sleep_0: cpu-sleep-1-0 { 453 compatible = "arm,idle-state"; 454 idle-state-name = "big-power-down"; 455 arm,psci-suspend-param = <0x40000003>; 456 entry-latency-us = <523>; 457 exit-latency-us = <1244>; 458 min-residency-us = <2207>; 459 local-timer-stop; 460 }; 461 462 big_cpu_sleep_1: cpu-sleep-1-1 { 463 compatible = "arm,idle-state"; 464 idle-state-name = "big-rail-power-down"; 465 arm,psci-suspend-param = <0x40000004>; 466 entry-latency-us = <526>; 467 exit-latency-us = <1854>; 468 min-residency-us = <5555>; 469 local-timer-stop; 470 }; 471 }; 472 473 domain_idle_states: domain-idle-states { 474 cluster_sleep_apss_off: cluster-sleep-0 { 475 compatible = "domain-idle-state"; 476 arm,psci-suspend-param = <0x41000044>; 477 entry-latency-us = <2752>; 478 exit-latency-us = <3048>; 479 min-residency-us = <6118>; 480 }; 481 482 cluster_sleep_cx_ret: cluster-sleep-1 { 483 compatible = "domain-idle-state"; 484 arm,psci-suspend-param = <0x41001344>; 485 entry-latency-us = <3263>; 486 exit-latency-us = <4562>; 487 min-residency-us = <8467>; 488 }; 489 490 cluster_sleep_llcc_off: cluster-sleep-2 { 491 compatible = "domain-idle-state"; 492 arm,psci-suspend-param = <0x4100b344>; 493 entry-latency-us = <3638>; 494 exit-latency-us = <6562>; 495 min-residency-us = <9826>; 496 }; 497 }; 498 }; 499 500 cpu0_opp_table: opp-table-cpu0 { 501 compatible = "operating-points-v2"; 502 opp-shared; 503 504 cpu0_opp_300mhz: opp-300000000 { 505 opp-hz = /bits/ 64 <300000000>; 506 opp-peak-kBps = <800000 9600000>; 507 }; 508 509 cpu0_opp_691mhz: opp-691200000 { 510 opp-hz = /bits/ 64 <691200000>; 511 opp-peak-kBps = <800000 17817600>; 512 }; 513 514 cpu0_opp_806mhz: opp-806400000 { 515 opp-hz = /bits/ 64 <806400000>; 516 opp-peak-kBps = <800000 20889600>; 517 }; 518 519 cpu0_opp_941mhz: opp-940800000 { 520 opp-hz = /bits/ 64 <940800000>; 521 opp-peak-kBps = <1804000 24576000>; 522 }; 523 524 cpu0_opp_1152mhz: opp-1152000000 { 525 opp-hz = /bits/ 64 <1152000000>; 526 opp-peak-kBps = <2188000 27033600>; 527 }; 528 529 cpu0_opp_1325mhz: opp-1324800000 { 530 opp-hz = /bits/ 64 <1324800000>; 531 opp-peak-kBps = <2188000 33792000>; 532 }; 533 534 cpu0_opp_1517mhz: opp-1516800000 { 535 opp-hz = /bits/ 64 <1516800000>; 536 opp-peak-kBps = <3072000 38092800>; 537 }; 538 539 cpu0_opp_1651mhz: opp-1651200000 { 540 opp-hz = /bits/ 64 <1651200000>; 541 opp-peak-kBps = <3072000 41779200>; 542 }; 543 544 cpu0_opp_1805mhz: opp-1804800000 { 545 opp-hz = /bits/ 64 <1804800000>; 546 opp-peak-kBps = <4068000 48537600>; 547 }; 548 549 cpu0_opp_1958mhz: opp-1958400000 { 550 opp-hz = /bits/ 64 <1958400000>; 551 opp-peak-kBps = <4068000 48537600>; 552 }; 553 554 cpu0_opp_2016mhz: opp-2016000000 { 555 opp-hz = /bits/ 64 <2016000000>; 556 opp-peak-kBps = <6220000 48537600>; 557 }; 558 }; 559 560 cpu4_opp_table: opp-table-cpu4 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 cpu4_opp_691mhz: opp-691200000 { 565 opp-hz = /bits/ 64 <691200000>; 566 opp-peak-kBps = <1804000 9600000>; 567 }; 568 569 cpu4_opp_941mhz: opp-940800000 { 570 opp-hz = /bits/ 64 <940800000>; 571 opp-peak-kBps = <2188000 17817600>; 572 }; 573 574 cpu4_opp_1229mhz: opp-1228800000 { 575 opp-hz = /bits/ 64 <1228800000>; 576 opp-peak-kBps = <4068000 24576000>; 577 }; 578 579 cpu4_opp_1344mhz: opp-1344000000 { 580 opp-hz = /bits/ 64 <1344000000>; 581 opp-peak-kBps = <4068000 24576000>; 582 }; 583 584 cpu4_opp_1517mhz: opp-1516800000 { 585 opp-hz = /bits/ 64 <1516800000>; 586 opp-peak-kBps = <4068000 24576000>; 587 }; 588 589 cpu4_opp_1651mhz: opp-1651200000 { 590 opp-hz = /bits/ 64 <1651200000>; 591 opp-peak-kBps = <6220000 38092800>; 592 }; 593 594 cpu4_opp_1901mhz: opp-1900800000 { 595 opp-hz = /bits/ 64 <1900800000>; 596 opp-peak-kBps = <6220000 44851200>; 597 }; 598 599 cpu4_opp_2054mhz: opp-2054400000 { 600 opp-hz = /bits/ 64 <2054400000>; 601 opp-peak-kBps = <6220000 44851200>; 602 }; 603 604 cpu4_opp_2112mhz: opp-2112000000 { 605 opp-hz = /bits/ 64 <2112000000>; 606 opp-peak-kBps = <6220000 44851200>; 607 }; 608 609 cpu4_opp_2131mhz: opp-2131200000 { 610 opp-hz = /bits/ 64 <2131200000>; 611 opp-peak-kBps = <6220000 44851200>; 612 }; 613 614 cpu4_opp_2208mhz: opp-2208000000 { 615 opp-hz = /bits/ 64 <2208000000>; 616 opp-peak-kBps = <6220000 44851200>; 617 }; 618 619 cpu4_opp_2400mhz: opp-2400000000 { 620 opp-hz = /bits/ 64 <2400000000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 624 cpu4_opp_2611mhz: opp-2611200000 { 625 opp-hz = /bits/ 64 <2611200000>; 626 opp-peak-kBps = <8532000 48537600>; 627 }; 628 }; 629 630 cpu7_opp_table: opp-table-cpu7 { 631 compatible = "operating-points-v2"; 632 opp-shared; 633 634 cpu7_opp_806mhz: opp-806400000 { 635 opp-hz = /bits/ 64 <806400000>; 636 opp-peak-kBps = <1804000 9600000>; 637 }; 638 639 cpu7_opp_1056mhz: opp-1056000000 { 640 opp-hz = /bits/ 64 <1056000000>; 641 opp-peak-kBps = <2188000 17817600>; 642 }; 643 644 cpu7_opp_1325mhz: opp-1324800000 { 645 opp-hz = /bits/ 64 <1324800000>; 646 opp-peak-kBps = <4068000 24576000>; 647 }; 648 649 cpu7_opp_1517mhz: opp-1516800000 { 650 opp-hz = /bits/ 64 <1516800000>; 651 opp-peak-kBps = <4068000 24576000>; 652 }; 653 654 cpu7_opp_1766mhz: opp-1766400000 { 655 opp-hz = /bits/ 64 <1766400000>; 656 opp-peak-kBps = <6220000 38092800>; 657 }; 658 659 cpu7_opp_1862mhz: opp-1862400000 { 660 opp-hz = /bits/ 64 <1862400000>; 661 opp-peak-kBps = <6220000 38092800>; 662 }; 663 664 cpu7_opp_2035mhz: opp-2035200000 { 665 opp-hz = /bits/ 64 <2035200000>; 666 opp-peak-kBps = <6220000 38092800>; 667 }; 668 669 cpu7_opp_2112mhz: opp-2112000000 { 670 opp-hz = /bits/ 64 <2112000000>; 671 opp-peak-kBps = <6220000 44851200>; 672 }; 673 674 cpu7_opp_2208mhz: opp-2208000000 { 675 opp-hz = /bits/ 64 <2208000000>; 676 opp-peak-kBps = <6220000 44851200>; 677 }; 678 679 cpu7_opp_2381mhz: opp-2380800000 { 680 opp-hz = /bits/ 64 <2380800000>; 681 opp-peak-kBps = <6832000 44851200>; 682 }; 683 684 cpu7_opp_2400mhz: opp-2400000000 { 685 opp-hz = /bits/ 64 <2400000000>; 686 opp-peak-kBps = <8532000 48537600>; 687 }; 688 689 cpu7_opp_2515mhz: opp-2515200000 { 690 opp-hz = /bits/ 64 <2515200000>; 691 opp-peak-kBps = <8532000 48537600>; 692 }; 693 694 cpu7_opp_2707mhz: opp-2707200000 { 695 opp-hz = /bits/ 64 <2707200000>; 696 opp-peak-kBps = <8532000 48537600>; 697 }; 698 699 cpu7_opp_3014mhz: opp-3014400000 { 700 opp-hz = /bits/ 64 <3014400000>; 701 opp-peak-kBps = <8532000 48537600>; 702 }; 703 }; 704 705 memory@80000000 { 706 device_type = "memory"; 707 /* We expect the bootloader to fill in the size */ 708 reg = <0 0x80000000 0 0>; 709 }; 710 711 firmware { 712 scm: scm { 713 compatible = "qcom,scm-sc7280", "qcom,scm"; 714 qcom,dload-mode = <&tcsr_2 0x13000>; 715 }; 716 }; 717 718 clk_virt: interconnect { 719 compatible = "qcom,sc7280-clk-virt"; 720 #interconnect-cells = <2>; 721 qcom,bcm-voters = <&apps_bcm_voter>; 722 }; 723 724 smem { 725 compatible = "qcom,smem"; 726 memory-region = <&smem_mem>; 727 hwlocks = <&tcsr_mutex 3>; 728 }; 729 730 smp2p-adsp { 731 compatible = "qcom,smp2p"; 732 qcom,smem = <443>, <429>; 733 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 734 IPCC_MPROC_SIGNAL_SMP2P 735 IRQ_TYPE_EDGE_RISING>; 736 mboxes = <&ipcc IPCC_CLIENT_LPASS 737 IPCC_MPROC_SIGNAL_SMP2P>; 738 739 qcom,local-pid = <0>; 740 qcom,remote-pid = <2>; 741 742 adsp_smp2p_out: master-kernel { 743 qcom,entry-name = "master-kernel"; 744 #qcom,smem-state-cells = <1>; 745 }; 746 747 adsp_smp2p_in: slave-kernel { 748 qcom,entry-name = "slave-kernel"; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 }; 752 }; 753 754 smp2p-cdsp { 755 compatible = "qcom,smp2p"; 756 qcom,smem = <94>, <432>; 757 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 758 IPCC_MPROC_SIGNAL_SMP2P 759 IRQ_TYPE_EDGE_RISING>; 760 mboxes = <&ipcc IPCC_CLIENT_CDSP 761 IPCC_MPROC_SIGNAL_SMP2P>; 762 763 qcom,local-pid = <0>; 764 qcom,remote-pid = <5>; 765 766 cdsp_smp2p_out: master-kernel { 767 qcom,entry-name = "master-kernel"; 768 #qcom,smem-state-cells = <1>; 769 }; 770 771 cdsp_smp2p_in: slave-kernel { 772 qcom,entry-name = "slave-kernel"; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 }; 776 }; 777 778 smp2p-mpss { 779 compatible = "qcom,smp2p"; 780 qcom,smem = <435>, <428>; 781 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 782 IPCC_MPROC_SIGNAL_SMP2P 783 IRQ_TYPE_EDGE_RISING>; 784 mboxes = <&ipcc IPCC_CLIENT_MPSS 785 IPCC_MPROC_SIGNAL_SMP2P>; 786 787 qcom,local-pid = <0>; 788 qcom,remote-pid = <1>; 789 790 modem_smp2p_out: master-kernel { 791 qcom,entry-name = "master-kernel"; 792 #qcom,smem-state-cells = <1>; 793 }; 794 795 modem_smp2p_in: slave-kernel { 796 qcom,entry-name = "slave-kernel"; 797 interrupt-controller; 798 #interrupt-cells = <2>; 799 }; 800 801 ipa_smp2p_out: ipa-ap-to-modem { 802 qcom,entry-name = "ipa"; 803 #qcom,smem-state-cells = <1>; 804 }; 805 806 ipa_smp2p_in: ipa-modem-to-ap { 807 qcom,entry-name = "ipa"; 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 }; 811 }; 812 813 smp2p-wpss { 814 compatible = "qcom,smp2p"; 815 qcom,smem = <617>, <616>; 816 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 817 IPCC_MPROC_SIGNAL_SMP2P 818 IRQ_TYPE_EDGE_RISING>; 819 mboxes = <&ipcc IPCC_CLIENT_WPSS 820 IPCC_MPROC_SIGNAL_SMP2P>; 821 822 qcom,local-pid = <0>; 823 qcom,remote-pid = <13>; 824 825 wpss_smp2p_out: master-kernel { 826 qcom,entry-name = "master-kernel"; 827 #qcom,smem-state-cells = <1>; 828 }; 829 830 wpss_smp2p_in: slave-kernel { 831 qcom,entry-name = "slave-kernel"; 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 }; 835 836 wlan_smp2p_out: wlan-ap-to-wpss { 837 qcom,entry-name = "wlan"; 838 #qcom,smem-state-cells = <1>; 839 }; 840 841 wlan_smp2p_in: wlan-wpss-to-ap { 842 qcom,entry-name = "wlan"; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 }; 847 848 pmu-a55 { 849 compatible = "arm,cortex-a55-pmu"; 850 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 851 }; 852 853 pmu-a78 { 854 compatible = "arm,cortex-a78-pmu"; 855 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 856 }; 857 858 psci { 859 compatible = "arm,psci-1.0"; 860 method = "smc"; 861 862 cpu_pd0: power-domain-cpu0 { 863 #power-domain-cells = <0>; 864 power-domains = <&cluster_pd>; 865 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 866 }; 867 868 cpu_pd1: power-domain-cpu1 { 869 #power-domain-cells = <0>; 870 power-domains = <&cluster_pd>; 871 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 872 }; 873 874 cpu_pd2: power-domain-cpu2 { 875 #power-domain-cells = <0>; 876 power-domains = <&cluster_pd>; 877 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 878 }; 879 880 cpu_pd3: power-domain-cpu3 { 881 #power-domain-cells = <0>; 882 power-domains = <&cluster_pd>; 883 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 884 }; 885 886 cpu_pd4: power-domain-cpu4 { 887 #power-domain-cells = <0>; 888 power-domains = <&cluster_pd>; 889 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 890 }; 891 892 cpu_pd5: power-domain-cpu5 { 893 #power-domain-cells = <0>; 894 power-domains = <&cluster_pd>; 895 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 896 }; 897 898 cpu_pd6: power-domain-cpu6 { 899 #power-domain-cells = <0>; 900 power-domains = <&cluster_pd>; 901 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 902 }; 903 904 cpu_pd7: power-domain-cpu7 { 905 #power-domain-cells = <0>; 906 power-domains = <&cluster_pd>; 907 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 908 }; 909 910 cluster_pd: power-domain-cluster { 911 #power-domain-cells = <0>; 912 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 913 }; 914 }; 915 916 qspi_opp_table: opp-table-qspi { 917 compatible = "operating-points-v2"; 918 919 opp-75000000 { 920 opp-hz = /bits/ 64 <75000000>; 921 required-opps = <&rpmhpd_opp_low_svs>; 922 }; 923 924 opp-150000000 { 925 opp-hz = /bits/ 64 <150000000>; 926 required-opps = <&rpmhpd_opp_svs>; 927 }; 928 929 opp-200000000 { 930 opp-hz = /bits/ 64 <200000000>; 931 required-opps = <&rpmhpd_opp_svs_l1>; 932 }; 933 934 opp-300000000 { 935 opp-hz = /bits/ 64 <300000000>; 936 required-opps = <&rpmhpd_opp_nom>; 937 }; 938 }; 939 940 qup_opp_table: opp-table-qup { 941 compatible = "operating-points-v2"; 942 943 opp-75000000 { 944 opp-hz = /bits/ 64 <75000000>; 945 required-opps = <&rpmhpd_opp_low_svs>; 946 }; 947 948 opp-100000000 { 949 opp-hz = /bits/ 64 <100000000>; 950 required-opps = <&rpmhpd_opp_svs>; 951 }; 952 953 opp-128000000 { 954 opp-hz = /bits/ 64 <128000000>; 955 required-opps = <&rpmhpd_opp_nom>; 956 }; 957 }; 958 959 soc: soc@0 { 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges = <0 0 0 0 0x10 0>; 963 dma-ranges = <0 0 0 0 0x10 0>; 964 compatible = "simple-bus"; 965 966 gcc: clock-controller@100000 { 967 compatible = "qcom,gcc-sc7280"; 968 reg = <0 0x00100000 0 0x1f0000>; 969 clocks = <&rpmhcc RPMH_CXO_CLK>, 970 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 971 <0>, <&pcie1_phy>, 972 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 973 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 974 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 975 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 976 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 977 "ufs_phy_tx_symbol_0_clk", 978 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 979 #clock-cells = <1>; 980 #reset-cells = <1>; 981 #power-domain-cells = <1>; 982 power-domains = <&rpmhpd SC7280_CX>; 983 }; 984 985 ipcc: mailbox@408000 { 986 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 987 reg = <0 0x00408000 0 0x1000>; 988 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 989 interrupt-controller; 990 #interrupt-cells = <3>; 991 #mbox-cells = <2>; 992 }; 993 994 qfprom: efuse@784000 { 995 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 996 reg = <0 0x00784000 0 0xa20>, 997 <0 0x00780000 0 0xa20>, 998 <0 0x00782000 0 0x120>, 999 <0 0x00786000 0 0x1fff>; 1000 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1001 clock-names = "core"; 1002 power-domains = <&rpmhpd SC7280_MX>; 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 1006 gpu_speed_bin: gpu-speed-bin@1e9 { 1007 reg = <0x1e9 0x2>; 1008 bits = <5 8>; 1009 }; 1010 }; 1011 1012 sdhc_1: mmc@7c4000 { 1013 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1014 pinctrl-names = "default", "sleep"; 1015 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1016 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1017 status = "disabled"; 1018 1019 reg = <0 0x007c4000 0 0x1000>, 1020 <0 0x007c5000 0 0x1000>; 1021 reg-names = "hc", "cqhci"; 1022 1023 iommus = <&apps_smmu 0xc0 0x0>; 1024 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1026 interrupt-names = "hc_irq", "pwr_irq"; 1027 1028 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1029 <&gcc GCC_SDCC1_APPS_CLK>, 1030 <&rpmhcc RPMH_CXO_CLK>; 1031 clock-names = "iface", "core", "xo"; 1032 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1033 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1034 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1035 power-domains = <&rpmhpd SC7280_CX>; 1036 operating-points-v2 = <&sdhc1_opp_table>; 1037 1038 bus-width = <8>; 1039 supports-cqe; 1040 dma-coherent; 1041 1042 qcom,dll-config = <0x0007642c>; 1043 qcom,ddr-config = <0x80040868>; 1044 1045 mmc-ddr-1_8v; 1046 mmc-hs200-1_8v; 1047 mmc-hs400-1_8v; 1048 mmc-hs400-enhanced-strobe; 1049 1050 resets = <&gcc GCC_SDCC1_BCR>; 1051 1052 sdhc1_opp_table: opp-table { 1053 compatible = "operating-points-v2"; 1054 1055 opp-100000000 { 1056 opp-hz = /bits/ 64 <100000000>; 1057 required-opps = <&rpmhpd_opp_low_svs>; 1058 opp-peak-kBps = <1800000 400000>; 1059 opp-avg-kBps = <100000 0>; 1060 }; 1061 1062 opp-384000000 { 1063 opp-hz = /bits/ 64 <384000000>; 1064 required-opps = <&rpmhpd_opp_nom>; 1065 opp-peak-kBps = <5400000 1600000>; 1066 opp-avg-kBps = <390000 0>; 1067 }; 1068 }; 1069 }; 1070 1071 gpi_dma0: dma-controller@900000 { 1072 #dma-cells = <3>; 1073 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1074 reg = <0 0x00900000 0 0x60000>; 1075 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1087 dma-channels = <12>; 1088 dma-channel-mask = <0x7f>; 1089 iommus = <&apps_smmu 0x0136 0x0>; 1090 status = "disabled"; 1091 }; 1092 1093 qupv3_id_0: geniqup@9c0000 { 1094 compatible = "qcom,geni-se-qup"; 1095 reg = <0 0x009c0000 0 0x2000>; 1096 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1097 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1098 clock-names = "m-ahb", "s-ahb"; 1099 #address-cells = <2>; 1100 #size-cells = <2>; 1101 ranges; 1102 iommus = <&apps_smmu 0x123 0x0>; 1103 status = "disabled"; 1104 1105 i2c0: i2c@980000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0 0x00980000 0 0x4000>; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1109 clock-names = "se"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_i2c0_data_clk>; 1112 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1117 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1118 interconnect-names = "qup-core", "qup-config", 1119 "qup-memory"; 1120 power-domains = <&rpmhpd SC7280_CX>; 1121 required-opps = <&rpmhpd_opp_low_svs>; 1122 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 status = "disabled"; 1126 }; 1127 1128 spi0: spi@980000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00980000 0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1132 clock-names = "se"; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1135 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1144 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1145 dma-names = "tx", "rx"; 1146 status = "disabled"; 1147 }; 1148 1149 uart0: serial@980000 { 1150 compatible = "qcom,geni-uart"; 1151 reg = <0 0x00980000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1153 clock-names = "se"; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1156 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1157 power-domains = <&rpmhpd SC7280_CX>; 1158 operating-points-v2 = <&qup_opp_table>; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1160 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1161 interconnect-names = "qup-core", "qup-config"; 1162 status = "disabled"; 1163 }; 1164 1165 i2c1: i2c@984000 { 1166 compatible = "qcom,geni-i2c"; 1167 reg = <0 0x00984000 0 0x4000>; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1169 clock-names = "se"; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_i2c1_data_clk>; 1172 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1176 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1177 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1178 interconnect-names = "qup-core", "qup-config", 1179 "qup-memory"; 1180 power-domains = <&rpmhpd SC7280_CX>; 1181 required-opps = <&rpmhpd_opp_low_svs>; 1182 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1183 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1184 dma-names = "tx", "rx"; 1185 status = "disabled"; 1186 }; 1187 1188 spi1: spi@984000 { 1189 compatible = "qcom,geni-spi"; 1190 reg = <0 0x00984000 0 0x4000>; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1192 clock-names = "se"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1195 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1204 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart1: serial@984000 { 1210 compatible = "qcom,geni-uart"; 1211 reg = <0 0x00984000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1213 clock-names = "se"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1216 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1217 power-domains = <&rpmhpd SC7280_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 status = "disabled"; 1223 }; 1224 1225 i2c2: i2c@988000 { 1226 compatible = "qcom,geni-i2c"; 1227 reg = <0 0x00988000 0 0x4000>; 1228 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1229 clock-names = "se"; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_i2c2_data_clk>; 1232 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1236 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1237 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1238 interconnect-names = "qup-core", "qup-config", 1239 "qup-memory"; 1240 power-domains = <&rpmhpd SC7280_CX>; 1241 required-opps = <&rpmhpd_opp_low_svs>; 1242 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1243 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1244 dma-names = "tx", "rx"; 1245 status = "disabled"; 1246 }; 1247 1248 spi2: spi@988000 { 1249 compatible = "qcom,geni-spi"; 1250 reg = <0 0x00988000 0 0x4000>; 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1252 clock-names = "se"; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1255 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1264 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1265 dma-names = "tx", "rx"; 1266 status = "disabled"; 1267 }; 1268 1269 uart2: serial@988000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00988000 0 0x4000>; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1273 clock-names = "se"; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1276 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1277 power-domains = <&rpmhpd SC7280_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1280 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 status = "disabled"; 1283 }; 1284 1285 i2c3: i2c@98c000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x0098c000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c3_data_clk>; 1292 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1297 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1298 interconnect-names = "qup-core", "qup-config", 1299 "qup-memory"; 1300 power-domains = <&rpmhpd SC7280_CX>; 1301 required-opps = <&rpmhpd_opp_low_svs>; 1302 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1303 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1304 dma-names = "tx", "rx"; 1305 status = "disabled"; 1306 }; 1307 1308 spi3: spi@98c000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0 0x0098c000 0 0x4000>; 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1312 clock-names = "se"; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1315 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1324 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1325 dma-names = "tx", "rx"; 1326 status = "disabled"; 1327 }; 1328 1329 uart3: serial@98c000 { 1330 compatible = "qcom,geni-uart"; 1331 reg = <0 0x0098c000 0 0x4000>; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1333 clock-names = "se"; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1336 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1337 power-domains = <&rpmhpd SC7280_CX>; 1338 operating-points-v2 = <&qup_opp_table>; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1340 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1341 interconnect-names = "qup-core", "qup-config"; 1342 status = "disabled"; 1343 }; 1344 1345 i2c4: i2c@990000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00990000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1349 clock-names = "se"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_i2c4_data_clk>; 1352 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1357 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1358 interconnect-names = "qup-core", "qup-config", 1359 "qup-memory"; 1360 power-domains = <&rpmhpd SC7280_CX>; 1361 required-opps = <&rpmhpd_opp_low_svs>; 1362 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1363 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1364 dma-names = "tx", "rx"; 1365 status = "disabled"; 1366 }; 1367 1368 spi4: spi@990000 { 1369 compatible = "qcom,geni-spi"; 1370 reg = <0 0x00990000 0 0x4000>; 1371 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1372 clock-names = "se"; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1375 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1384 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1385 dma-names = "tx", "rx"; 1386 status = "disabled"; 1387 }; 1388 1389 uart4: serial@990000 { 1390 compatible = "qcom,geni-uart"; 1391 reg = <0 0x00990000 0 0x4000>; 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1393 clock-names = "se"; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1396 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1397 power-domains = <&rpmhpd SC7280_CX>; 1398 operating-points-v2 = <&qup_opp_table>; 1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1400 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1401 interconnect-names = "qup-core", "qup-config"; 1402 status = "disabled"; 1403 }; 1404 1405 i2c5: i2c@994000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0 0x00994000 0 0x4000>; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1409 clock-names = "se"; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_i2c5_data_clk>; 1412 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1417 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1418 interconnect-names = "qup-core", "qup-config", 1419 "qup-memory"; 1420 power-domains = <&rpmhpd SC7280_CX>; 1421 required-opps = <&rpmhpd_opp_low_svs>; 1422 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1423 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1424 dma-names = "tx", "rx"; 1425 status = "disabled"; 1426 }; 1427 1428 spi5: spi@994000 { 1429 compatible = "qcom,geni-spi"; 1430 reg = <0 0x00994000 0 0x4000>; 1431 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1432 clock-names = "se"; 1433 pinctrl-names = "default"; 1434 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1435 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1444 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1445 dma-names = "tx", "rx"; 1446 status = "disabled"; 1447 }; 1448 1449 uart5: serial@994000 { 1450 compatible = "qcom,geni-debug-uart"; 1451 reg = <0 0x00994000 0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1453 clock-names = "se"; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1456 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1457 power-domains = <&rpmhpd SC7280_CX>; 1458 operating-points-v2 = <&qup_opp_table>; 1459 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1460 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1461 interconnect-names = "qup-core", "qup-config"; 1462 status = "disabled"; 1463 }; 1464 1465 i2c6: i2c@998000 { 1466 compatible = "qcom,geni-i2c"; 1467 reg = <0 0x00998000 0 0x4000>; 1468 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1469 clock-names = "se"; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&qup_i2c6_data_clk>; 1472 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1476 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1477 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1478 interconnect-names = "qup-core", "qup-config", 1479 "qup-memory"; 1480 power-domains = <&rpmhpd SC7280_CX>; 1481 required-opps = <&rpmhpd_opp_low_svs>; 1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1483 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1484 dma-names = "tx", "rx"; 1485 status = "disabled"; 1486 }; 1487 1488 spi6: spi@998000 { 1489 compatible = "qcom,geni-spi"; 1490 reg = <0 0x00998000 0 0x4000>; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1492 clock-names = "se"; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 power-domains = <&rpmhpd SC7280_CX>; 1499 operating-points-v2 = <&qup_opp_table>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1501 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1502 interconnect-names = "qup-core", "qup-config"; 1503 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1504 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1505 dma-names = "tx", "rx"; 1506 status = "disabled"; 1507 }; 1508 1509 uart6: serial@998000 { 1510 compatible = "qcom,geni-uart"; 1511 reg = <0 0x00998000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1513 clock-names = "se"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1516 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1517 power-domains = <&rpmhpd SC7280_CX>; 1518 operating-points-v2 = <&qup_opp_table>; 1519 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1521 interconnect-names = "qup-core", "qup-config"; 1522 status = "disabled"; 1523 }; 1524 1525 i2c7: i2c@99c000 { 1526 compatible = "qcom,geni-i2c"; 1527 reg = <0 0x0099c000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_i2c7_data_clk>; 1532 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1537 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1538 interconnect-names = "qup-core", "qup-config", 1539 "qup-memory"; 1540 power-domains = <&rpmhpd SC7280_CX>; 1541 required-opps = <&rpmhpd_opp_low_svs>; 1542 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1543 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1544 dma-names = "tx", "rx"; 1545 status = "disabled"; 1546 }; 1547 1548 spi7: spi@99c000 { 1549 compatible = "qcom,geni-spi"; 1550 reg = <0 0x0099c000 0 0x4000>; 1551 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1552 clock-names = "se"; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1555 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1556 #address-cells = <1>; 1557 #size-cells = <0>; 1558 power-domains = <&rpmhpd SC7280_CX>; 1559 operating-points-v2 = <&qup_opp_table>; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1561 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1562 interconnect-names = "qup-core", "qup-config"; 1563 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1564 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1565 dma-names = "tx", "rx"; 1566 status = "disabled"; 1567 }; 1568 1569 uart7: serial@99c000 { 1570 compatible = "qcom,geni-uart"; 1571 reg = <0 0x0099c000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1573 clock-names = "se"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1576 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1577 power-domains = <&rpmhpd SC7280_CX>; 1578 operating-points-v2 = <&qup_opp_table>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1581 interconnect-names = "qup-core", "qup-config"; 1582 status = "disabled"; 1583 }; 1584 }; 1585 1586 gpi_dma1: dma-controller@a00000 { 1587 #dma-cells = <3>; 1588 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1589 reg = <0 0x00a00000 0 0x60000>; 1590 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1602 dma-channels = <12>; 1603 dma-channel-mask = <0x1e>; 1604 iommus = <&apps_smmu 0x56 0x0>; 1605 status = "disabled"; 1606 }; 1607 1608 qupv3_id_1: geniqup@ac0000 { 1609 compatible = "qcom,geni-se-qup"; 1610 reg = <0 0x00ac0000 0 0x2000>; 1611 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1612 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1613 clock-names = "m-ahb", "s-ahb"; 1614 #address-cells = <2>; 1615 #size-cells = <2>; 1616 ranges; 1617 iommus = <&apps_smmu 0x43 0x0>; 1618 status = "disabled"; 1619 1620 i2c8: i2c@a80000 { 1621 compatible = "qcom,geni-i2c"; 1622 reg = <0 0x00a80000 0 0x4000>; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1624 clock-names = "se"; 1625 pinctrl-names = "default"; 1626 pinctrl-0 = <&qup_i2c8_data_clk>; 1627 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1631 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1632 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1633 interconnect-names = "qup-core", "qup-config", 1634 "qup-memory"; 1635 power-domains = <&rpmhpd SC7280_CX>; 1636 required-opps = <&rpmhpd_opp_low_svs>; 1637 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1638 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1639 dma-names = "tx", "rx"; 1640 status = "disabled"; 1641 }; 1642 1643 spi8: spi@a80000 { 1644 compatible = "qcom,geni-spi"; 1645 reg = <0 0x00a80000 0 0x4000>; 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1647 clock-names = "se"; 1648 pinctrl-names = "default"; 1649 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1650 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1660 dma-names = "tx", "rx"; 1661 status = "disabled"; 1662 }; 1663 1664 uart8: serial@a80000 { 1665 compatible = "qcom,geni-uart"; 1666 reg = <0 0x00a80000 0 0x4000>; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1668 clock-names = "se"; 1669 pinctrl-names = "default"; 1670 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1671 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1672 power-domains = <&rpmhpd SC7280_CX>; 1673 operating-points-v2 = <&qup_opp_table>; 1674 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1675 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1676 interconnect-names = "qup-core", "qup-config"; 1677 status = "disabled"; 1678 }; 1679 1680 i2c9: i2c@a84000 { 1681 compatible = "qcom,geni-i2c"; 1682 reg = <0 0x00a84000 0 0x4000>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1684 clock-names = "se"; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_i2c9_data_clk>; 1687 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1691 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1692 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1693 interconnect-names = "qup-core", "qup-config", 1694 "qup-memory"; 1695 power-domains = <&rpmhpd SC7280_CX>; 1696 required-opps = <&rpmhpd_opp_low_svs>; 1697 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1698 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1699 dma-names = "tx", "rx"; 1700 status = "disabled"; 1701 }; 1702 1703 spi9: spi@a84000 { 1704 compatible = "qcom,geni-spi"; 1705 reg = <0 0x00a84000 0 0x4000>; 1706 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1707 clock-names = "se"; 1708 pinctrl-names = "default"; 1709 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1710 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 operating-points-v2 = <&qup_opp_table>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1717 interconnect-names = "qup-core", "qup-config"; 1718 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1719 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1720 dma-names = "tx", "rx"; 1721 status = "disabled"; 1722 }; 1723 1724 uart9: serial@a84000 { 1725 compatible = "qcom,geni-uart"; 1726 reg = <0 0x00a84000 0 0x4000>; 1727 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1728 clock-names = "se"; 1729 pinctrl-names = "default"; 1730 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1731 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1732 power-domains = <&rpmhpd SC7280_CX>; 1733 operating-points-v2 = <&qup_opp_table>; 1734 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1735 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1736 interconnect-names = "qup-core", "qup-config"; 1737 status = "disabled"; 1738 }; 1739 1740 i2c10: i2c@a88000 { 1741 compatible = "qcom,geni-i2c"; 1742 reg = <0 0x00a88000 0 0x4000>; 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1744 clock-names = "se"; 1745 pinctrl-names = "default"; 1746 pinctrl-0 = <&qup_i2c10_data_clk>; 1747 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1751 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1752 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1753 interconnect-names = "qup-core", "qup-config", 1754 "qup-memory"; 1755 power-domains = <&rpmhpd SC7280_CX>; 1756 required-opps = <&rpmhpd_opp_low_svs>; 1757 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1759 dma-names = "tx", "rx"; 1760 status = "disabled"; 1761 }; 1762 1763 spi10: spi@a88000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0 0x00a88000 0 0x4000>; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1767 clock-names = "se"; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1770 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 uart10: serial@a88000 { 1785 compatible = "qcom,geni-uart"; 1786 reg = <0 0x00a88000 0 0x4000>; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1788 clock-names = "se"; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1791 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1792 power-domains = <&rpmhpd SC7280_CX>; 1793 operating-points-v2 = <&qup_opp_table>; 1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1795 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 status = "disabled"; 1798 }; 1799 1800 i2c11: i2c@a8c000 { 1801 compatible = "qcom,geni-i2c"; 1802 reg = <0 0x00a8c000 0 0x4000>; 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1804 clock-names = "se"; 1805 pinctrl-names = "default"; 1806 pinctrl-0 = <&qup_i2c11_data_clk>; 1807 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", 1814 "qup-memory"; 1815 power-domains = <&rpmhpd SC7280_CX>; 1816 required-opps = <&rpmhpd_opp_low_svs>; 1817 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1818 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1819 dma-names = "tx", "rx"; 1820 status = "disabled"; 1821 }; 1822 1823 spi11: spi@a8c000 { 1824 compatible = "qcom,geni-spi"; 1825 reg = <0 0x00a8c000 0 0x4000>; 1826 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1827 clock-names = "se"; 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1830 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1839 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1840 dma-names = "tx", "rx"; 1841 status = "disabled"; 1842 }; 1843 1844 uart11: serial@a8c000 { 1845 compatible = "qcom,geni-uart"; 1846 reg = <0 0x00a8c000 0 0x4000>; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1848 clock-names = "se"; 1849 pinctrl-names = "default"; 1850 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1851 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1852 power-domains = <&rpmhpd SC7280_CX>; 1853 operating-points-v2 = <&qup_opp_table>; 1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1855 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1856 interconnect-names = "qup-core", "qup-config"; 1857 status = "disabled"; 1858 }; 1859 1860 i2c12: i2c@a90000 { 1861 compatible = "qcom,geni-i2c"; 1862 reg = <0 0x00a90000 0 0x4000>; 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1864 clock-names = "se"; 1865 pinctrl-names = "default"; 1866 pinctrl-0 = <&qup_i2c12_data_clk>; 1867 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", 1874 "qup-memory"; 1875 power-domains = <&rpmhpd SC7280_CX>; 1876 required-opps = <&rpmhpd_opp_low_svs>; 1877 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1878 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1879 dma-names = "tx", "rx"; 1880 status = "disabled"; 1881 }; 1882 1883 spi12: spi@a90000 { 1884 compatible = "qcom,geni-spi"; 1885 reg = <0 0x00a90000 0 0x4000>; 1886 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1887 clock-names = "se"; 1888 pinctrl-names = "default"; 1889 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1890 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 operating-points-v2 = <&qup_opp_table>; 1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1899 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1900 dma-names = "tx", "rx"; 1901 status = "disabled"; 1902 }; 1903 1904 uart12: serial@a90000 { 1905 compatible = "qcom,geni-uart"; 1906 reg = <0 0x00a90000 0 0x4000>; 1907 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1908 clock-names = "se"; 1909 pinctrl-names = "default"; 1910 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1911 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1912 power-domains = <&rpmhpd SC7280_CX>; 1913 operating-points-v2 = <&qup_opp_table>; 1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1915 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1916 interconnect-names = "qup-core", "qup-config"; 1917 status = "disabled"; 1918 }; 1919 1920 i2c13: i2c@a94000 { 1921 compatible = "qcom,geni-i2c"; 1922 reg = <0 0x00a94000 0 0x4000>; 1923 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1924 clock-names = "se"; 1925 pinctrl-names = "default"; 1926 pinctrl-0 = <&qup_i2c13_data_clk>; 1927 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1931 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1932 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1933 interconnect-names = "qup-core", "qup-config", 1934 "qup-memory"; 1935 power-domains = <&rpmhpd SC7280_CX>; 1936 required-opps = <&rpmhpd_opp_low_svs>; 1937 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1938 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1939 dma-names = "tx", "rx"; 1940 status = "disabled"; 1941 }; 1942 1943 spi13: spi@a94000 { 1944 compatible = "qcom,geni-spi"; 1945 reg = <0 0x00a94000 0 0x4000>; 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1947 clock-names = "se"; 1948 pinctrl-names = "default"; 1949 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1950 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1959 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1960 dma-names = "tx", "rx"; 1961 status = "disabled"; 1962 }; 1963 1964 uart13: serial@a94000 { 1965 compatible = "qcom,geni-uart"; 1966 reg = <0 0x00a94000 0 0x4000>; 1967 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1968 clock-names = "se"; 1969 pinctrl-names = "default"; 1970 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1971 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1972 power-domains = <&rpmhpd SC7280_CX>; 1973 operating-points-v2 = <&qup_opp_table>; 1974 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1975 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1976 interconnect-names = "qup-core", "qup-config"; 1977 status = "disabled"; 1978 }; 1979 1980 i2c14: i2c@a98000 { 1981 compatible = "qcom,geni-i2c"; 1982 reg = <0 0x00a98000 0 0x4000>; 1983 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1984 clock-names = "se"; 1985 pinctrl-names = "default"; 1986 pinctrl-0 = <&qup_i2c14_data_clk>; 1987 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1988 #address-cells = <1>; 1989 #size-cells = <0>; 1990 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1991 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1992 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1993 interconnect-names = "qup-core", "qup-config", 1994 "qup-memory"; 1995 power-domains = <&rpmhpd SC7280_CX>; 1996 required-opps = <&rpmhpd_opp_low_svs>; 1997 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1998 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1999 dma-names = "tx", "rx"; 2000 status = "disabled"; 2001 }; 2002 2003 spi14: spi@a98000 { 2004 compatible = "qcom,geni-spi"; 2005 reg = <0 0x00a98000 0 0x4000>; 2006 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2007 clock-names = "se"; 2008 pinctrl-names = "default"; 2009 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2010 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 power-domains = <&rpmhpd SC7280_CX>; 2014 operating-points-v2 = <&qup_opp_table>; 2015 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2016 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2017 interconnect-names = "qup-core", "qup-config"; 2018 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2019 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2020 dma-names = "tx", "rx"; 2021 status = "disabled"; 2022 }; 2023 2024 uart14: serial@a98000 { 2025 compatible = "qcom,geni-uart"; 2026 reg = <0 0x00a98000 0 0x4000>; 2027 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2028 clock-names = "se"; 2029 pinctrl-names = "default"; 2030 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2031 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2032 power-domains = <&rpmhpd SC7280_CX>; 2033 operating-points-v2 = <&qup_opp_table>; 2034 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2036 interconnect-names = "qup-core", "qup-config"; 2037 status = "disabled"; 2038 }; 2039 2040 i2c15: i2c@a9c000 { 2041 compatible = "qcom,geni-i2c"; 2042 reg = <0 0x00a9c000 0 0x4000>; 2043 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2044 clock-names = "se"; 2045 pinctrl-names = "default"; 2046 pinctrl-0 = <&qup_i2c15_data_clk>; 2047 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2048 #address-cells = <1>; 2049 #size-cells = <0>; 2050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2052 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2053 interconnect-names = "qup-core", "qup-config", 2054 "qup-memory"; 2055 power-domains = <&rpmhpd SC7280_CX>; 2056 required-opps = <&rpmhpd_opp_low_svs>; 2057 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2058 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2059 dma-names = "tx", "rx"; 2060 status = "disabled"; 2061 }; 2062 2063 spi15: spi@a9c000 { 2064 compatible = "qcom,geni-spi"; 2065 reg = <0 0x00a9c000 0 0x4000>; 2066 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2067 clock-names = "se"; 2068 pinctrl-names = "default"; 2069 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2070 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 power-domains = <&rpmhpd SC7280_CX>; 2074 operating-points-v2 = <&qup_opp_table>; 2075 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2076 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2077 interconnect-names = "qup-core", "qup-config"; 2078 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2079 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2080 dma-names = "tx", "rx"; 2081 status = "disabled"; 2082 }; 2083 2084 uart15: serial@a9c000 { 2085 compatible = "qcom,geni-uart"; 2086 reg = <0 0x00a9c000 0 0x4000>; 2087 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2088 clock-names = "se"; 2089 pinctrl-names = "default"; 2090 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2091 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2092 power-domains = <&rpmhpd SC7280_CX>; 2093 operating-points-v2 = <&qup_opp_table>; 2094 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2095 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2096 interconnect-names = "qup-core", "qup-config"; 2097 status = "disabled"; 2098 }; 2099 }; 2100 2101 rng: rng@10d3000 { 2102 compatible = "qcom,sc7280-trng", "qcom,trng"; 2103 reg = <0 0x010d3000 0 0x1000>; 2104 }; 2105 2106 cnoc2: interconnect@1500000 { 2107 reg = <0 0x01500000 0 0x1000>; 2108 compatible = "qcom,sc7280-cnoc2"; 2109 #interconnect-cells = <2>; 2110 qcom,bcm-voters = <&apps_bcm_voter>; 2111 }; 2112 2113 cnoc3: interconnect@1502000 { 2114 reg = <0 0x01502000 0 0x1000>; 2115 compatible = "qcom,sc7280-cnoc3"; 2116 #interconnect-cells = <2>; 2117 qcom,bcm-voters = <&apps_bcm_voter>; 2118 }; 2119 2120 mc_virt: interconnect@1580000 { 2121 reg = <0 0x01580000 0 0x4>; 2122 compatible = "qcom,sc7280-mc-virt"; 2123 #interconnect-cells = <2>; 2124 qcom,bcm-voters = <&apps_bcm_voter>; 2125 }; 2126 2127 system_noc: interconnect@1680000 { 2128 reg = <0 0x01680000 0 0x15480>; 2129 compatible = "qcom,sc7280-system-noc"; 2130 #interconnect-cells = <2>; 2131 qcom,bcm-voters = <&apps_bcm_voter>; 2132 }; 2133 2134 aggre1_noc: interconnect@16e0000 { 2135 compatible = "qcom,sc7280-aggre1-noc"; 2136 reg = <0 0x016e0000 0 0x1c080>; 2137 #interconnect-cells = <2>; 2138 qcom,bcm-voters = <&apps_bcm_voter>; 2139 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2140 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2141 }; 2142 2143 aggre2_noc: interconnect@1700000 { 2144 reg = <0 0x01700000 0 0x2b080>; 2145 compatible = "qcom,sc7280-aggre2-noc"; 2146 #interconnect-cells = <2>; 2147 qcom,bcm-voters = <&apps_bcm_voter>; 2148 clocks = <&rpmhcc RPMH_IPA_CLK>; 2149 }; 2150 2151 mmss_noc: interconnect@1740000 { 2152 reg = <0 0x01740000 0 0x1e080>; 2153 compatible = "qcom,sc7280-mmss-noc"; 2154 #interconnect-cells = <2>; 2155 qcom,bcm-voters = <&apps_bcm_voter>; 2156 }; 2157 2158 wifi: wifi@17a10040 { 2159 compatible = "qcom,wcn6750-wifi"; 2160 reg = <0 0x17a10040 0 0x0>; 2161 iommus = <&apps_smmu 0x1c00 0x1>; 2162 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2163 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2164 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2194 qcom,rproc = <&remoteproc_wpss>; 2195 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2196 status = "disabled"; 2197 qcom,smem-states = <&wlan_smp2p_out 0>; 2198 qcom,smem-state-names = "wlan-smp2p-out"; 2199 }; 2200 2201 pcie1: pcie@1c08000 { 2202 compatible = "qcom,pcie-sc7280"; 2203 reg = <0 0x01c08000 0 0x3000>, 2204 <0 0x40000000 0 0xf1d>, 2205 <0 0x40000f20 0 0xa8>, 2206 <0 0x40001000 0 0x1000>, 2207 <0 0x40100000 0 0x100000>; 2208 2209 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2210 device_type = "pci"; 2211 linux,pci-domain = <1>; 2212 bus-range = <0x00 0xff>; 2213 num-lanes = <2>; 2214 2215 #address-cells = <3>; 2216 #size-cells = <2>; 2217 2218 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2219 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2220 2221 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2229 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2230 "msi4", "msi5", "msi6", "msi7"; 2231 #interrupt-cells = <1>; 2232 interrupt-map-mask = <0 0 0 0x7>; 2233 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2234 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2235 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2236 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2239 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2240 <&pcie1_phy>, 2241 <&rpmhcc RPMH_CXO_CLK>, 2242 <&gcc GCC_PCIE_1_AUX_CLK>, 2243 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2244 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2245 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2246 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2247 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2248 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2249 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2250 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2251 2252 clock-names = "pipe", 2253 "pipe_mux", 2254 "phy_pipe", 2255 "ref", 2256 "aux", 2257 "cfg", 2258 "bus_master", 2259 "bus_slave", 2260 "slave_q2a", 2261 "tbu", 2262 "ddrss_sf_tbu", 2263 "aggre0", 2264 "aggre1"; 2265 2266 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2267 assigned-clock-rates = <19200000>; 2268 2269 resets = <&gcc GCC_PCIE_1_BCR>; 2270 reset-names = "pci"; 2271 2272 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2273 2274 phys = <&pcie1_phy>; 2275 phy-names = "pciephy"; 2276 2277 pinctrl-names = "default"; 2278 pinctrl-0 = <&pcie1_clkreq_n>; 2279 2280 dma-coherent; 2281 2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2283 <0x100 &apps_smmu 0x1c81 0x1>; 2284 2285 status = "disabled"; 2286 2287 pcie@0 { 2288 device_type = "pci"; 2289 reg = <0x0 0x0 0x0 0x0 0x0>; 2290 bus-range = <0x01 0xff>; 2291 2292 #address-cells = <3>; 2293 #size-cells = <2>; 2294 ranges; 2295 }; 2296 }; 2297 2298 pcie1_phy: phy@1c0e000 { 2299 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2300 reg = <0 0x01c0e000 0 0x1000>; 2301 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2302 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2303 <&gcc GCC_PCIE_CLKREF_EN>, 2304 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2305 <&gcc GCC_PCIE_1_PIPE_CLK>; 2306 clock-names = "aux", 2307 "cfg_ahb", 2308 "ref", 2309 "refgen", 2310 "pipe"; 2311 2312 clock-output-names = "pcie_1_pipe_clk"; 2313 #clock-cells = <0>; 2314 2315 #phy-cells = <0>; 2316 2317 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2318 reset-names = "phy"; 2319 2320 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2321 assigned-clock-rates = <100000000>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2328 "jedec,ufs-2.0"; 2329 reg = <0x0 0x01d84000 0x0 0x3000>; 2330 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2331 phys = <&ufs_mem_phy>; 2332 phy-names = "ufsphy"; 2333 lanes-per-direction = <2>; 2334 #reset-cells = <1>; 2335 resets = <&gcc GCC_UFS_PHY_BCR>; 2336 reset-names = "rst"; 2337 2338 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2339 required-opps = <&rpmhpd_opp_nom>; 2340 2341 iommus = <&apps_smmu 0x80 0x0>; 2342 dma-coherent; 2343 2344 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2347 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2348 interconnect-names = "ufs-ddr", "cpu-ufs"; 2349 2350 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2351 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2352 <&gcc GCC_UFS_PHY_AHB_CLK>, 2353 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2354 <&rpmhcc RPMH_CXO_CLK>, 2355 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2356 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2357 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2358 clock-names = "core_clk", 2359 "bus_aggr_clk", 2360 "iface_clk", 2361 "core_clk_unipro", 2362 "ref_clk", 2363 "tx_lane0_sync_clk", 2364 "rx_lane0_sync_clk", 2365 "rx_lane1_sync_clk"; 2366 freq-table-hz = 2367 <75000000 300000000>, 2368 <0 0>, 2369 <0 0>, 2370 <75000000 300000000>, 2371 <0 0>, 2372 <0 0>, 2373 <0 0>, 2374 <0 0>; 2375 qcom,ice = <&ice>; 2376 2377 status = "disabled"; 2378 }; 2379 2380 ufs_mem_phy: phy@1d87000 { 2381 compatible = "qcom,sc7280-qmp-ufs-phy"; 2382 reg = <0x0 0x01d87000 0x0 0xe00>; 2383 clocks = <&rpmhcc RPMH_CXO_CLK>, 2384 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2385 <&gcc GCC_UFS_1_CLKREF_EN>; 2386 clock-names = "ref", "ref_aux", "qref"; 2387 2388 power-domains = <&rpmhpd SC7280_MX>; 2389 2390 resets = <&ufs_mem_hc 0>; 2391 reset-names = "ufsphy"; 2392 2393 #clock-cells = <1>; 2394 #phy-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 ice: crypto@1d88000 { 2400 compatible = "qcom,sc7280-inline-crypto-engine", 2401 "qcom,inline-crypto-engine"; 2402 reg = <0 0x01d88000 0 0x8000>; 2403 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2404 }; 2405 2406 cryptobam: dma-controller@1dc4000 { 2407 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2408 reg = <0x0 0x01dc4000 0x0 0x28000>; 2409 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2410 #dma-cells = <1>; 2411 iommus = <&apps_smmu 0x4e4 0x0011>, 2412 <&apps_smmu 0x4e6 0x0011>; 2413 qcom,ee = <0>; 2414 qcom,controlled-remotely; 2415 num-channels = <16>; 2416 qcom,num-ees = <4>; 2417 }; 2418 2419 crypto: crypto@1dfa000 { 2420 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2421 reg = <0x0 0x01dfa000 0x0 0x6000>; 2422 dmas = <&cryptobam 4>, <&cryptobam 5>; 2423 dma-names = "rx", "tx"; 2424 iommus = <&apps_smmu 0x4e4 0x0011>, 2425 <&apps_smmu 0x4e4 0x0011>; 2426 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2427 interconnect-names = "memory"; 2428 }; 2429 2430 ipa: ipa@1e40000 { 2431 compatible = "qcom,sc7280-ipa"; 2432 2433 iommus = <&apps_smmu 0x480 0x0>, 2434 <&apps_smmu 0x482 0x0>; 2435 reg = <0 0x01e40000 0 0x8000>, 2436 <0 0x01e50000 0 0x4ad0>, 2437 <0 0x01e04000 0 0x23000>; 2438 reg-names = "ipa-reg", 2439 "ipa-shared", 2440 "gsi"; 2441 2442 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2443 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2444 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2445 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2446 interrupt-names = "ipa", 2447 "gsi", 2448 "ipa-clock-query", 2449 "ipa-setup-ready"; 2450 2451 clocks = <&rpmhcc RPMH_IPA_CLK>; 2452 clock-names = "core"; 2453 2454 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2456 interconnect-names = "memory", 2457 "config"; 2458 2459 qcom,qmp = <&aoss_qmp>; 2460 2461 qcom,smem-states = <&ipa_smp2p_out 0>, 2462 <&ipa_smp2p_out 1>; 2463 qcom,smem-state-names = "ipa-clock-enabled-valid", 2464 "ipa-clock-enabled"; 2465 2466 status = "disabled"; 2467 }; 2468 2469 tcsr_mutex: hwlock@1f40000 { 2470 compatible = "qcom,tcsr-mutex"; 2471 reg = <0 0x01f40000 0 0x20000>; 2472 #hwlock-cells = <1>; 2473 }; 2474 2475 tcsr_1: syscon@1f60000 { 2476 compatible = "qcom,sc7280-tcsr", "syscon"; 2477 reg = <0 0x01f60000 0 0x20000>; 2478 }; 2479 2480 tcsr_2: syscon@1fc0000 { 2481 compatible = "qcom,sc7280-tcsr", "syscon"; 2482 reg = <0 0x01fc0000 0 0x30000>; 2483 }; 2484 2485 lpasscc: lpasscc@3000000 { 2486 compatible = "qcom,sc7280-lpasscc"; 2487 reg = <0 0x03000000 0 0x40>, 2488 <0 0x03c04000 0 0x4>; 2489 reg-names = "qdsp6ss", "top_cc"; 2490 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2491 clock-names = "iface"; 2492 #clock-cells = <1>; 2493 status = "reserved"; /* Owned by ADSP firmware */ 2494 }; 2495 2496 lpass_rx_macro: codec@3200000 { 2497 compatible = "qcom,sc7280-lpass-rx-macro"; 2498 reg = <0 0x03200000 0 0x1000>; 2499 2500 pinctrl-names = "default"; 2501 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2502 2503 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2504 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2505 <&lpass_va_macro>; 2506 clock-names = "mclk", "npl", "fsgen"; 2507 2508 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2509 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2510 power-domain-names = "macro", "dcodec"; 2511 2512 #clock-cells = <0>; 2513 #sound-dai-cells = <1>; 2514 2515 status = "disabled"; 2516 }; 2517 2518 swr0: soundwire@3210000 { 2519 compatible = "qcom,soundwire-v1.6.0"; 2520 reg = <0 0x03210000 0 0x2000>; 2521 2522 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2523 clocks = <&lpass_rx_macro>; 2524 clock-names = "iface"; 2525 2526 qcom,din-ports = <0>; 2527 qcom,dout-ports = <5>; 2528 2529 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2530 reset-names = "swr_audio_cgcr"; 2531 2532 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2533 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2534 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2535 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2536 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2537 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2538 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2539 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2541 2542 #sound-dai-cells = <1>; 2543 #address-cells = <2>; 2544 #size-cells = <0>; 2545 2546 status = "disabled"; 2547 }; 2548 2549 lpass_tx_macro: codec@3220000 { 2550 compatible = "qcom,sc7280-lpass-tx-macro"; 2551 reg = <0 0x03220000 0 0x1000>; 2552 2553 pinctrl-names = "default"; 2554 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2555 2556 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2557 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2558 <&lpass_va_macro>; 2559 clock-names = "mclk", "npl", "fsgen"; 2560 2561 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2562 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2563 power-domain-names = "macro", "dcodec"; 2564 2565 #clock-cells = <0>; 2566 #sound-dai-cells = <1>; 2567 2568 status = "disabled"; 2569 }; 2570 2571 swr1: soundwire@3230000 { 2572 compatible = "qcom,soundwire-v1.6.0"; 2573 reg = <0 0x03230000 0 0x2000>; 2574 2575 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2576 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2577 clocks = <&lpass_tx_macro>; 2578 clock-names = "iface"; 2579 2580 qcom,din-ports = <3>; 2581 qcom,dout-ports = <0>; 2582 2583 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2584 reset-names = "swr_audio_cgcr"; 2585 2586 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2587 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2588 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2589 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2590 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2591 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2592 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2593 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2594 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2595 2596 #sound-dai-cells = <1>; 2597 #address-cells = <2>; 2598 #size-cells = <0>; 2599 2600 status = "disabled"; 2601 }; 2602 2603 lpass_audiocc: clock-controller@3300000 { 2604 compatible = "qcom,sc7280-lpassaudiocc"; 2605 reg = <0 0x03300000 0 0x30000>, 2606 <0 0x032a9000 0 0x1000>; 2607 clocks = <&rpmhcc RPMH_CXO_CLK>, 2608 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2609 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2610 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2611 #clock-cells = <1>; 2612 #power-domain-cells = <1>; 2613 #reset-cells = <1>; 2614 }; 2615 2616 lpass_va_macro: codec@3370000 { 2617 compatible = "qcom,sc7280-lpass-va-macro"; 2618 reg = <0 0x03370000 0 0x1000>; 2619 2620 pinctrl-names = "default"; 2621 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2622 2623 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2624 clock-names = "mclk"; 2625 2626 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2627 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2628 power-domain-names = "macro", "dcodec"; 2629 2630 #clock-cells = <0>; 2631 #sound-dai-cells = <1>; 2632 2633 status = "disabled"; 2634 }; 2635 2636 lpass_aon: clock-controller@3380000 { 2637 compatible = "qcom,sc7280-lpassaoncc"; 2638 reg = <0 0x03380000 0 0x30000>; 2639 clocks = <&rpmhcc RPMH_CXO_CLK>, 2640 <&rpmhcc RPMH_CXO_CLK_A>, 2641 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2642 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2643 #clock-cells = <1>; 2644 #power-domain-cells = <1>; 2645 status = "reserved"; /* Owned by ADSP firmware */ 2646 }; 2647 2648 lpass_core: clock-controller@3900000 { 2649 compatible = "qcom,sc7280-lpasscorecc"; 2650 reg = <0 0x03900000 0 0x50000>; 2651 clocks = <&rpmhcc RPMH_CXO_CLK>; 2652 clock-names = "bi_tcxo"; 2653 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2654 #clock-cells = <1>; 2655 #power-domain-cells = <1>; 2656 status = "reserved"; /* Owned by ADSP firmware */ 2657 }; 2658 2659 lpass_cpu: audio@3987000 { 2660 compatible = "qcom,sc7280-lpass-cpu"; 2661 2662 reg = <0 0x03987000 0 0x68000>, 2663 <0 0x03b00000 0 0x29000>, 2664 <0 0x03260000 0 0xc000>, 2665 <0 0x03280000 0 0x29000>, 2666 <0 0x03340000 0 0x29000>, 2667 <0 0x0336c000 0 0x3000>; 2668 reg-names = "lpass-hdmiif", 2669 "lpass-lpaif", 2670 "lpass-rxtx-cdc-dma-lpm", 2671 "lpass-rxtx-lpaif", 2672 "lpass-va-lpaif", 2673 "lpass-va-cdc-dma-lpm"; 2674 2675 iommus = <&apps_smmu 0x1820 0>, 2676 <&apps_smmu 0x1821 0>, 2677 <&apps_smmu 0x1832 0>; 2678 2679 power-domains = <&rpmhpd SC7280_LCX>; 2680 power-domain-names = "lcx"; 2681 required-opps = <&rpmhpd_opp_nom>; 2682 2683 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2684 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2685 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2686 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2687 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2688 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2689 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2690 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2691 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2692 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2693 clock-names = "aon_cc_audio_hm_h", 2694 "audio_cc_ext_mclk0", 2695 "core_cc_sysnoc_mport_core", 2696 "core_cc_ext_if0_ibit", 2697 "core_cc_ext_if1_ibit", 2698 "audio_cc_codec_mem", 2699 "audio_cc_codec_mem0", 2700 "audio_cc_codec_mem1", 2701 "audio_cc_codec_mem2", 2702 "aon_cc_va_mem0"; 2703 2704 #sound-dai-cells = <1>; 2705 #address-cells = <1>; 2706 #size-cells = <0>; 2707 2708 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2712 interrupt-names = "lpass-irq-lpaif", 2713 "lpass-irq-hdmi", 2714 "lpass-irq-vaif", 2715 "lpass-irq-rxtxif"; 2716 2717 status = "disabled"; 2718 }; 2719 2720 slimbam: dma-controller@3a84000 { 2721 compatible = "qcom,bam-v1.7.0"; 2722 reg = <0 0x03a84000 0 0x20000>; 2723 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2724 #dma-cells = <1>; 2725 qcom,controlled-remotely; 2726 num-channels = <31>; 2727 qcom,ee = <1>; 2728 qcom,num-ees = <2>; 2729 iommus = <&apps_smmu 0x1826 0x0>; 2730 status = "disabled"; 2731 }; 2732 2733 slim: slim-ngd@3ac0000 { 2734 compatible = "qcom,slim-ngd-v1.5.0"; 2735 reg = <0 0x03ac0000 0 0x2c000>; 2736 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2737 dmas = <&slimbam 3>, <&slimbam 4>; 2738 dma-names = "rx", "tx"; 2739 iommus = <&apps_smmu 0x1826 0x0>; 2740 #address-cells = <1>; 2741 #size-cells = <0>; 2742 status = "disabled"; 2743 }; 2744 2745 lpass_hm: clock-controller@3c00000 { 2746 compatible = "qcom,sc7280-lpasshm"; 2747 reg = <0 0x03c00000 0 0x28>; 2748 clocks = <&rpmhcc RPMH_CXO_CLK>; 2749 clock-names = "bi_tcxo"; 2750 #clock-cells = <1>; 2751 #power-domain-cells = <1>; 2752 status = "reserved"; /* Owned by ADSP firmware */ 2753 }; 2754 2755 lpass_ag_noc: interconnect@3c40000 { 2756 reg = <0 0x03c40000 0 0xf080>; 2757 compatible = "qcom,sc7280-lpass-ag-noc"; 2758 #interconnect-cells = <2>; 2759 qcom,bcm-voters = <&apps_bcm_voter>; 2760 }; 2761 2762 lpass_tlmm: pinctrl@33c0000 { 2763 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2764 reg = <0 0x033c0000 0x0 0x20000>, 2765 <0 0x03550000 0x0 0x10000>; 2766 gpio-controller; 2767 #gpio-cells = <2>; 2768 gpio-ranges = <&lpass_tlmm 0 0 15>; 2769 2770 lpass_dmic01_clk: dmic01-clk-state { 2771 pins = "gpio6"; 2772 function = "dmic1_clk"; 2773 }; 2774 2775 lpass_dmic01_data: dmic01-data-state { 2776 pins = "gpio7"; 2777 function = "dmic1_data"; 2778 }; 2779 2780 lpass_dmic23_clk: dmic23-clk-state { 2781 pins = "gpio8"; 2782 function = "dmic2_clk"; 2783 }; 2784 2785 lpass_dmic23_data: dmic23-data-state { 2786 pins = "gpio9"; 2787 function = "dmic2_data"; 2788 }; 2789 2790 lpass_rx_swr_clk: rx-swr-clk-state { 2791 pins = "gpio3"; 2792 function = "swr_rx_clk"; 2793 }; 2794 2795 lpass_rx_swr_data: rx-swr-data-state { 2796 pins = "gpio4", "gpio5"; 2797 function = "swr_rx_data"; 2798 }; 2799 2800 lpass_tx_swr_clk: tx-swr-clk-state { 2801 pins = "gpio0"; 2802 function = "swr_tx_clk"; 2803 }; 2804 2805 lpass_tx_swr_data: tx-swr-data-state { 2806 pins = "gpio1", "gpio2", "gpio14"; 2807 function = "swr_tx_data"; 2808 }; 2809 }; 2810 2811 gpu: gpu@3d00000 { 2812 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2813 reg = <0 0x03d00000 0 0x40000>, 2814 <0 0x03d9e000 0 0x1000>, 2815 <0 0x03d61000 0 0x800>; 2816 reg-names = "kgsl_3d0_reg_memory", 2817 "cx_mem", 2818 "cx_dbgc"; 2819 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2820 iommus = <&adreno_smmu 0 0x400>, 2821 <&adreno_smmu 1 0x400>; 2822 operating-points-v2 = <&gpu_opp_table>; 2823 qcom,gmu = <&gmu>; 2824 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2825 interconnect-names = "gfx-mem"; 2826 #cooling-cells = <2>; 2827 2828 nvmem-cells = <&gpu_speed_bin>; 2829 nvmem-cell-names = "speed_bin"; 2830 2831 status = "disabled"; 2832 2833 gpu_zap_shader: zap-shader { 2834 memory-region = <&gpu_zap_mem>; 2835 }; 2836 2837 gpu_opp_table: opp-table { 2838 compatible = "operating-points-v2"; 2839 2840 opp-315000000 { 2841 opp-hz = /bits/ 64 <315000000>; 2842 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2843 opp-peak-kBps = <1804000>; 2844 opp-supported-hw = <0x17>; 2845 }; 2846 2847 opp-450000000 { 2848 opp-hz = /bits/ 64 <450000000>; 2849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2850 opp-peak-kBps = <4068000>; 2851 opp-supported-hw = <0x17>; 2852 }; 2853 2854 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2855 opp-550000000-0 { 2856 opp-hz = /bits/ 64 <550000000>; 2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2858 opp-peak-kBps = <8368000>; 2859 opp-supported-hw = <0x01>; 2860 }; 2861 2862 opp-550000000-1 { 2863 opp-hz = /bits/ 64 <550000000>; 2864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2865 opp-peak-kBps = <6832000>; 2866 opp-supported-hw = <0x16>; 2867 }; 2868 2869 opp-608000000 { 2870 opp-hz = /bits/ 64 <608000000>; 2871 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2872 opp-peak-kBps = <8368000>; 2873 opp-supported-hw = <0x16>; 2874 }; 2875 2876 opp-700000000 { 2877 opp-hz = /bits/ 64 <700000000>; 2878 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2879 opp-peak-kBps = <8532000>; 2880 opp-supported-hw = <0x06>; 2881 }; 2882 2883 opp-812000000 { 2884 opp-hz = /bits/ 64 <812000000>; 2885 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2886 opp-peak-kBps = <8532000>; 2887 opp-supported-hw = <0x06>; 2888 }; 2889 2890 opp-840000000 { 2891 opp-hz = /bits/ 64 <840000000>; 2892 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2893 opp-peak-kBps = <8532000>; 2894 opp-supported-hw = <0x02>; 2895 }; 2896 2897 opp-900000000 { 2898 opp-hz = /bits/ 64 <900000000>; 2899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2900 opp-peak-kBps = <8532000>; 2901 opp-supported-hw = <0x02>; 2902 }; 2903 }; 2904 }; 2905 2906 gmu: gmu@3d6a000 { 2907 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2908 reg = <0 0x03d6a000 0 0x34000>, 2909 <0 0x3de0000 0 0x10000>, 2910 <0 0x0b290000 0 0x10000>; 2911 reg-names = "gmu", "rscc", "gmu_pdc"; 2912 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2914 interrupt-names = "hfi", "gmu"; 2915 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2916 <&gpucc GPU_CC_CXO_CLK>, 2917 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2918 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2919 <&gpucc GPU_CC_AHB_CLK>, 2920 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2921 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2922 clock-names = "gmu", 2923 "cxo", 2924 "axi", 2925 "memnoc", 2926 "ahb", 2927 "hub", 2928 "smmu_vote"; 2929 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2930 <&gpucc GPU_CC_GX_GDSC>; 2931 power-domain-names = "cx", 2932 "gx"; 2933 iommus = <&adreno_smmu 5 0x400>; 2934 operating-points-v2 = <&gmu_opp_table>; 2935 2936 gmu_opp_table: opp-table { 2937 compatible = "operating-points-v2"; 2938 2939 opp-200000000 { 2940 opp-hz = /bits/ 64 <200000000>; 2941 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2942 }; 2943 }; 2944 }; 2945 2946 gpucc: clock-controller@3d90000 { 2947 compatible = "qcom,sc7280-gpucc"; 2948 reg = <0 0x03d90000 0 0x9000>; 2949 clocks = <&rpmhcc RPMH_CXO_CLK>, 2950 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2951 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2952 clock-names = "bi_tcxo", 2953 "gcc_gpu_gpll0_clk_src", 2954 "gcc_gpu_gpll0_div_clk_src"; 2955 #clock-cells = <1>; 2956 #reset-cells = <1>; 2957 #power-domain-cells = <1>; 2958 }; 2959 2960 dma@117f000 { 2961 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2962 reg = <0x0 0x0117f000 0x0 0x1000>, 2963 <0x0 0x01112000 0x0 0x6000>; 2964 }; 2965 2966 adreno_smmu: iommu@3da0000 { 2967 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2968 "qcom,smmu-500", "arm,mmu-500"; 2969 reg = <0 0x03da0000 0 0x20000>; 2970 #iommu-cells = <2>; 2971 #global-interrupts = <2>; 2972 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2984 2985 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2986 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2987 <&gpucc GPU_CC_AHB_CLK>, 2988 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2989 <&gpucc GPU_CC_CX_GMU_CLK>, 2990 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2991 <&gpucc GPU_CC_HUB_AON_CLK>; 2992 clock-names = "gcc_gpu_memnoc_gfx_clk", 2993 "gcc_gpu_snoc_dvm_gfx_clk", 2994 "gpu_cc_ahb_clk", 2995 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2996 "gpu_cc_cx_gmu_clk", 2997 "gpu_cc_hub_cx_int_clk", 2998 "gpu_cc_hub_aon_clk"; 2999 3000 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3001 dma-coherent; 3002 }; 3003 3004 gfx_0_tbu: tbu@3dd9000 { 3005 compatible = "qcom,sc7280-tbu"; 3006 reg = <0x0 0x3dd9000 0x0 0x1000>; 3007 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3008 }; 3009 3010 gfx_1_tbu: tbu@3ddd000 { 3011 compatible = "qcom,sc7280-tbu"; 3012 reg = <0x0 0x3ddd000 0x0 0x1000>; 3013 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3014 }; 3015 3016 remoteproc_mpss: remoteproc@4080000 { 3017 compatible = "qcom,sc7280-mpss-pas"; 3018 reg = <0 0x04080000 0 0x10000>; 3019 3020 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3021 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3022 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3023 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3024 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3025 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3026 interrupt-names = "wdog", "fatal", "ready", "handover", 3027 "stop-ack", "shutdown-ack"; 3028 3029 clocks = <&rpmhcc RPMH_CXO_CLK>; 3030 clock-names = "xo"; 3031 3032 power-domains = <&rpmhpd SC7280_CX>, 3033 <&rpmhpd SC7280_MSS>; 3034 power-domain-names = "cx", "mss"; 3035 3036 memory-region = <&mpss_mem>; 3037 3038 qcom,qmp = <&aoss_qmp>; 3039 3040 qcom,smem-states = <&modem_smp2p_out 0>; 3041 qcom,smem-state-names = "stop"; 3042 3043 status = "disabled"; 3044 3045 glink-edge { 3046 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3047 IPCC_MPROC_SIGNAL_GLINK_QMP 3048 IRQ_TYPE_EDGE_RISING>; 3049 mboxes = <&ipcc IPCC_CLIENT_MPSS 3050 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3051 label = "modem"; 3052 qcom,remote-pid = <1>; 3053 }; 3054 }; 3055 3056 stm@6002000 { 3057 compatible = "arm,coresight-stm", "arm,primecell"; 3058 reg = <0 0x06002000 0 0x1000>, 3059 <0 0x16280000 0 0x180000>; 3060 reg-names = "stm-base", "stm-stimulus-base"; 3061 3062 clocks = <&aoss_qmp>; 3063 clock-names = "apb_pclk"; 3064 3065 out-ports { 3066 port { 3067 stm_out: endpoint { 3068 remote-endpoint = <&funnel0_in7>; 3069 }; 3070 }; 3071 }; 3072 }; 3073 3074 funnel@6041000 { 3075 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3076 reg = <0 0x06041000 0 0x1000>; 3077 3078 clocks = <&aoss_qmp>; 3079 clock-names = "apb_pclk"; 3080 3081 out-ports { 3082 port { 3083 funnel0_out: endpoint { 3084 remote-endpoint = <&merge_funnel_in0>; 3085 }; 3086 }; 3087 }; 3088 3089 in-ports { 3090 #address-cells = <1>; 3091 #size-cells = <0>; 3092 3093 port@7 { 3094 reg = <7>; 3095 funnel0_in7: endpoint { 3096 remote-endpoint = <&stm_out>; 3097 }; 3098 }; 3099 }; 3100 }; 3101 3102 funnel@6042000 { 3103 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3104 reg = <0 0x06042000 0 0x1000>; 3105 3106 clocks = <&aoss_qmp>; 3107 clock-names = "apb_pclk"; 3108 3109 out-ports { 3110 port { 3111 funnel1_out: endpoint { 3112 remote-endpoint = <&merge_funnel_in1>; 3113 }; 3114 }; 3115 }; 3116 3117 in-ports { 3118 #address-cells = <1>; 3119 #size-cells = <0>; 3120 3121 port@4 { 3122 reg = <4>; 3123 funnel1_in4: endpoint { 3124 remote-endpoint = <&apss_merge_funnel_out>; 3125 }; 3126 }; 3127 }; 3128 }; 3129 3130 funnel@6045000 { 3131 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3132 reg = <0 0x06045000 0 0x1000>; 3133 3134 clocks = <&aoss_qmp>; 3135 clock-names = "apb_pclk"; 3136 3137 out-ports { 3138 port { 3139 merge_funnel_out: endpoint { 3140 remote-endpoint = <&swao_funnel_in>; 3141 }; 3142 }; 3143 }; 3144 3145 in-ports { 3146 #address-cells = <1>; 3147 #size-cells = <0>; 3148 3149 port@0 { 3150 reg = <0>; 3151 merge_funnel_in0: endpoint { 3152 remote-endpoint = <&funnel0_out>; 3153 }; 3154 }; 3155 3156 port@1 { 3157 reg = <1>; 3158 merge_funnel_in1: endpoint { 3159 remote-endpoint = <&funnel1_out>; 3160 }; 3161 }; 3162 }; 3163 }; 3164 3165 replicator@6046000 { 3166 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3167 reg = <0 0x06046000 0 0x1000>; 3168 3169 clocks = <&aoss_qmp>; 3170 clock-names = "apb_pclk"; 3171 3172 out-ports { 3173 port { 3174 replicator_out: endpoint { 3175 remote-endpoint = <&etr_in>; 3176 }; 3177 }; 3178 }; 3179 3180 in-ports { 3181 port { 3182 replicator_in: endpoint { 3183 remote-endpoint = <&swao_replicator_out>; 3184 }; 3185 }; 3186 }; 3187 }; 3188 3189 etr@6048000 { 3190 compatible = "arm,coresight-tmc", "arm,primecell"; 3191 reg = <0 0x06048000 0 0x1000>; 3192 iommus = <&apps_smmu 0x04c0 0>; 3193 3194 clocks = <&aoss_qmp>; 3195 clock-names = "apb_pclk"; 3196 arm,scatter-gather; 3197 3198 in-ports { 3199 port { 3200 etr_in: endpoint { 3201 remote-endpoint = <&replicator_out>; 3202 }; 3203 }; 3204 }; 3205 }; 3206 3207 funnel@6b04000 { 3208 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3209 reg = <0 0x06b04000 0 0x1000>; 3210 3211 clocks = <&aoss_qmp>; 3212 clock-names = "apb_pclk"; 3213 3214 out-ports { 3215 port { 3216 swao_funnel_out: endpoint { 3217 remote-endpoint = <&etf_in>; 3218 }; 3219 }; 3220 }; 3221 3222 in-ports { 3223 #address-cells = <1>; 3224 #size-cells = <0>; 3225 3226 port@7 { 3227 reg = <7>; 3228 swao_funnel_in: endpoint { 3229 remote-endpoint = <&merge_funnel_out>; 3230 }; 3231 }; 3232 }; 3233 }; 3234 3235 etf@6b05000 { 3236 compatible = "arm,coresight-tmc", "arm,primecell"; 3237 reg = <0 0x06b05000 0 0x1000>; 3238 3239 clocks = <&aoss_qmp>; 3240 clock-names = "apb_pclk"; 3241 3242 out-ports { 3243 port { 3244 etf_out: endpoint { 3245 remote-endpoint = <&swao_replicator_in>; 3246 }; 3247 }; 3248 }; 3249 3250 in-ports { 3251 port { 3252 etf_in: endpoint { 3253 remote-endpoint = <&swao_funnel_out>; 3254 }; 3255 }; 3256 }; 3257 }; 3258 3259 replicator@6b06000 { 3260 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3261 reg = <0 0x06b06000 0 0x1000>; 3262 3263 clocks = <&aoss_qmp>; 3264 clock-names = "apb_pclk"; 3265 qcom,replicator-loses-context; 3266 3267 out-ports { 3268 port { 3269 swao_replicator_out: endpoint { 3270 remote-endpoint = <&replicator_in>; 3271 }; 3272 }; 3273 }; 3274 3275 in-ports { 3276 port { 3277 swao_replicator_in: endpoint { 3278 remote-endpoint = <&etf_out>; 3279 }; 3280 }; 3281 }; 3282 }; 3283 3284 etm@7040000 { 3285 compatible = "arm,coresight-etm4x", "arm,primecell"; 3286 reg = <0 0x07040000 0 0x1000>; 3287 3288 cpu = <&cpu0>; 3289 3290 clocks = <&aoss_qmp>; 3291 clock-names = "apb_pclk"; 3292 arm,coresight-loses-context-with-cpu; 3293 qcom,skip-power-up; 3294 3295 out-ports { 3296 port { 3297 etm0_out: endpoint { 3298 remote-endpoint = <&apss_funnel_in0>; 3299 }; 3300 }; 3301 }; 3302 }; 3303 3304 etm@7140000 { 3305 compatible = "arm,coresight-etm4x", "arm,primecell"; 3306 reg = <0 0x07140000 0 0x1000>; 3307 3308 cpu = <&cpu1>; 3309 3310 clocks = <&aoss_qmp>; 3311 clock-names = "apb_pclk"; 3312 arm,coresight-loses-context-with-cpu; 3313 qcom,skip-power-up; 3314 3315 out-ports { 3316 port { 3317 etm1_out: endpoint { 3318 remote-endpoint = <&apss_funnel_in1>; 3319 }; 3320 }; 3321 }; 3322 }; 3323 3324 etm@7240000 { 3325 compatible = "arm,coresight-etm4x", "arm,primecell"; 3326 reg = <0 0x07240000 0 0x1000>; 3327 3328 cpu = <&cpu2>; 3329 3330 clocks = <&aoss_qmp>; 3331 clock-names = "apb_pclk"; 3332 arm,coresight-loses-context-with-cpu; 3333 qcom,skip-power-up; 3334 3335 out-ports { 3336 port { 3337 etm2_out: endpoint { 3338 remote-endpoint = <&apss_funnel_in2>; 3339 }; 3340 }; 3341 }; 3342 }; 3343 3344 etm@7340000 { 3345 compatible = "arm,coresight-etm4x", "arm,primecell"; 3346 reg = <0 0x07340000 0 0x1000>; 3347 3348 cpu = <&cpu3>; 3349 3350 clocks = <&aoss_qmp>; 3351 clock-names = "apb_pclk"; 3352 arm,coresight-loses-context-with-cpu; 3353 qcom,skip-power-up; 3354 3355 out-ports { 3356 port { 3357 etm3_out: endpoint { 3358 remote-endpoint = <&apss_funnel_in3>; 3359 }; 3360 }; 3361 }; 3362 }; 3363 3364 etm@7440000 { 3365 compatible = "arm,coresight-etm4x", "arm,primecell"; 3366 reg = <0 0x07440000 0 0x1000>; 3367 3368 cpu = <&cpu4>; 3369 3370 clocks = <&aoss_qmp>; 3371 clock-names = "apb_pclk"; 3372 arm,coresight-loses-context-with-cpu; 3373 qcom,skip-power-up; 3374 3375 out-ports { 3376 port { 3377 etm4_out: endpoint { 3378 remote-endpoint = <&apss_funnel_in4>; 3379 }; 3380 }; 3381 }; 3382 }; 3383 3384 etm@7540000 { 3385 compatible = "arm,coresight-etm4x", "arm,primecell"; 3386 reg = <0 0x07540000 0 0x1000>; 3387 3388 cpu = <&cpu5>; 3389 3390 clocks = <&aoss_qmp>; 3391 clock-names = "apb_pclk"; 3392 arm,coresight-loses-context-with-cpu; 3393 qcom,skip-power-up; 3394 3395 out-ports { 3396 port { 3397 etm5_out: endpoint { 3398 remote-endpoint = <&apss_funnel_in5>; 3399 }; 3400 }; 3401 }; 3402 }; 3403 3404 etm@7640000 { 3405 compatible = "arm,coresight-etm4x", "arm,primecell"; 3406 reg = <0 0x07640000 0 0x1000>; 3407 3408 cpu = <&cpu6>; 3409 3410 clocks = <&aoss_qmp>; 3411 clock-names = "apb_pclk"; 3412 arm,coresight-loses-context-with-cpu; 3413 qcom,skip-power-up; 3414 3415 out-ports { 3416 port { 3417 etm6_out: endpoint { 3418 remote-endpoint = <&apss_funnel_in6>; 3419 }; 3420 }; 3421 }; 3422 }; 3423 3424 etm@7740000 { 3425 compatible = "arm,coresight-etm4x", "arm,primecell"; 3426 reg = <0 0x07740000 0 0x1000>; 3427 3428 cpu = <&cpu7>; 3429 3430 clocks = <&aoss_qmp>; 3431 clock-names = "apb_pclk"; 3432 arm,coresight-loses-context-with-cpu; 3433 qcom,skip-power-up; 3434 3435 out-ports { 3436 port { 3437 etm7_out: endpoint { 3438 remote-endpoint = <&apss_funnel_in7>; 3439 }; 3440 }; 3441 }; 3442 }; 3443 3444 funnel@7800000 { /* APSS Funnel */ 3445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3446 reg = <0 0x07800000 0 0x1000>; 3447 3448 clocks = <&aoss_qmp>; 3449 clock-names = "apb_pclk"; 3450 3451 out-ports { 3452 port { 3453 apss_funnel_out: endpoint { 3454 remote-endpoint = <&apss_merge_funnel_in>; 3455 }; 3456 }; 3457 }; 3458 3459 in-ports { 3460 #address-cells = <1>; 3461 #size-cells = <0>; 3462 3463 port@0 { 3464 reg = <0>; 3465 apss_funnel_in0: endpoint { 3466 remote-endpoint = <&etm0_out>; 3467 }; 3468 }; 3469 3470 port@1 { 3471 reg = <1>; 3472 apss_funnel_in1: endpoint { 3473 remote-endpoint = <&etm1_out>; 3474 }; 3475 }; 3476 3477 port@2 { 3478 reg = <2>; 3479 apss_funnel_in2: endpoint { 3480 remote-endpoint = <&etm2_out>; 3481 }; 3482 }; 3483 3484 port@3 { 3485 reg = <3>; 3486 apss_funnel_in3: endpoint { 3487 remote-endpoint = <&etm3_out>; 3488 }; 3489 }; 3490 3491 port@4 { 3492 reg = <4>; 3493 apss_funnel_in4: endpoint { 3494 remote-endpoint = <&etm4_out>; 3495 }; 3496 }; 3497 3498 port@5 { 3499 reg = <5>; 3500 apss_funnel_in5: endpoint { 3501 remote-endpoint = <&etm5_out>; 3502 }; 3503 }; 3504 3505 port@6 { 3506 reg = <6>; 3507 apss_funnel_in6: endpoint { 3508 remote-endpoint = <&etm6_out>; 3509 }; 3510 }; 3511 3512 port@7 { 3513 reg = <7>; 3514 apss_funnel_in7: endpoint { 3515 remote-endpoint = <&etm7_out>; 3516 }; 3517 }; 3518 }; 3519 }; 3520 3521 funnel@7810000 { 3522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3523 reg = <0 0x07810000 0 0x1000>; 3524 3525 clocks = <&aoss_qmp>; 3526 clock-names = "apb_pclk"; 3527 3528 out-ports { 3529 port { 3530 apss_merge_funnel_out: endpoint { 3531 remote-endpoint = <&funnel1_in4>; 3532 }; 3533 }; 3534 }; 3535 3536 in-ports { 3537 port { 3538 apss_merge_funnel_in: endpoint { 3539 remote-endpoint = <&apss_funnel_out>; 3540 }; 3541 }; 3542 }; 3543 }; 3544 3545 sdhc_2: mmc@8804000 { 3546 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3547 pinctrl-names = "default", "sleep"; 3548 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3549 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3550 status = "disabled"; 3551 3552 reg = <0 0x08804000 0 0x1000>; 3553 3554 iommus = <&apps_smmu 0x100 0x0>; 3555 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3557 interrupt-names = "hc_irq", "pwr_irq"; 3558 3559 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3560 <&gcc GCC_SDCC2_APPS_CLK>, 3561 <&rpmhcc RPMH_CXO_CLK>; 3562 clock-names = "iface", "core", "xo"; 3563 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3565 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3566 power-domains = <&rpmhpd SC7280_CX>; 3567 operating-points-v2 = <&sdhc2_opp_table>; 3568 3569 bus-width = <4>; 3570 dma-coherent; 3571 3572 qcom,dll-config = <0x0007642c>; 3573 3574 resets = <&gcc GCC_SDCC2_BCR>; 3575 3576 sdhc2_opp_table: opp-table { 3577 compatible = "operating-points-v2"; 3578 3579 opp-100000000 { 3580 opp-hz = /bits/ 64 <100000000>; 3581 required-opps = <&rpmhpd_opp_low_svs>; 3582 opp-peak-kBps = <1800000 400000>; 3583 opp-avg-kBps = <100000 0>; 3584 }; 3585 3586 opp-202000000 { 3587 opp-hz = /bits/ 64 <202000000>; 3588 required-opps = <&rpmhpd_opp_nom>; 3589 opp-peak-kBps = <5400000 1600000>; 3590 opp-avg-kBps = <200000 0>; 3591 }; 3592 }; 3593 }; 3594 3595 usb_1_hsphy: phy@88e3000 { 3596 compatible = "qcom,sc7280-usb-hs-phy", 3597 "qcom,usb-snps-hs-7nm-phy"; 3598 reg = <0 0x088e3000 0 0x400>; 3599 status = "disabled"; 3600 #phy-cells = <0>; 3601 3602 clocks = <&rpmhcc RPMH_CXO_CLK>; 3603 clock-names = "ref"; 3604 3605 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3606 }; 3607 3608 usb_2_hsphy: phy@88e4000 { 3609 compatible = "qcom,sc7280-usb-hs-phy", 3610 "qcom,usb-snps-hs-7nm-phy"; 3611 reg = <0 0x088e4000 0 0x400>; 3612 status = "disabled"; 3613 #phy-cells = <0>; 3614 3615 clocks = <&rpmhcc RPMH_CXO_CLK>; 3616 clock-names = "ref"; 3617 3618 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3619 }; 3620 3621 usb_1_qmpphy: phy@88e8000 { 3622 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3623 reg = <0 0x088e8000 0 0x3000>; 3624 status = "disabled"; 3625 3626 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3627 <&rpmhcc RPMH_CXO_CLK>, 3628 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3629 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3630 clock-names = "aux", 3631 "ref", 3632 "com_aux", 3633 "usb3_pipe"; 3634 3635 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3636 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3637 reset-names = "phy", "common"; 3638 3639 #clock-cells = <1>; 3640 #phy-cells = <1>; 3641 3642 ports { 3643 #address-cells = <1>; 3644 #size-cells = <0>; 3645 3646 port@0 { 3647 reg = <0>; 3648 3649 usb_dp_qmpphy_out: endpoint { 3650 }; 3651 }; 3652 3653 port@1 { 3654 reg = <1>; 3655 3656 usb_dp_qmpphy_usb_ss_in: endpoint { 3657 }; 3658 }; 3659 3660 port@2 { 3661 reg = <2>; 3662 3663 usb_dp_qmpphy_dp_in: endpoint { 3664 }; 3665 }; 3666 }; 3667 }; 3668 3669 usb_2: usb@8cf8800 { 3670 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3671 reg = <0 0x08cf8800 0 0x400>; 3672 status = "disabled"; 3673 #address-cells = <2>; 3674 #size-cells = <2>; 3675 ranges; 3676 dma-ranges; 3677 3678 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3679 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3680 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3681 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3682 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3683 clock-names = "cfg_noc", 3684 "core", 3685 "iface", 3686 "sleep", 3687 "mock_utmi"; 3688 3689 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3690 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3691 assigned-clock-rates = <19200000>, <200000000>; 3692 3693 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3694 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3695 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3696 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3697 interrupt-names = "pwr_event", 3698 "hs_phy_irq", 3699 "dp_hs_phy_irq", 3700 "dm_hs_phy_irq"; 3701 3702 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3703 required-opps = <&rpmhpd_opp_nom>; 3704 3705 resets = <&gcc GCC_USB30_SEC_BCR>; 3706 3707 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3708 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3709 interconnect-names = "usb-ddr", "apps-usb"; 3710 3711 usb_2_dwc3: usb@8c00000 { 3712 compatible = "snps,dwc3"; 3713 reg = <0 0x08c00000 0 0xe000>; 3714 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3715 iommus = <&apps_smmu 0xa0 0x0>; 3716 snps,dis_u2_susphy_quirk; 3717 snps,dis_enblslpm_quirk; 3718 snps,dis-u1-entry-quirk; 3719 snps,dis-u2-entry-quirk; 3720 phys = <&usb_2_hsphy>; 3721 phy-names = "usb2-phy"; 3722 maximum-speed = "high-speed"; 3723 usb-role-switch; 3724 3725 port { 3726 usb2_role_switch: endpoint { 3727 remote-endpoint = <&eud_ep>; 3728 }; 3729 }; 3730 }; 3731 }; 3732 3733 qspi: spi@88dc000 { 3734 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3735 reg = <0 0x088dc000 0 0x1000>; 3736 iommus = <&apps_smmu 0x20 0x0>; 3737 #address-cells = <1>; 3738 #size-cells = <0>; 3739 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3740 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3741 <&gcc GCC_QSPI_CORE_CLK>; 3742 clock-names = "iface", "core"; 3743 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3744 &cnoc2 SLAVE_QSPI_0 0>; 3745 interconnect-names = "qspi-config"; 3746 power-domains = <&rpmhpd SC7280_CX>; 3747 operating-points-v2 = <&qspi_opp_table>; 3748 status = "disabled"; 3749 }; 3750 3751 remoteproc_adsp: remoteproc@3700000 { 3752 compatible = "qcom,sc7280-adsp-pas"; 3753 reg = <0 0x03700000 0 0x100>; 3754 3755 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3756 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3757 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3758 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3759 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3760 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3761 interrupt-names = "wdog", "fatal", "ready", "handover", 3762 "stop-ack", "shutdown-ack"; 3763 3764 clocks = <&rpmhcc RPMH_CXO_CLK>; 3765 clock-names = "xo"; 3766 3767 power-domains = <&rpmhpd SC7280_LCX>, 3768 <&rpmhpd SC7280_LMX>; 3769 power-domain-names = "lcx", "lmx"; 3770 3771 memory-region = <&adsp_mem>; 3772 3773 qcom,qmp = <&aoss_qmp>; 3774 3775 qcom,smem-states = <&adsp_smp2p_out 0>; 3776 qcom,smem-state-names = "stop"; 3777 3778 status = "disabled"; 3779 3780 glink-edge { 3781 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3782 IPCC_MPROC_SIGNAL_GLINK_QMP 3783 IRQ_TYPE_EDGE_RISING>; 3784 3785 mboxes = <&ipcc IPCC_CLIENT_LPASS 3786 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3787 3788 label = "lpass"; 3789 qcom,remote-pid = <2>; 3790 3791 apr { 3792 compatible = "qcom,apr-v2"; 3793 qcom,glink-channels = "apr_audio_svc"; 3794 qcom,domain = <APR_DOMAIN_ADSP>; 3795 #address-cells = <1>; 3796 #size-cells = <0>; 3797 3798 service@3 { 3799 reg = <APR_SVC_ADSP_CORE>; 3800 compatible = "qcom,q6core"; 3801 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3802 }; 3803 3804 q6afe: service@4 { 3805 compatible = "qcom,q6afe"; 3806 reg = <APR_SVC_AFE>; 3807 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3808 3809 q6afedai: dais { 3810 compatible = "qcom,q6afe-dais"; 3811 #address-cells = <1>; 3812 #size-cells = <0>; 3813 #sound-dai-cells = <1>; 3814 }; 3815 3816 q6afecc: clock-controller { 3817 compatible = "qcom,q6afe-clocks"; 3818 #clock-cells = <2>; 3819 }; 3820 }; 3821 3822 q6asm: service@7 { 3823 compatible = "qcom,q6asm"; 3824 reg = <APR_SVC_ASM>; 3825 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3826 3827 q6asmdai: dais { 3828 compatible = "qcom,q6asm-dais"; 3829 #address-cells = <1>; 3830 #size-cells = <0>; 3831 #sound-dai-cells = <1>; 3832 iommus = <&apps_smmu 0x1801 0x0>; 3833 3834 dai@0 { 3835 reg = <0>; 3836 }; 3837 3838 dai@1 { 3839 reg = <1>; 3840 }; 3841 3842 dai@2 { 3843 reg = <2>; 3844 }; 3845 }; 3846 }; 3847 3848 q6adm: service@8 { 3849 compatible = "qcom,q6adm"; 3850 reg = <APR_SVC_ADM>; 3851 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3852 3853 q6routing: routing { 3854 compatible = "qcom,q6adm-routing"; 3855 #sound-dai-cells = <0>; 3856 }; 3857 }; 3858 }; 3859 3860 fastrpc { 3861 compatible = "qcom,fastrpc"; 3862 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3863 label = "adsp"; 3864 qcom,non-secure-domain; 3865 #address-cells = <1>; 3866 #size-cells = <0>; 3867 3868 compute-cb@3 { 3869 compatible = "qcom,fastrpc-compute-cb"; 3870 reg = <3>; 3871 iommus = <&apps_smmu 0x1803 0x0>; 3872 }; 3873 3874 compute-cb@4 { 3875 compatible = "qcom,fastrpc-compute-cb"; 3876 reg = <4>; 3877 iommus = <&apps_smmu 0x1804 0x0>; 3878 }; 3879 3880 compute-cb@5 { 3881 compatible = "qcom,fastrpc-compute-cb"; 3882 reg = <5>; 3883 iommus = <&apps_smmu 0x1805 0x0>; 3884 }; 3885 }; 3886 }; 3887 }; 3888 3889 remoteproc_wpss: remoteproc@8a00000 { 3890 compatible = "qcom,sc7280-wpss-pas"; 3891 reg = <0 0x08a00000 0 0x10000>; 3892 3893 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3894 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3895 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3896 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3897 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3898 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3899 interrupt-names = "wdog", "fatal", "ready", "handover", 3900 "stop-ack", "shutdown-ack"; 3901 3902 clocks = <&rpmhcc RPMH_CXO_CLK>; 3903 clock-names = "xo"; 3904 3905 power-domains = <&rpmhpd SC7280_CX>, 3906 <&rpmhpd SC7280_MX>; 3907 power-domain-names = "cx", "mx"; 3908 3909 memory-region = <&wpss_mem>; 3910 3911 qcom,qmp = <&aoss_qmp>; 3912 3913 qcom,smem-states = <&wpss_smp2p_out 0>; 3914 qcom,smem-state-names = "stop"; 3915 3916 3917 status = "disabled"; 3918 3919 glink-edge { 3920 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3921 IPCC_MPROC_SIGNAL_GLINK_QMP 3922 IRQ_TYPE_EDGE_RISING>; 3923 mboxes = <&ipcc IPCC_CLIENT_WPSS 3924 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3925 3926 label = "wpss"; 3927 qcom,remote-pid = <13>; 3928 }; 3929 }; 3930 3931 pmu@9091000 { 3932 compatible = "qcom,sc7280-llcc-bwmon"; 3933 reg = <0 0x09091000 0 0x1000>; 3934 3935 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3936 3937 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3938 3939 operating-points-v2 = <&llcc_bwmon_opp_table>; 3940 3941 llcc_bwmon_opp_table: opp-table { 3942 compatible = "operating-points-v2"; 3943 3944 opp-0 { 3945 opp-peak-kBps = <800000>; 3946 }; 3947 opp-1 { 3948 opp-peak-kBps = <1804000>; 3949 }; 3950 opp-2 { 3951 opp-peak-kBps = <2188000>; 3952 }; 3953 opp-3 { 3954 opp-peak-kBps = <3072000>; 3955 }; 3956 opp-4 { 3957 opp-peak-kBps = <4068000>; 3958 }; 3959 opp-5 { 3960 opp-peak-kBps = <6220000>; 3961 }; 3962 opp-6 { 3963 opp-peak-kBps = <6832000>; 3964 }; 3965 opp-7 { 3966 opp-peak-kBps = <8532000>; 3967 }; 3968 }; 3969 }; 3970 3971 pmu@90b6400 { 3972 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3973 reg = <0 0x090b6400 0 0x600>; 3974 3975 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3976 3977 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3978 operating-points-v2 = <&cpu_bwmon_opp_table>; 3979 3980 cpu_bwmon_opp_table: opp-table { 3981 compatible = "operating-points-v2"; 3982 3983 opp-0 { 3984 opp-peak-kBps = <2400000>; 3985 }; 3986 opp-1 { 3987 opp-peak-kBps = <4800000>; 3988 }; 3989 opp-2 { 3990 opp-peak-kBps = <7456000>; 3991 }; 3992 opp-3 { 3993 opp-peak-kBps = <9600000>; 3994 }; 3995 opp-4 { 3996 opp-peak-kBps = <12896000>; 3997 }; 3998 opp-5 { 3999 opp-peak-kBps = <14928000>; 4000 }; 4001 opp-6 { 4002 opp-peak-kBps = <17056000>; 4003 }; 4004 }; 4005 }; 4006 4007 dc_noc: interconnect@90e0000 { 4008 reg = <0 0x090e0000 0 0x5080>; 4009 compatible = "qcom,sc7280-dc-noc"; 4010 #interconnect-cells = <2>; 4011 qcom,bcm-voters = <&apps_bcm_voter>; 4012 }; 4013 4014 gem_noc: interconnect@9100000 { 4015 reg = <0 0x09100000 0 0xe2200>; 4016 compatible = "qcom,sc7280-gem-noc"; 4017 #interconnect-cells = <2>; 4018 qcom,bcm-voters = <&apps_bcm_voter>; 4019 }; 4020 4021 system-cache-controller@9200000 { 4022 compatible = "qcom,sc7280-llcc"; 4023 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4024 <0 0x09600000 0 0x58000>; 4025 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4026 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4027 }; 4028 4029 eud: eud@88e0000 { 4030 compatible = "qcom,sc7280-eud", "qcom,eud"; 4031 reg = <0 0x88e0000 0 0x2000>, 4032 <0 0x88e2000 0 0x1000>; 4033 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4034 4035 status = "disabled"; 4036 4037 ports { 4038 #address-cells = <1>; 4039 #size-cells = <0>; 4040 4041 port@0 { 4042 reg = <0>; 4043 eud_ep: endpoint { 4044 remote-endpoint = <&usb2_role_switch>; 4045 }; 4046 }; 4047 }; 4048 }; 4049 4050 nsp_noc: interconnect@a0c0000 { 4051 reg = <0 0x0a0c0000 0 0x10000>; 4052 compatible = "qcom,sc7280-nsp-noc"; 4053 #interconnect-cells = <2>; 4054 qcom,bcm-voters = <&apps_bcm_voter>; 4055 }; 4056 4057 remoteproc_cdsp: remoteproc@a300000 { 4058 compatible = "qcom,sc7280-cdsp-pas"; 4059 reg = <0 0x0a300000 0 0x10000>; 4060 4061 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4062 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4063 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4064 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4065 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4066 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4067 interrupt-names = "wdog", "fatal", "ready", "handover", 4068 "stop-ack", "shutdown-ack"; 4069 4070 clocks = <&rpmhcc RPMH_CXO_CLK>; 4071 clock-names = "xo"; 4072 4073 power-domains = <&rpmhpd SC7280_CX>, 4074 <&rpmhpd SC7280_MX>; 4075 power-domain-names = "cx", "mx"; 4076 4077 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4078 4079 memory-region = <&cdsp_mem>; 4080 4081 qcom,qmp = <&aoss_qmp>; 4082 4083 qcom,smem-states = <&cdsp_smp2p_out 0>; 4084 qcom,smem-state-names = "stop"; 4085 4086 status = "disabled"; 4087 4088 glink-edge { 4089 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4090 IPCC_MPROC_SIGNAL_GLINK_QMP 4091 IRQ_TYPE_EDGE_RISING>; 4092 mboxes = <&ipcc IPCC_CLIENT_CDSP 4093 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4094 4095 label = "cdsp"; 4096 qcom,remote-pid = <5>; 4097 4098 fastrpc { 4099 compatible = "qcom,fastrpc"; 4100 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4101 label = "cdsp"; 4102 qcom,non-secure-domain; 4103 #address-cells = <1>; 4104 #size-cells = <0>; 4105 4106 compute-cb@1 { 4107 compatible = "qcom,fastrpc-compute-cb"; 4108 reg = <1>; 4109 iommus = <&apps_smmu 0x11a1 0x0420>, 4110 <&apps_smmu 0x1181 0x0420>; 4111 }; 4112 4113 compute-cb@2 { 4114 compatible = "qcom,fastrpc-compute-cb"; 4115 reg = <2>; 4116 iommus = <&apps_smmu 0x11a2 0x0420>, 4117 <&apps_smmu 0x1182 0x0420>; 4118 }; 4119 4120 compute-cb@3 { 4121 compatible = "qcom,fastrpc-compute-cb"; 4122 reg = <3>; 4123 iommus = <&apps_smmu 0x11a3 0x0420>, 4124 <&apps_smmu 0x1183 0x0420>; 4125 }; 4126 4127 compute-cb@4 { 4128 compatible = "qcom,fastrpc-compute-cb"; 4129 reg = <4>; 4130 iommus = <&apps_smmu 0x11a4 0x0420>, 4131 <&apps_smmu 0x1184 0x0420>; 4132 }; 4133 4134 compute-cb@5 { 4135 compatible = "qcom,fastrpc-compute-cb"; 4136 reg = <5>; 4137 iommus = <&apps_smmu 0x11a5 0x0420>, 4138 <&apps_smmu 0x1185 0x0420>; 4139 }; 4140 4141 compute-cb@6 { 4142 compatible = "qcom,fastrpc-compute-cb"; 4143 reg = <6>; 4144 iommus = <&apps_smmu 0x11a6 0x0420>, 4145 <&apps_smmu 0x1186 0x0420>; 4146 }; 4147 4148 compute-cb@7 { 4149 compatible = "qcom,fastrpc-compute-cb"; 4150 reg = <7>; 4151 iommus = <&apps_smmu 0x11a7 0x0420>, 4152 <&apps_smmu 0x1187 0x0420>; 4153 }; 4154 4155 compute-cb@8 { 4156 compatible = "qcom,fastrpc-compute-cb"; 4157 reg = <8>; 4158 iommus = <&apps_smmu 0x11a8 0x0420>, 4159 <&apps_smmu 0x1188 0x0420>; 4160 }; 4161 4162 /* note: secure cb9 in downstream */ 4163 4164 compute-cb@11 { 4165 compatible = "qcom,fastrpc-compute-cb"; 4166 reg = <11>; 4167 iommus = <&apps_smmu 0x11ab 0x0420>, 4168 <&apps_smmu 0x118b 0x0420>; 4169 }; 4170 4171 compute-cb@12 { 4172 compatible = "qcom,fastrpc-compute-cb"; 4173 reg = <12>; 4174 iommus = <&apps_smmu 0x11ac 0x0420>, 4175 <&apps_smmu 0x118c 0x0420>; 4176 }; 4177 4178 compute-cb@13 { 4179 compatible = "qcom,fastrpc-compute-cb"; 4180 reg = <13>; 4181 iommus = <&apps_smmu 0x11ad 0x0420>, 4182 <&apps_smmu 0x118d 0x0420>; 4183 }; 4184 4185 compute-cb@14 { 4186 compatible = "qcom,fastrpc-compute-cb"; 4187 reg = <14>; 4188 iommus = <&apps_smmu 0x11ae 0x0420>, 4189 <&apps_smmu 0x118e 0x0420>; 4190 }; 4191 }; 4192 }; 4193 }; 4194 4195 usb_1: usb@a6f8800 { 4196 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4197 reg = <0 0x0a6f8800 0 0x400>; 4198 status = "disabled"; 4199 #address-cells = <2>; 4200 #size-cells = <2>; 4201 ranges; 4202 dma-ranges; 4203 4204 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4205 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4206 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4207 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4208 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4209 clock-names = "cfg_noc", 4210 "core", 4211 "iface", 4212 "sleep", 4213 "mock_utmi"; 4214 4215 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4216 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4217 assigned-clock-rates = <19200000>, <200000000>; 4218 4219 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4220 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4221 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4222 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4223 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4224 interrupt-names = "pwr_event", 4225 "hs_phy_irq", 4226 "dp_hs_phy_irq", 4227 "dm_hs_phy_irq", 4228 "ss_phy_irq"; 4229 4230 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4231 required-opps = <&rpmhpd_opp_nom>; 4232 4233 resets = <&gcc GCC_USB30_PRIM_BCR>; 4234 4235 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4236 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4237 interconnect-names = "usb-ddr", "apps-usb"; 4238 4239 wakeup-source; 4240 4241 usb_1_dwc3: usb@a600000 { 4242 compatible = "snps,dwc3"; 4243 reg = <0 0x0a600000 0 0xe000>; 4244 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4245 iommus = <&apps_smmu 0xe0 0x0>; 4246 snps,dis_u2_susphy_quirk; 4247 snps,dis_enblslpm_quirk; 4248 snps,parkmode-disable-ss-quirk; 4249 snps,dis-u1-entry-quirk; 4250 snps,dis-u2-entry-quirk; 4251 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4252 phy-names = "usb2-phy", "usb3-phy"; 4253 maximum-speed = "super-speed"; 4254 4255 ports { 4256 #address-cells = <1>; 4257 #size-cells = <0>; 4258 4259 port@0 { 4260 reg = <0>; 4261 4262 usb_1_dwc3_hs: endpoint { 4263 }; 4264 }; 4265 4266 port@1 { 4267 reg = <1>; 4268 4269 usb_1_dwc3_ss: endpoint { 4270 }; 4271 }; 4272 }; 4273 }; 4274 }; 4275 4276 venus: video-codec@aa00000 { 4277 compatible = "qcom,sc7280-venus"; 4278 reg = <0 0x0aa00000 0 0xd0600>; 4279 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4280 4281 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4282 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4283 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4284 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4285 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4286 clock-names = "core", "bus", "iface", 4287 "vcodec_core", "vcodec_bus"; 4288 4289 power-domains = <&videocc MVSC_GDSC>, 4290 <&videocc MVS0_GDSC>, 4291 <&rpmhpd SC7280_CX>; 4292 power-domain-names = "venus", "vcodec0", "cx"; 4293 operating-points-v2 = <&venus_opp_table>; 4294 4295 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4296 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4297 interconnect-names = "cpu-cfg", "video-mem"; 4298 4299 iommus = <&apps_smmu 0x2180 0x20>; 4300 memory-region = <&video_mem>; 4301 4302 status = "disabled"; 4303 4304 video-decoder { 4305 compatible = "venus-decoder"; 4306 }; 4307 4308 video-encoder { 4309 compatible = "venus-encoder"; 4310 }; 4311 4312 venus_opp_table: opp-table { 4313 compatible = "operating-points-v2"; 4314 4315 opp-133330000 { 4316 opp-hz = /bits/ 64 <133330000>; 4317 required-opps = <&rpmhpd_opp_low_svs>; 4318 }; 4319 4320 opp-240000000 { 4321 opp-hz = /bits/ 64 <240000000>; 4322 required-opps = <&rpmhpd_opp_svs>; 4323 }; 4324 4325 opp-335000000 { 4326 opp-hz = /bits/ 64 <335000000>; 4327 required-opps = <&rpmhpd_opp_svs_l1>; 4328 }; 4329 4330 opp-424000000 { 4331 opp-hz = /bits/ 64 <424000000>; 4332 required-opps = <&rpmhpd_opp_nom>; 4333 }; 4334 4335 opp-460000048 { 4336 opp-hz = /bits/ 64 <460000048>; 4337 required-opps = <&rpmhpd_opp_turbo>; 4338 }; 4339 }; 4340 }; 4341 4342 videocc: clock-controller@aaf0000 { 4343 compatible = "qcom,sc7280-videocc"; 4344 reg = <0 0x0aaf0000 0 0x10000>; 4345 clocks = <&rpmhcc RPMH_CXO_CLK>, 4346 <&rpmhcc RPMH_CXO_CLK_A>; 4347 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4348 #clock-cells = <1>; 4349 #reset-cells = <1>; 4350 #power-domain-cells = <1>; 4351 }; 4352 4353 cci0: cci@ac4a000 { 4354 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4355 reg = <0 0x0ac4a000 0 0x1000>; 4356 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4357 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4358 4359 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4360 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4361 <&camcc CAM_CC_CPAS_AHB_CLK>, 4362 <&camcc CAM_CC_CCI_0_CLK>, 4363 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4364 clock-names = "camnoc_axi", 4365 "slow_ahb_src", 4366 "cpas_ahb", 4367 "cci", 4368 "cci_src"; 4369 pinctrl-0 = <&cci0_default &cci1_default>; 4370 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4371 pinctrl-names = "default", "sleep"; 4372 4373 #address-cells = <1>; 4374 #size-cells = <0>; 4375 4376 status = "disabled"; 4377 4378 cci0_i2c0: i2c-bus@0 { 4379 reg = <0>; 4380 clock-frequency = <1000000>; 4381 #address-cells = <1>; 4382 #size-cells = <0>; 4383 }; 4384 4385 cci0_i2c1: i2c-bus@1 { 4386 reg = <1>; 4387 clock-frequency = <1000000>; 4388 #address-cells = <1>; 4389 #size-cells = <0>; 4390 }; 4391 }; 4392 4393 cci1: cci@ac4b000 { 4394 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4395 reg = <0 0x0ac4b000 0 0x1000>; 4396 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4397 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4398 4399 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4400 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4401 <&camcc CAM_CC_CPAS_AHB_CLK>, 4402 <&camcc CAM_CC_CCI_1_CLK>, 4403 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4404 clock-names = "camnoc_axi", 4405 "slow_ahb_src", 4406 "cpas_ahb", 4407 "cci", 4408 "cci_src"; 4409 pinctrl-0 = <&cci2_default &cci3_default>; 4410 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4411 pinctrl-names = "default", "sleep"; 4412 4413 #address-cells = <1>; 4414 #size-cells = <0>; 4415 4416 status = "disabled"; 4417 4418 cci1_i2c0: i2c-bus@0 { 4419 reg = <0>; 4420 clock-frequency = <1000000>; 4421 #address-cells = <1>; 4422 #size-cells = <0>; 4423 }; 4424 4425 cci1_i2c1: i2c-bus@1 { 4426 reg = <1>; 4427 clock-frequency = <1000000>; 4428 #address-cells = <1>; 4429 #size-cells = <0>; 4430 }; 4431 }; 4432 4433 camcc: clock-controller@ad00000 { 4434 compatible = "qcom,sc7280-camcc"; 4435 reg = <0 0x0ad00000 0 0x10000>; 4436 clocks = <&rpmhcc RPMH_CXO_CLK>, 4437 <&rpmhcc RPMH_CXO_CLK_A>, 4438 <&sleep_clk>; 4439 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4440 #clock-cells = <1>; 4441 #reset-cells = <1>; 4442 #power-domain-cells = <1>; 4443 }; 4444 4445 dispcc: clock-controller@af00000 { 4446 compatible = "qcom,sc7280-dispcc"; 4447 reg = <0 0x0af00000 0 0x20000>; 4448 clocks = <&rpmhcc RPMH_CXO_CLK>, 4449 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4450 <&mdss_dsi_phy 0>, 4451 <&mdss_dsi_phy 1>, 4452 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4453 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4454 <&mdss_edp_phy 0>, 4455 <&mdss_edp_phy 1>; 4456 clock-names = "bi_tcxo", 4457 "gcc_disp_gpll0_clk", 4458 "dsi0_phy_pll_out_byteclk", 4459 "dsi0_phy_pll_out_dsiclk", 4460 "dp_phy_pll_link_clk", 4461 "dp_phy_pll_vco_div_clk", 4462 "edp_phy_pll_link_clk", 4463 "edp_phy_pll_vco_div_clk"; 4464 #clock-cells = <1>; 4465 #reset-cells = <1>; 4466 #power-domain-cells = <1>; 4467 }; 4468 4469 mdss: display-subsystem@ae00000 { 4470 compatible = "qcom,sc7280-mdss"; 4471 reg = <0 0x0ae00000 0 0x1000>; 4472 reg-names = "mdss"; 4473 4474 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4475 4476 clocks = <&gcc GCC_DISP_AHB_CLK>, 4477 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4478 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4479 clock-names = "iface", 4480 "ahb", 4481 "core"; 4482 4483 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4484 interrupt-controller; 4485 #interrupt-cells = <1>; 4486 4487 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4489 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4490 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4491 interconnect-names = "mdp0-mem", 4492 "cpu-cfg"; 4493 4494 iommus = <&apps_smmu 0x900 0x402>; 4495 4496 #address-cells = <2>; 4497 #size-cells = <2>; 4498 ranges; 4499 4500 status = "disabled"; 4501 4502 mdss_mdp: display-controller@ae01000 { 4503 compatible = "qcom,sc7280-dpu"; 4504 reg = <0 0x0ae01000 0 0x8f030>, 4505 <0 0x0aeb0000 0 0x2008>; 4506 reg-names = "mdp", "vbif"; 4507 4508 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4509 <&gcc GCC_DISP_SF_AXI_CLK>, 4510 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4511 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4512 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4513 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4514 clock-names = "bus", 4515 "nrt_bus", 4516 "iface", 4517 "lut", 4518 "core", 4519 "vsync"; 4520 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4521 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4522 assigned-clock-rates = <19200000>, 4523 <19200000>; 4524 operating-points-v2 = <&mdp_opp_table>; 4525 power-domains = <&rpmhpd SC7280_CX>; 4526 4527 interrupt-parent = <&mdss>; 4528 interrupts = <0>; 4529 4530 ports { 4531 #address-cells = <1>; 4532 #size-cells = <0>; 4533 4534 port@0 { 4535 reg = <0>; 4536 dpu_intf1_out: endpoint { 4537 remote-endpoint = <&mdss_dsi0_in>; 4538 }; 4539 }; 4540 4541 port@1 { 4542 reg = <1>; 4543 dpu_intf5_out: endpoint { 4544 remote-endpoint = <&edp_in>; 4545 }; 4546 }; 4547 4548 port@2 { 4549 reg = <2>; 4550 dpu_intf0_out: endpoint { 4551 remote-endpoint = <&dp_in>; 4552 }; 4553 }; 4554 }; 4555 4556 mdp_opp_table: opp-table { 4557 compatible = "operating-points-v2"; 4558 4559 opp-200000000 { 4560 opp-hz = /bits/ 64 <200000000>; 4561 required-opps = <&rpmhpd_opp_low_svs>; 4562 }; 4563 4564 opp-300000000 { 4565 opp-hz = /bits/ 64 <300000000>; 4566 required-opps = <&rpmhpd_opp_svs>; 4567 }; 4568 4569 opp-380000000 { 4570 opp-hz = /bits/ 64 <380000000>; 4571 required-opps = <&rpmhpd_opp_svs_l1>; 4572 }; 4573 4574 opp-506666667 { 4575 opp-hz = /bits/ 64 <506666667>; 4576 required-opps = <&rpmhpd_opp_nom>; 4577 }; 4578 4579 opp-608000000 { 4580 opp-hz = /bits/ 64 <608000000>; 4581 required-opps = <&rpmhpd_opp_turbo>; 4582 }; 4583 }; 4584 }; 4585 4586 mdss_dsi: dsi@ae94000 { 4587 compatible = "qcom,sc7280-dsi-ctrl", 4588 "qcom,mdss-dsi-ctrl"; 4589 reg = <0 0x0ae94000 0 0x400>; 4590 reg-names = "dsi_ctrl"; 4591 4592 interrupt-parent = <&mdss>; 4593 interrupts = <4>; 4594 4595 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4596 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4597 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4598 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4599 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4600 <&gcc GCC_DISP_HF_AXI_CLK>; 4601 clock-names = "byte", 4602 "byte_intf", 4603 "pixel", 4604 "core", 4605 "iface", 4606 "bus"; 4607 4608 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4609 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 4610 4611 operating-points-v2 = <&dsi_opp_table>; 4612 power-domains = <&rpmhpd SC7280_CX>; 4613 4614 phys = <&mdss_dsi_phy>; 4615 4616 #address-cells = <1>; 4617 #size-cells = <0>; 4618 4619 status = "disabled"; 4620 4621 ports { 4622 #address-cells = <1>; 4623 #size-cells = <0>; 4624 4625 port@0 { 4626 reg = <0>; 4627 mdss_dsi0_in: endpoint { 4628 remote-endpoint = <&dpu_intf1_out>; 4629 }; 4630 }; 4631 4632 port@1 { 4633 reg = <1>; 4634 mdss_dsi0_out: endpoint { 4635 }; 4636 }; 4637 }; 4638 4639 dsi_opp_table: opp-table { 4640 compatible = "operating-points-v2"; 4641 4642 opp-187500000 { 4643 opp-hz = /bits/ 64 <187500000>; 4644 required-opps = <&rpmhpd_opp_low_svs>; 4645 }; 4646 4647 opp-300000000 { 4648 opp-hz = /bits/ 64 <300000000>; 4649 required-opps = <&rpmhpd_opp_svs>; 4650 }; 4651 4652 opp-358000000 { 4653 opp-hz = /bits/ 64 <358000000>; 4654 required-opps = <&rpmhpd_opp_svs_l1>; 4655 }; 4656 }; 4657 }; 4658 4659 mdss_dsi_phy: phy@ae94400 { 4660 compatible = "qcom,sc7280-dsi-phy-7nm"; 4661 reg = <0 0x0ae94400 0 0x200>, 4662 <0 0x0ae94600 0 0x280>, 4663 <0 0x0ae94900 0 0x280>; 4664 reg-names = "dsi_phy", 4665 "dsi_phy_lane", 4666 "dsi_pll"; 4667 4668 #clock-cells = <1>; 4669 #phy-cells = <0>; 4670 4671 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4672 <&rpmhcc RPMH_CXO_CLK>; 4673 clock-names = "iface", "ref"; 4674 4675 status = "disabled"; 4676 }; 4677 4678 mdss_edp: edp@aea0000 { 4679 compatible = "qcom,sc7280-edp"; 4680 pinctrl-names = "default"; 4681 pinctrl-0 = <&edp_hot_plug_det>; 4682 4683 reg = <0 0x0aea0000 0 0x200>, 4684 <0 0x0aea0200 0 0x200>, 4685 <0 0x0aea0400 0 0xc00>, 4686 <0 0x0aea1000 0 0x400>; 4687 4688 interrupt-parent = <&mdss>; 4689 interrupts = <14>; 4690 4691 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4692 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4693 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4694 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4695 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4696 clock-names = "core_iface", 4697 "core_aux", 4698 "ctrl_link", 4699 "ctrl_link_iface", 4700 "stream_pixel"; 4701 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4702 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4703 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4704 4705 phys = <&mdss_edp_phy>; 4706 phy-names = "dp"; 4707 4708 operating-points-v2 = <&edp_opp_table>; 4709 power-domains = <&rpmhpd SC7280_CX>; 4710 4711 status = "disabled"; 4712 4713 ports { 4714 #address-cells = <1>; 4715 #size-cells = <0>; 4716 4717 port@0 { 4718 reg = <0>; 4719 edp_in: endpoint { 4720 remote-endpoint = <&dpu_intf5_out>; 4721 }; 4722 }; 4723 4724 port@1 { 4725 reg = <1>; 4726 mdss_edp_out: endpoint { }; 4727 }; 4728 }; 4729 4730 edp_opp_table: opp-table { 4731 compatible = "operating-points-v2"; 4732 4733 opp-160000000 { 4734 opp-hz = /bits/ 64 <160000000>; 4735 required-opps = <&rpmhpd_opp_low_svs>; 4736 }; 4737 4738 opp-270000000 { 4739 opp-hz = /bits/ 64 <270000000>; 4740 required-opps = <&rpmhpd_opp_svs>; 4741 }; 4742 4743 opp-540000000 { 4744 opp-hz = /bits/ 64 <540000000>; 4745 required-opps = <&rpmhpd_opp_nom>; 4746 }; 4747 4748 opp-810000000 { 4749 opp-hz = /bits/ 64 <810000000>; 4750 required-opps = <&rpmhpd_opp_nom>; 4751 }; 4752 }; 4753 }; 4754 4755 mdss_edp_phy: phy@aec2a00 { 4756 compatible = "qcom,sc7280-edp-phy"; 4757 4758 reg = <0 0x0aec2a00 0 0x19c>, 4759 <0 0x0aec2200 0 0xa0>, 4760 <0 0x0aec2600 0 0xa0>, 4761 <0 0x0aec2000 0 0x1c0>; 4762 4763 clocks = <&rpmhcc RPMH_CXO_CLK>, 4764 <&gcc GCC_EDP_CLKREF_EN>; 4765 clock-names = "aux", 4766 "cfg_ahb"; 4767 4768 #clock-cells = <1>; 4769 #phy-cells = <0>; 4770 4771 status = "disabled"; 4772 }; 4773 4774 mdss_dp: displayport-controller@ae90000 { 4775 compatible = "qcom,sc7280-dp"; 4776 4777 reg = <0 0x0ae90000 0 0x200>, 4778 <0 0x0ae90200 0 0x200>, 4779 <0 0x0ae90400 0 0xc00>, 4780 <0 0x0ae91000 0 0x400>, 4781 <0 0x0ae91400 0 0x400>; 4782 4783 interrupt-parent = <&mdss>; 4784 interrupts = <12>; 4785 4786 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4787 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4788 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4789 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4790 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4791 clock-names = "core_iface", 4792 "core_aux", 4793 "ctrl_link", 4794 "ctrl_link_iface", 4795 "stream_pixel"; 4796 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4797 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4798 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4799 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4800 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4801 phy-names = "dp"; 4802 4803 operating-points-v2 = <&dp_opp_table>; 4804 power-domains = <&rpmhpd SC7280_CX>; 4805 4806 #sound-dai-cells = <0>; 4807 4808 status = "disabled"; 4809 4810 ports { 4811 #address-cells = <1>; 4812 #size-cells = <0>; 4813 4814 port@0 { 4815 reg = <0>; 4816 dp_in: endpoint { 4817 remote-endpoint = <&dpu_intf0_out>; 4818 }; 4819 }; 4820 4821 port@1 { 4822 reg = <1>; 4823 mdss_dp_out: endpoint { }; 4824 }; 4825 }; 4826 4827 dp_opp_table: opp-table { 4828 compatible = "operating-points-v2"; 4829 4830 opp-160000000 { 4831 opp-hz = /bits/ 64 <160000000>; 4832 required-opps = <&rpmhpd_opp_low_svs>; 4833 }; 4834 4835 opp-270000000 { 4836 opp-hz = /bits/ 64 <270000000>; 4837 required-opps = <&rpmhpd_opp_svs>; 4838 }; 4839 4840 opp-540000000 { 4841 opp-hz = /bits/ 64 <540000000>; 4842 required-opps = <&rpmhpd_opp_svs_l1>; 4843 }; 4844 4845 opp-810000000 { 4846 opp-hz = /bits/ 64 <810000000>; 4847 required-opps = <&rpmhpd_opp_nom>; 4848 }; 4849 }; 4850 }; 4851 }; 4852 4853 pdc: interrupt-controller@b220000 { 4854 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4855 reg = <0 0x0b220000 0 0x30000>; 4856 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4857 <55 306 4>, <59 312 3>, <62 374 2>, 4858 <64 434 2>, <66 438 3>, <69 86 1>, 4859 <70 520 54>, <124 609 31>, <155 63 1>, 4860 <156 716 12>; 4861 #interrupt-cells = <2>; 4862 interrupt-parent = <&intc>; 4863 interrupt-controller; 4864 }; 4865 4866 pdc_reset: reset-controller@b5e0000 { 4867 compatible = "qcom,sc7280-pdc-global"; 4868 reg = <0 0x0b5e0000 0 0x20000>; 4869 #reset-cells = <1>; 4870 status = "reserved"; /* Owned by firmware */ 4871 }; 4872 4873 tsens0: thermal-sensor@c263000 { 4874 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4875 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4876 <0 0x0c222000 0 0x1ff>; /* SROT */ 4877 #qcom,sensors = <15>; 4878 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4880 interrupt-names = "uplow","critical"; 4881 #thermal-sensor-cells = <1>; 4882 }; 4883 4884 tsens1: thermal-sensor@c265000 { 4885 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4886 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4887 <0 0x0c223000 0 0x1ff>; /* SROT */ 4888 #qcom,sensors = <12>; 4889 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4890 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4891 interrupt-names = "uplow","critical"; 4892 #thermal-sensor-cells = <1>; 4893 }; 4894 4895 aoss_reset: reset-controller@c2a0000 { 4896 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4897 reg = <0 0x0c2a0000 0 0x31000>; 4898 #reset-cells = <1>; 4899 }; 4900 4901 aoss_qmp: power-management@c300000 { 4902 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4903 reg = <0 0x0c300000 0 0x400>; 4904 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4905 IPCC_MPROC_SIGNAL_GLINK_QMP 4906 IRQ_TYPE_EDGE_RISING>; 4907 mboxes = <&ipcc IPCC_CLIENT_AOP 4908 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4909 4910 #clock-cells = <0>; 4911 }; 4912 4913 sram@c3f0000 { 4914 compatible = "qcom,rpmh-stats"; 4915 reg = <0 0x0c3f0000 0 0x400>; 4916 }; 4917 4918 spmi_bus: spmi@c440000 { 4919 compatible = "qcom,spmi-pmic-arb"; 4920 reg = <0 0x0c440000 0 0x1100>, 4921 <0 0x0c600000 0 0x2000000>, 4922 <0 0x0e600000 0 0x100000>, 4923 <0 0x0e700000 0 0xa0000>, 4924 <0 0x0c40a000 0 0x26000>; 4925 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4926 interrupt-names = "periph_irq"; 4927 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4928 qcom,ee = <0>; 4929 qcom,channel = <0>; 4930 #address-cells = <2>; 4931 #size-cells = <0>; 4932 interrupt-controller; 4933 #interrupt-cells = <4>; 4934 }; 4935 4936 tlmm: pinctrl@f100000 { 4937 compatible = "qcom,sc7280-pinctrl"; 4938 reg = <0 0x0f100000 0 0x300000>; 4939 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4940 gpio-controller; 4941 #gpio-cells = <2>; 4942 interrupt-controller; 4943 #interrupt-cells = <2>; 4944 gpio-ranges = <&tlmm 0 0 175>; 4945 wakeup-parent = <&pdc>; 4946 4947 cci0_default: cci0-default-state { 4948 pins = "gpio69", "gpio70"; 4949 function = "cci_i2c"; 4950 drive-strength = <2>; 4951 bias-pull-up; 4952 }; 4953 4954 cci0_sleep: cci0-sleep-state { 4955 pins = "gpio69", "gpio70"; 4956 function = "cci_i2c"; 4957 drive-strength = <2>; 4958 bias-pull-down; 4959 }; 4960 4961 cci1_default: cci1-default-state { 4962 pins = "gpio71", "gpio72"; 4963 function = "cci_i2c"; 4964 drive-strength = <2>; 4965 bias-pull-up; 4966 }; 4967 4968 cci1_sleep: cci1-sleep-state { 4969 pins = "gpio71", "gpio72"; 4970 function = "cci_i2c"; 4971 drive-strength = <2>; 4972 bias-pull-down; 4973 }; 4974 4975 cci2_default: cci2-default-state { 4976 pins = "gpio73", "gpio74"; 4977 function = "cci_i2c"; 4978 drive-strength = <2>; 4979 bias-pull-up; 4980 }; 4981 4982 cci2_sleep: cci2-sleep-state { 4983 pins = "gpio73", "gpio74"; 4984 function = "cci_i2c"; 4985 drive-strength = <2>; 4986 bias-pull-down; 4987 }; 4988 4989 cci3_default: cci3-default-state { 4990 pins = "gpio75", "gpio76"; 4991 function = "cci_i2c"; 4992 drive-strength = <2>; 4993 bias-pull-up; 4994 }; 4995 4996 cci3_sleep: cci3-sleep-state { 4997 pins = "gpio75", "gpio76"; 4998 function = "cci_i2c"; 4999 drive-strength = <2>; 5000 bias-pull-down; 5001 }; 5002 5003 dp_hot_plug_det: dp-hot-plug-det-state { 5004 pins = "gpio47"; 5005 function = "dp_hot"; 5006 }; 5007 5008 edp_hot_plug_det: edp-hot-plug-det-state { 5009 pins = "gpio60"; 5010 function = "edp_hot"; 5011 }; 5012 5013 mi2s0_data0: mi2s0-data0-state { 5014 pins = "gpio98"; 5015 function = "mi2s0_data0"; 5016 }; 5017 5018 mi2s0_data1: mi2s0-data1-state { 5019 pins = "gpio99"; 5020 function = "mi2s0_data1"; 5021 }; 5022 5023 mi2s0_mclk: mi2s0-mclk-state { 5024 pins = "gpio96"; 5025 function = "pri_mi2s"; 5026 }; 5027 5028 mi2s0_sclk: mi2s0-sclk-state { 5029 pins = "gpio97"; 5030 function = "mi2s0_sck"; 5031 }; 5032 5033 mi2s0_ws: mi2s0-ws-state { 5034 pins = "gpio100"; 5035 function = "mi2s0_ws"; 5036 }; 5037 5038 mi2s1_data0: mi2s1-data0-state { 5039 pins = "gpio107"; 5040 function = "mi2s1_data0"; 5041 }; 5042 5043 mi2s1_sclk: mi2s1-sclk-state { 5044 pins = "gpio106"; 5045 function = "mi2s1_sck"; 5046 }; 5047 5048 mi2s1_ws: mi2s1-ws-state { 5049 pins = "gpio108"; 5050 function = "mi2s1_ws"; 5051 }; 5052 5053 pcie1_clkreq_n: pcie1-clkreq-n-state { 5054 pins = "gpio79"; 5055 function = "pcie1_clkreqn"; 5056 }; 5057 5058 qspi_clk: qspi-clk-state { 5059 pins = "gpio14"; 5060 function = "qspi_clk"; 5061 }; 5062 5063 qspi_cs0: qspi-cs0-state { 5064 pins = "gpio15"; 5065 function = "qspi_cs"; 5066 }; 5067 5068 qspi_cs1: qspi-cs1-state { 5069 pins = "gpio19"; 5070 function = "qspi_cs"; 5071 }; 5072 5073 qspi_data0: qspi-data0-state { 5074 pins = "gpio12"; 5075 function = "qspi_data"; 5076 }; 5077 5078 qspi_data1: qspi-data1-state { 5079 pins = "gpio13"; 5080 function = "qspi_data"; 5081 }; 5082 5083 qspi_data23: qspi-data23-state { 5084 pins = "gpio16", "gpio17"; 5085 function = "qspi_data"; 5086 }; 5087 5088 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5089 pins = "gpio0", "gpio1"; 5090 function = "qup00"; 5091 }; 5092 5093 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5094 pins = "gpio4", "gpio5"; 5095 function = "qup01"; 5096 }; 5097 5098 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5099 pins = "gpio8", "gpio9"; 5100 function = "qup02"; 5101 }; 5102 5103 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5104 pins = "gpio12", "gpio13"; 5105 function = "qup03"; 5106 }; 5107 5108 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5109 pins = "gpio16", "gpio17"; 5110 function = "qup04"; 5111 }; 5112 5113 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5114 pins = "gpio20", "gpio21"; 5115 function = "qup05"; 5116 }; 5117 5118 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5119 pins = "gpio24", "gpio25"; 5120 function = "qup06"; 5121 }; 5122 5123 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5124 pins = "gpio28", "gpio29"; 5125 function = "qup07"; 5126 }; 5127 5128 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5129 pins = "gpio32", "gpio33"; 5130 function = "qup10"; 5131 }; 5132 5133 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5134 pins = "gpio36", "gpio37"; 5135 function = "qup11"; 5136 }; 5137 5138 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5139 pins = "gpio40", "gpio41"; 5140 function = "qup12"; 5141 }; 5142 5143 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5144 pins = "gpio44", "gpio45"; 5145 function = "qup13"; 5146 }; 5147 5148 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5149 pins = "gpio48", "gpio49"; 5150 function = "qup14"; 5151 }; 5152 5153 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5154 pins = "gpio52", "gpio53"; 5155 function = "qup15"; 5156 }; 5157 5158 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5159 pins = "gpio56", "gpio57"; 5160 function = "qup16"; 5161 }; 5162 5163 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5164 pins = "gpio60", "gpio61"; 5165 function = "qup17"; 5166 }; 5167 5168 qup_spi0_data_clk: qup-spi0-data-clk-state { 5169 pins = "gpio0", "gpio1", "gpio2"; 5170 function = "qup00"; 5171 }; 5172 5173 qup_spi0_cs: qup-spi0-cs-state { 5174 pins = "gpio3"; 5175 function = "qup00"; 5176 }; 5177 5178 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5179 pins = "gpio3"; 5180 function = "gpio"; 5181 }; 5182 5183 qup_spi1_data_clk: qup-spi1-data-clk-state { 5184 pins = "gpio4", "gpio5", "gpio6"; 5185 function = "qup01"; 5186 }; 5187 5188 qup_spi1_cs: qup-spi1-cs-state { 5189 pins = "gpio7"; 5190 function = "qup01"; 5191 }; 5192 5193 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5194 pins = "gpio7"; 5195 function = "gpio"; 5196 }; 5197 5198 qup_spi2_data_clk: qup-spi2-data-clk-state { 5199 pins = "gpio8", "gpio9", "gpio10"; 5200 function = "qup02"; 5201 }; 5202 5203 qup_spi2_cs: qup-spi2-cs-state { 5204 pins = "gpio11"; 5205 function = "qup02"; 5206 }; 5207 5208 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5209 pins = "gpio11"; 5210 function = "gpio"; 5211 }; 5212 5213 qup_spi3_data_clk: qup-spi3-data-clk-state { 5214 pins = "gpio12", "gpio13", "gpio14"; 5215 function = "qup03"; 5216 }; 5217 5218 qup_spi3_cs: qup-spi3-cs-state { 5219 pins = "gpio15"; 5220 function = "qup03"; 5221 }; 5222 5223 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5224 pins = "gpio15"; 5225 function = "gpio"; 5226 }; 5227 5228 qup_spi4_data_clk: qup-spi4-data-clk-state { 5229 pins = "gpio16", "gpio17", "gpio18"; 5230 function = "qup04"; 5231 }; 5232 5233 qup_spi4_cs: qup-spi4-cs-state { 5234 pins = "gpio19"; 5235 function = "qup04"; 5236 }; 5237 5238 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5239 pins = "gpio19"; 5240 function = "gpio"; 5241 }; 5242 5243 qup_spi5_data_clk: qup-spi5-data-clk-state { 5244 pins = "gpio20", "gpio21", "gpio22"; 5245 function = "qup05"; 5246 }; 5247 5248 qup_spi5_cs: qup-spi5-cs-state { 5249 pins = "gpio23"; 5250 function = "qup05"; 5251 }; 5252 5253 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5254 pins = "gpio23"; 5255 function = "gpio"; 5256 }; 5257 5258 qup_spi6_data_clk: qup-spi6-data-clk-state { 5259 pins = "gpio24", "gpio25", "gpio26"; 5260 function = "qup06"; 5261 }; 5262 5263 qup_spi6_cs: qup-spi6-cs-state { 5264 pins = "gpio27"; 5265 function = "qup06"; 5266 }; 5267 5268 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5269 pins = "gpio27"; 5270 function = "gpio"; 5271 }; 5272 5273 qup_spi7_data_clk: qup-spi7-data-clk-state { 5274 pins = "gpio28", "gpio29", "gpio30"; 5275 function = "qup07"; 5276 }; 5277 5278 qup_spi7_cs: qup-spi7-cs-state { 5279 pins = "gpio31"; 5280 function = "qup07"; 5281 }; 5282 5283 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5284 pins = "gpio31"; 5285 function = "gpio"; 5286 }; 5287 5288 qup_spi8_data_clk: qup-spi8-data-clk-state { 5289 pins = "gpio32", "gpio33", "gpio34"; 5290 function = "qup10"; 5291 }; 5292 5293 qup_spi8_cs: qup-spi8-cs-state { 5294 pins = "gpio35"; 5295 function = "qup10"; 5296 }; 5297 5298 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5299 pins = "gpio35"; 5300 function = "gpio"; 5301 }; 5302 5303 qup_spi9_data_clk: qup-spi9-data-clk-state { 5304 pins = "gpio36", "gpio37", "gpio38"; 5305 function = "qup11"; 5306 }; 5307 5308 qup_spi9_cs: qup-spi9-cs-state { 5309 pins = "gpio39"; 5310 function = "qup11"; 5311 }; 5312 5313 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5314 pins = "gpio39"; 5315 function = "gpio"; 5316 }; 5317 5318 qup_spi10_data_clk: qup-spi10-data-clk-state { 5319 pins = "gpio40", "gpio41", "gpio42"; 5320 function = "qup12"; 5321 }; 5322 5323 qup_spi10_cs: qup-spi10-cs-state { 5324 pins = "gpio43"; 5325 function = "qup12"; 5326 }; 5327 5328 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5329 pins = "gpio43"; 5330 function = "gpio"; 5331 }; 5332 5333 qup_spi11_data_clk: qup-spi11-data-clk-state { 5334 pins = "gpio44", "gpio45", "gpio46"; 5335 function = "qup13"; 5336 }; 5337 5338 qup_spi11_cs: qup-spi11-cs-state { 5339 pins = "gpio47"; 5340 function = "qup13"; 5341 }; 5342 5343 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5344 pins = "gpio47"; 5345 function = "gpio"; 5346 }; 5347 5348 qup_spi12_data_clk: qup-spi12-data-clk-state { 5349 pins = "gpio48", "gpio49", "gpio50"; 5350 function = "qup14"; 5351 }; 5352 5353 qup_spi12_cs: qup-spi12-cs-state { 5354 pins = "gpio51"; 5355 function = "qup14"; 5356 }; 5357 5358 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5359 pins = "gpio51"; 5360 function = "gpio"; 5361 }; 5362 5363 qup_spi13_data_clk: qup-spi13-data-clk-state { 5364 pins = "gpio52", "gpio53", "gpio54"; 5365 function = "qup15"; 5366 }; 5367 5368 qup_spi13_cs: qup-spi13-cs-state { 5369 pins = "gpio55"; 5370 function = "qup15"; 5371 }; 5372 5373 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5374 pins = "gpio55"; 5375 function = "gpio"; 5376 }; 5377 5378 qup_spi14_data_clk: qup-spi14-data-clk-state { 5379 pins = "gpio56", "gpio57", "gpio58"; 5380 function = "qup16"; 5381 }; 5382 5383 qup_spi14_cs: qup-spi14-cs-state { 5384 pins = "gpio59"; 5385 function = "qup16"; 5386 }; 5387 5388 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5389 pins = "gpio59"; 5390 function = "gpio"; 5391 }; 5392 5393 qup_spi15_data_clk: qup-spi15-data-clk-state { 5394 pins = "gpio60", "gpio61", "gpio62"; 5395 function = "qup17"; 5396 }; 5397 5398 qup_spi15_cs: qup-spi15-cs-state { 5399 pins = "gpio63"; 5400 function = "qup17"; 5401 }; 5402 5403 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5404 pins = "gpio63"; 5405 function = "gpio"; 5406 }; 5407 5408 qup_uart0_cts: qup-uart0-cts-state { 5409 pins = "gpio0"; 5410 function = "qup00"; 5411 }; 5412 5413 qup_uart0_rts: qup-uart0-rts-state { 5414 pins = "gpio1"; 5415 function = "qup00"; 5416 }; 5417 5418 qup_uart0_tx: qup-uart0-tx-state { 5419 pins = "gpio2"; 5420 function = "qup00"; 5421 }; 5422 5423 qup_uart0_rx: qup-uart0-rx-state { 5424 pins = "gpio3"; 5425 function = "qup00"; 5426 }; 5427 5428 qup_uart1_cts: qup-uart1-cts-state { 5429 pins = "gpio4"; 5430 function = "qup01"; 5431 }; 5432 5433 qup_uart1_rts: qup-uart1-rts-state { 5434 pins = "gpio5"; 5435 function = "qup01"; 5436 }; 5437 5438 qup_uart1_tx: qup-uart1-tx-state { 5439 pins = "gpio6"; 5440 function = "qup01"; 5441 }; 5442 5443 qup_uart1_rx: qup-uart1-rx-state { 5444 pins = "gpio7"; 5445 function = "qup01"; 5446 }; 5447 5448 qup_uart2_cts: qup-uart2-cts-state { 5449 pins = "gpio8"; 5450 function = "qup02"; 5451 }; 5452 5453 qup_uart2_rts: qup-uart2-rts-state { 5454 pins = "gpio9"; 5455 function = "qup02"; 5456 }; 5457 5458 qup_uart2_tx: qup-uart2-tx-state { 5459 pins = "gpio10"; 5460 function = "qup02"; 5461 }; 5462 5463 qup_uart2_rx: qup-uart2-rx-state { 5464 pins = "gpio11"; 5465 function = "qup02"; 5466 }; 5467 5468 qup_uart3_cts: qup-uart3-cts-state { 5469 pins = "gpio12"; 5470 function = "qup03"; 5471 }; 5472 5473 qup_uart3_rts: qup-uart3-rts-state { 5474 pins = "gpio13"; 5475 function = "qup03"; 5476 }; 5477 5478 qup_uart3_tx: qup-uart3-tx-state { 5479 pins = "gpio14"; 5480 function = "qup03"; 5481 }; 5482 5483 qup_uart3_rx: qup-uart3-rx-state { 5484 pins = "gpio15"; 5485 function = "qup03"; 5486 }; 5487 5488 qup_uart4_cts: qup-uart4-cts-state { 5489 pins = "gpio16"; 5490 function = "qup04"; 5491 }; 5492 5493 qup_uart4_rts: qup-uart4-rts-state { 5494 pins = "gpio17"; 5495 function = "qup04"; 5496 }; 5497 5498 qup_uart4_tx: qup-uart4-tx-state { 5499 pins = "gpio18"; 5500 function = "qup04"; 5501 }; 5502 5503 qup_uart4_rx: qup-uart4-rx-state { 5504 pins = "gpio19"; 5505 function = "qup04"; 5506 }; 5507 5508 qup_uart5_tx: qup-uart5-tx-state { 5509 pins = "gpio22"; 5510 function = "qup05"; 5511 }; 5512 5513 qup_uart5_rx: qup-uart5-rx-state { 5514 pins = "gpio23"; 5515 function = "qup05"; 5516 }; 5517 5518 qup_uart6_cts: qup-uart6-cts-state { 5519 pins = "gpio24"; 5520 function = "qup06"; 5521 }; 5522 5523 qup_uart6_rts: qup-uart6-rts-state { 5524 pins = "gpio25"; 5525 function = "qup06"; 5526 }; 5527 5528 qup_uart6_tx: qup-uart6-tx-state { 5529 pins = "gpio26"; 5530 function = "qup06"; 5531 }; 5532 5533 qup_uart6_rx: qup-uart6-rx-state { 5534 pins = "gpio27"; 5535 function = "qup06"; 5536 }; 5537 5538 qup_uart7_cts: qup-uart7-cts-state { 5539 pins = "gpio28"; 5540 function = "qup07"; 5541 }; 5542 5543 qup_uart7_rts: qup-uart7-rts-state { 5544 pins = "gpio29"; 5545 function = "qup07"; 5546 }; 5547 5548 qup_uart7_tx: qup-uart7-tx-state { 5549 pins = "gpio30"; 5550 function = "qup07"; 5551 }; 5552 5553 qup_uart7_rx: qup-uart7-rx-state { 5554 pins = "gpio31"; 5555 function = "qup07"; 5556 }; 5557 5558 qup_uart8_cts: qup-uart8-cts-state { 5559 pins = "gpio32"; 5560 function = "qup10"; 5561 }; 5562 5563 qup_uart8_rts: qup-uart8-rts-state { 5564 pins = "gpio33"; 5565 function = "qup10"; 5566 }; 5567 5568 qup_uart8_tx: qup-uart8-tx-state { 5569 pins = "gpio34"; 5570 function = "qup10"; 5571 }; 5572 5573 qup_uart8_rx: qup-uart8-rx-state { 5574 pins = "gpio35"; 5575 function = "qup10"; 5576 }; 5577 5578 qup_uart9_cts: qup-uart9-cts-state { 5579 pins = "gpio36"; 5580 function = "qup11"; 5581 }; 5582 5583 qup_uart9_rts: qup-uart9-rts-state { 5584 pins = "gpio37"; 5585 function = "qup11"; 5586 }; 5587 5588 qup_uart9_tx: qup-uart9-tx-state { 5589 pins = "gpio38"; 5590 function = "qup11"; 5591 }; 5592 5593 qup_uart9_rx: qup-uart9-rx-state { 5594 pins = "gpio39"; 5595 function = "qup11"; 5596 }; 5597 5598 qup_uart10_cts: qup-uart10-cts-state { 5599 pins = "gpio40"; 5600 function = "qup12"; 5601 }; 5602 5603 qup_uart10_rts: qup-uart10-rts-state { 5604 pins = "gpio41"; 5605 function = "qup12"; 5606 }; 5607 5608 qup_uart10_tx: qup-uart10-tx-state { 5609 pins = "gpio42"; 5610 function = "qup12"; 5611 }; 5612 5613 qup_uart10_rx: qup-uart10-rx-state { 5614 pins = "gpio43"; 5615 function = "qup12"; 5616 }; 5617 5618 qup_uart11_cts: qup-uart11-cts-state { 5619 pins = "gpio44"; 5620 function = "qup13"; 5621 }; 5622 5623 qup_uart11_rts: qup-uart11-rts-state { 5624 pins = "gpio45"; 5625 function = "qup13"; 5626 }; 5627 5628 qup_uart11_tx: qup-uart11-tx-state { 5629 pins = "gpio46"; 5630 function = "qup13"; 5631 }; 5632 5633 qup_uart11_rx: qup-uart11-rx-state { 5634 pins = "gpio47"; 5635 function = "qup13"; 5636 }; 5637 5638 qup_uart12_cts: qup-uart12-cts-state { 5639 pins = "gpio48"; 5640 function = "qup14"; 5641 }; 5642 5643 qup_uart12_rts: qup-uart12-rts-state { 5644 pins = "gpio49"; 5645 function = "qup14"; 5646 }; 5647 5648 qup_uart12_tx: qup-uart12-tx-state { 5649 pins = "gpio50"; 5650 function = "qup14"; 5651 }; 5652 5653 qup_uart12_rx: qup-uart12-rx-state { 5654 pins = "gpio51"; 5655 function = "qup14"; 5656 }; 5657 5658 qup_uart13_cts: qup-uart13-cts-state { 5659 pins = "gpio52"; 5660 function = "qup15"; 5661 }; 5662 5663 qup_uart13_rts: qup-uart13-rts-state { 5664 pins = "gpio53"; 5665 function = "qup15"; 5666 }; 5667 5668 qup_uart13_tx: qup-uart13-tx-state { 5669 pins = "gpio54"; 5670 function = "qup15"; 5671 }; 5672 5673 qup_uart13_rx: qup-uart13-rx-state { 5674 pins = "gpio55"; 5675 function = "qup15"; 5676 }; 5677 5678 qup_uart14_cts: qup-uart14-cts-state { 5679 pins = "gpio56"; 5680 function = "qup16"; 5681 }; 5682 5683 qup_uart14_rts: qup-uart14-rts-state { 5684 pins = "gpio57"; 5685 function = "qup16"; 5686 }; 5687 5688 qup_uart14_tx: qup-uart14-tx-state { 5689 pins = "gpio58"; 5690 function = "qup16"; 5691 }; 5692 5693 qup_uart14_rx: qup-uart14-rx-state { 5694 pins = "gpio59"; 5695 function = "qup16"; 5696 }; 5697 5698 qup_uart15_cts: qup-uart15-cts-state { 5699 pins = "gpio60"; 5700 function = "qup17"; 5701 }; 5702 5703 qup_uart15_rts: qup-uart15-rts-state { 5704 pins = "gpio61"; 5705 function = "qup17"; 5706 }; 5707 5708 qup_uart15_tx: qup-uart15-tx-state { 5709 pins = "gpio62"; 5710 function = "qup17"; 5711 }; 5712 5713 qup_uart15_rx: qup-uart15-rx-state { 5714 pins = "gpio63"; 5715 function = "qup17"; 5716 }; 5717 5718 sdc1_clk: sdc1-clk-state { 5719 pins = "sdc1_clk"; 5720 }; 5721 5722 sdc1_cmd: sdc1-cmd-state { 5723 pins = "sdc1_cmd"; 5724 }; 5725 5726 sdc1_data: sdc1-data-state { 5727 pins = "sdc1_data"; 5728 }; 5729 5730 sdc1_rclk: sdc1-rclk-state { 5731 pins = "sdc1_rclk"; 5732 }; 5733 5734 sdc1_clk_sleep: sdc1-clk-sleep-state { 5735 pins = "sdc1_clk"; 5736 drive-strength = <2>; 5737 bias-bus-hold; 5738 }; 5739 5740 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5741 pins = "sdc1_cmd"; 5742 drive-strength = <2>; 5743 bias-bus-hold; 5744 }; 5745 5746 sdc1_data_sleep: sdc1-data-sleep-state { 5747 pins = "sdc1_data"; 5748 drive-strength = <2>; 5749 bias-bus-hold; 5750 }; 5751 5752 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5753 pins = "sdc1_rclk"; 5754 drive-strength = <2>; 5755 bias-bus-hold; 5756 }; 5757 5758 sdc2_clk: sdc2-clk-state { 5759 pins = "sdc2_clk"; 5760 }; 5761 5762 sdc2_cmd: sdc2-cmd-state { 5763 pins = "sdc2_cmd"; 5764 }; 5765 5766 sdc2_data: sdc2-data-state { 5767 pins = "sdc2_data"; 5768 }; 5769 5770 sdc2_clk_sleep: sdc2-clk-sleep-state { 5771 pins = "sdc2_clk"; 5772 drive-strength = <2>; 5773 bias-bus-hold; 5774 }; 5775 5776 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5777 pins = "sdc2_cmd"; 5778 drive-strength = <2>; 5779 bias-bus-hold; 5780 }; 5781 5782 sdc2_data_sleep: sdc2-data-sleep-state { 5783 pins = "sdc2_data"; 5784 drive-strength = <2>; 5785 bias-bus-hold; 5786 }; 5787 }; 5788 5789 sram@146a5000 { 5790 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5791 reg = <0 0x146a5000 0 0x6000>; 5792 5793 #address-cells = <1>; 5794 #size-cells = <1>; 5795 5796 ranges = <0 0 0x146a5000 0x6000>; 5797 5798 pil-reloc@594c { 5799 compatible = "qcom,pil-reloc-info"; 5800 reg = <0x594c 0xc8>; 5801 }; 5802 }; 5803 5804 apps_smmu: iommu@15000000 { 5805 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5806 reg = <0 0x15000000 0 0x100000>; 5807 #iommu-cells = <2>; 5808 #global-interrupts = <1>; 5809 dma-coherent; 5810 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5842 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5844 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5847 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5848 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5849 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5850 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5851 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5852 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5853 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5854 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5855 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5856 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5891 }; 5892 5893 anoc_1_tbu: tbu@151dd000 { 5894 compatible = "qcom,sc7280-tbu"; 5895 reg = <0x0 0x151dd000 0x0 0x1000>; 5896 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5897 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5898 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5899 }; 5900 5901 anoc_2_tbu: tbu@151e1000 { 5902 compatible = "qcom,sc7280-tbu"; 5903 reg = <0x0 0x151e1000 0x0 0x1000>; 5904 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5905 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5906 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5907 }; 5908 5909 mnoc_hf_0_tbu: tbu@151e5000 { 5910 compatible = "qcom,sc7280-tbu"; 5911 reg = <0x0 0x151e5000 0x0 0x1000>; 5912 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5913 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5914 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5915 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5916 }; 5917 5918 mnoc_hf_1_tbu: tbu@151e9000 { 5919 compatible = "qcom,sc7280-tbu"; 5920 reg = <0x0 0x151e9000 0x0 0x1000>; 5921 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5922 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5923 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5924 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5925 }; 5926 5927 compute_dsp_1_tbu: tbu@151ed000 { 5928 compatible = "qcom,sc7280-tbu"; 5929 reg = <0x0 0x151ed000 0x0 0x1000>; 5930 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5931 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5932 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 5933 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5934 }; 5935 5936 compute_dsp_0_tbu: tbu@151f1000 { 5937 compatible = "qcom,sc7280-tbu"; 5938 reg = <0x0 0x151f1000 0x0 0x1000>; 5939 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5940 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5941 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 5942 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5943 }; 5944 5945 adsp_tbu: tbu@151f5000 { 5946 compatible = "qcom,sc7280-tbu"; 5947 reg = <0x0 0x151f5000 0x0 0x1000>; 5948 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5949 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5950 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5951 }; 5952 5953 anoc_1_pcie_tbu: tbu@151f9000 { 5954 compatible = "qcom,sc7280-tbu"; 5955 reg = <0x0 0x151f9000 0x0 0x1000>; 5956 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5957 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5958 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5959 }; 5960 5961 mnoc_sf_0_tbu: tbu@151fd000 { 5962 compatible = "qcom,sc7280-tbu"; 5963 reg = <0x0 0x151fd000 0x0 0x1000>; 5964 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5965 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5966 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 5967 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 5968 }; 5969 5970 intc: interrupt-controller@17a00000 { 5971 compatible = "arm,gic-v3"; 5972 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5973 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5974 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5975 #interrupt-cells = <3>; 5976 interrupt-controller; 5977 #address-cells = <2>; 5978 #size-cells = <2>; 5979 ranges; 5980 5981 msi-controller@17a40000 { 5982 compatible = "arm,gic-v3-its"; 5983 reg = <0 0x17a40000 0 0x20000>; 5984 msi-controller; 5985 #msi-cells = <1>; 5986 status = "disabled"; 5987 }; 5988 }; 5989 5990 watchdog: watchdog@17c10000 { 5991 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5992 reg = <0 0x17c10000 0 0x1000>; 5993 clocks = <&sleep_clk>; 5994 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5995 status = "reserved"; /* Owned by Gunyah hyp */ 5996 }; 5997 5998 timer@17c20000 { 5999 #address-cells = <1>; 6000 #size-cells = <1>; 6001 ranges = <0 0 0 0x20000000>; 6002 compatible = "arm,armv7-timer-mem"; 6003 reg = <0 0x17c20000 0 0x1000>; 6004 6005 frame@17c21000 { 6006 frame-number = <0>; 6007 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6008 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6009 reg = <0x17c21000 0x1000>, 6010 <0x17c22000 0x1000>; 6011 }; 6012 6013 frame@17c23000 { 6014 frame-number = <1>; 6015 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6016 reg = <0x17c23000 0x1000>; 6017 status = "disabled"; 6018 }; 6019 6020 frame@17c25000 { 6021 frame-number = <2>; 6022 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6023 reg = <0x17c25000 0x1000>; 6024 status = "disabled"; 6025 }; 6026 6027 frame@17c27000 { 6028 frame-number = <3>; 6029 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6030 reg = <0x17c27000 0x1000>; 6031 status = "disabled"; 6032 }; 6033 6034 frame@17c29000 { 6035 frame-number = <4>; 6036 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6037 reg = <0x17c29000 0x1000>; 6038 status = "disabled"; 6039 }; 6040 6041 frame@17c2b000 { 6042 frame-number = <5>; 6043 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6044 reg = <0x17c2b000 0x1000>; 6045 status = "disabled"; 6046 }; 6047 6048 frame@17c2d000 { 6049 frame-number = <6>; 6050 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6051 reg = <0x17c2d000 0x1000>; 6052 status = "disabled"; 6053 }; 6054 }; 6055 6056 apps_rsc: rsc@18200000 { 6057 compatible = "qcom,rpmh-rsc"; 6058 reg = <0 0x18200000 0 0x10000>, 6059 <0 0x18210000 0 0x10000>, 6060 <0 0x18220000 0 0x10000>; 6061 reg-names = "drv-0", "drv-1", "drv-2"; 6062 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6063 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6064 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6065 qcom,tcs-offset = <0xd00>; 6066 qcom,drv-id = <2>; 6067 qcom,tcs-config = <ACTIVE_TCS 2>, 6068 <SLEEP_TCS 3>, 6069 <WAKE_TCS 3>, 6070 <CONTROL_TCS 1>; 6071 power-domains = <&cluster_pd>; 6072 6073 apps_bcm_voter: bcm-voter { 6074 compatible = "qcom,bcm-voter"; 6075 }; 6076 6077 rpmhpd: power-controller { 6078 compatible = "qcom,sc7280-rpmhpd"; 6079 #power-domain-cells = <1>; 6080 operating-points-v2 = <&rpmhpd_opp_table>; 6081 6082 rpmhpd_opp_table: opp-table { 6083 compatible = "operating-points-v2"; 6084 6085 rpmhpd_opp_ret: opp1 { 6086 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6087 }; 6088 6089 rpmhpd_opp_low_svs: opp2 { 6090 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6091 }; 6092 6093 rpmhpd_opp_svs: opp3 { 6094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6095 }; 6096 6097 rpmhpd_opp_svs_l1: opp4 { 6098 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6099 }; 6100 6101 rpmhpd_opp_svs_l2: opp5 { 6102 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6103 }; 6104 6105 rpmhpd_opp_nom: opp6 { 6106 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6107 }; 6108 6109 rpmhpd_opp_nom_l1: opp7 { 6110 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6111 }; 6112 6113 rpmhpd_opp_turbo: opp8 { 6114 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6115 }; 6116 6117 rpmhpd_opp_turbo_l1: opp9 { 6118 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6119 }; 6120 }; 6121 }; 6122 6123 rpmhcc: clock-controller { 6124 compatible = "qcom,sc7280-rpmh-clk"; 6125 clocks = <&xo_board>; 6126 clock-names = "xo"; 6127 #clock-cells = <1>; 6128 }; 6129 }; 6130 6131 epss_l3: interconnect@18590000 { 6132 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6133 reg = <0 0x18590000 0 0x1000>; 6134 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6135 clock-names = "xo", "alternate"; 6136 #interconnect-cells = <1>; 6137 }; 6138 6139 cpufreq_hw: cpufreq@18591000 { 6140 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6141 reg = <0 0x18591000 0 0x1000>, 6142 <0 0x18592000 0 0x1000>, 6143 <0 0x18593000 0 0x1000>; 6144 6145 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6146 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6147 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6148 interrupt-names = "dcvsh-irq-0", 6149 "dcvsh-irq-1", 6150 "dcvsh-irq-2"; 6151 6152 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6153 clock-names = "xo", "alternate"; 6154 #freq-domain-cells = <1>; 6155 #clock-cells = <1>; 6156 }; 6157 }; 6158 6159 sound: sound { 6160 }; 6161 6162 thermal_zones: thermal-zones { 6163 cpu0-thermal { 6164 polling-delay-passive = <250>; 6165 6166 thermal-sensors = <&tsens0 1>; 6167 6168 trips { 6169 cpu0_alert0: trip-point0 { 6170 temperature = <90000>; 6171 hysteresis = <2000>; 6172 type = "passive"; 6173 }; 6174 6175 cpu0_alert1: trip-point1 { 6176 temperature = <95000>; 6177 hysteresis = <2000>; 6178 type = "passive"; 6179 }; 6180 6181 cpu0_crit: cpu-crit { 6182 temperature = <110000>; 6183 hysteresis = <0>; 6184 type = "critical"; 6185 }; 6186 }; 6187 6188 cooling-maps { 6189 map0 { 6190 trip = <&cpu0_alert0>; 6191 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6192 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6193 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6194 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6195 }; 6196 map1 { 6197 trip = <&cpu0_alert1>; 6198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6202 }; 6203 }; 6204 }; 6205 6206 cpu1-thermal { 6207 polling-delay-passive = <250>; 6208 6209 thermal-sensors = <&tsens0 2>; 6210 6211 trips { 6212 cpu1_alert0: trip-point0 { 6213 temperature = <90000>; 6214 hysteresis = <2000>; 6215 type = "passive"; 6216 }; 6217 6218 cpu1_alert1: trip-point1 { 6219 temperature = <95000>; 6220 hysteresis = <2000>; 6221 type = "passive"; 6222 }; 6223 6224 cpu1_crit: cpu-crit { 6225 temperature = <110000>; 6226 hysteresis = <0>; 6227 type = "critical"; 6228 }; 6229 }; 6230 6231 cooling-maps { 6232 map0 { 6233 trip = <&cpu1_alert0>; 6234 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6235 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6236 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6237 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6238 }; 6239 map1 { 6240 trip = <&cpu1_alert1>; 6241 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6242 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6243 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6244 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6245 }; 6246 }; 6247 }; 6248 6249 cpu2-thermal { 6250 polling-delay-passive = <250>; 6251 6252 thermal-sensors = <&tsens0 3>; 6253 6254 trips { 6255 cpu2_alert0: trip-point0 { 6256 temperature = <90000>; 6257 hysteresis = <2000>; 6258 type = "passive"; 6259 }; 6260 6261 cpu2_alert1: trip-point1 { 6262 temperature = <95000>; 6263 hysteresis = <2000>; 6264 type = "passive"; 6265 }; 6266 6267 cpu2_crit: cpu-crit { 6268 temperature = <110000>; 6269 hysteresis = <0>; 6270 type = "critical"; 6271 }; 6272 }; 6273 6274 cooling-maps { 6275 map0 { 6276 trip = <&cpu2_alert0>; 6277 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6278 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6279 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6280 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6281 }; 6282 map1 { 6283 trip = <&cpu2_alert1>; 6284 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6285 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6286 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6287 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6288 }; 6289 }; 6290 }; 6291 6292 cpu3-thermal { 6293 polling-delay-passive = <250>; 6294 6295 thermal-sensors = <&tsens0 4>; 6296 6297 trips { 6298 cpu3_alert0: trip-point0 { 6299 temperature = <90000>; 6300 hysteresis = <2000>; 6301 type = "passive"; 6302 }; 6303 6304 cpu3_alert1: trip-point1 { 6305 temperature = <95000>; 6306 hysteresis = <2000>; 6307 type = "passive"; 6308 }; 6309 6310 cpu3_crit: cpu-crit { 6311 temperature = <110000>; 6312 hysteresis = <0>; 6313 type = "critical"; 6314 }; 6315 }; 6316 6317 cooling-maps { 6318 map0 { 6319 trip = <&cpu3_alert0>; 6320 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6321 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6322 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6323 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6324 }; 6325 map1 { 6326 trip = <&cpu3_alert1>; 6327 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6328 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6329 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6330 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6331 }; 6332 }; 6333 }; 6334 6335 cpu4-thermal { 6336 polling-delay-passive = <250>; 6337 6338 thermal-sensors = <&tsens0 7>; 6339 6340 trips { 6341 cpu4_alert0: trip-point0 { 6342 temperature = <90000>; 6343 hysteresis = <2000>; 6344 type = "passive"; 6345 }; 6346 6347 cpu4_alert1: trip-point1 { 6348 temperature = <95000>; 6349 hysteresis = <2000>; 6350 type = "passive"; 6351 }; 6352 6353 cpu4_crit: cpu-crit { 6354 temperature = <110000>; 6355 hysteresis = <0>; 6356 type = "critical"; 6357 }; 6358 }; 6359 6360 cooling-maps { 6361 map0 { 6362 trip = <&cpu4_alert0>; 6363 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6364 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6365 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6366 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6367 }; 6368 map1 { 6369 trip = <&cpu4_alert1>; 6370 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6371 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6372 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6373 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6374 }; 6375 }; 6376 }; 6377 6378 cpu5-thermal { 6379 polling-delay-passive = <250>; 6380 6381 thermal-sensors = <&tsens0 8>; 6382 6383 trips { 6384 cpu5_alert0: trip-point0 { 6385 temperature = <90000>; 6386 hysteresis = <2000>; 6387 type = "passive"; 6388 }; 6389 6390 cpu5_alert1: trip-point1 { 6391 temperature = <95000>; 6392 hysteresis = <2000>; 6393 type = "passive"; 6394 }; 6395 6396 cpu5_crit: cpu-crit { 6397 temperature = <110000>; 6398 hysteresis = <0>; 6399 type = "critical"; 6400 }; 6401 }; 6402 6403 cooling-maps { 6404 map0 { 6405 trip = <&cpu5_alert0>; 6406 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6407 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6408 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6409 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6410 }; 6411 map1 { 6412 trip = <&cpu5_alert1>; 6413 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6414 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6415 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6416 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6417 }; 6418 }; 6419 }; 6420 6421 cpu6-thermal { 6422 polling-delay-passive = <250>; 6423 6424 thermal-sensors = <&tsens0 9>; 6425 6426 trips { 6427 cpu6_alert0: trip-point0 { 6428 temperature = <90000>; 6429 hysteresis = <2000>; 6430 type = "passive"; 6431 }; 6432 6433 cpu6_alert1: trip-point1 { 6434 temperature = <95000>; 6435 hysteresis = <2000>; 6436 type = "passive"; 6437 }; 6438 6439 cpu6_crit: cpu-crit { 6440 temperature = <110000>; 6441 hysteresis = <0>; 6442 type = "critical"; 6443 }; 6444 }; 6445 6446 cooling-maps { 6447 map0 { 6448 trip = <&cpu6_alert0>; 6449 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6450 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6451 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6452 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6453 }; 6454 map1 { 6455 trip = <&cpu6_alert1>; 6456 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6457 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6458 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6459 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6460 }; 6461 }; 6462 }; 6463 6464 cpu7-thermal { 6465 polling-delay-passive = <250>; 6466 6467 thermal-sensors = <&tsens0 10>; 6468 6469 trips { 6470 cpu7_alert0: trip-point0 { 6471 temperature = <90000>; 6472 hysteresis = <2000>; 6473 type = "passive"; 6474 }; 6475 6476 cpu7_alert1: trip-point1 { 6477 temperature = <95000>; 6478 hysteresis = <2000>; 6479 type = "passive"; 6480 }; 6481 6482 cpu7_crit: cpu-crit { 6483 temperature = <110000>; 6484 hysteresis = <0>; 6485 type = "critical"; 6486 }; 6487 }; 6488 6489 cooling-maps { 6490 map0 { 6491 trip = <&cpu7_alert0>; 6492 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6493 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6494 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6495 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6496 }; 6497 map1 { 6498 trip = <&cpu7_alert1>; 6499 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6500 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6501 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6502 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6503 }; 6504 }; 6505 }; 6506 6507 cpu8-thermal { 6508 polling-delay-passive = <250>; 6509 6510 thermal-sensors = <&tsens0 11>; 6511 6512 trips { 6513 cpu8_alert0: trip-point0 { 6514 temperature = <90000>; 6515 hysteresis = <2000>; 6516 type = "passive"; 6517 }; 6518 6519 cpu8_alert1: trip-point1 { 6520 temperature = <95000>; 6521 hysteresis = <2000>; 6522 type = "passive"; 6523 }; 6524 6525 cpu8_crit: cpu-crit { 6526 temperature = <110000>; 6527 hysteresis = <0>; 6528 type = "critical"; 6529 }; 6530 }; 6531 6532 cooling-maps { 6533 map0 { 6534 trip = <&cpu8_alert0>; 6535 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6536 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6537 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6538 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6539 }; 6540 map1 { 6541 trip = <&cpu8_alert1>; 6542 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6543 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6544 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6545 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6546 }; 6547 }; 6548 }; 6549 6550 cpu9-thermal { 6551 polling-delay-passive = <250>; 6552 6553 thermal-sensors = <&tsens0 12>; 6554 6555 trips { 6556 cpu9_alert0: trip-point0 { 6557 temperature = <90000>; 6558 hysteresis = <2000>; 6559 type = "passive"; 6560 }; 6561 6562 cpu9_alert1: trip-point1 { 6563 temperature = <95000>; 6564 hysteresis = <2000>; 6565 type = "passive"; 6566 }; 6567 6568 cpu9_crit: cpu-crit { 6569 temperature = <110000>; 6570 hysteresis = <0>; 6571 type = "critical"; 6572 }; 6573 }; 6574 6575 cooling-maps { 6576 map0 { 6577 trip = <&cpu9_alert0>; 6578 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6579 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6580 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6581 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6582 }; 6583 map1 { 6584 trip = <&cpu9_alert1>; 6585 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6586 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6587 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6588 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6589 }; 6590 }; 6591 }; 6592 6593 cpu10-thermal { 6594 polling-delay-passive = <250>; 6595 6596 thermal-sensors = <&tsens0 13>; 6597 6598 trips { 6599 cpu10_alert0: trip-point0 { 6600 temperature = <90000>; 6601 hysteresis = <2000>; 6602 type = "passive"; 6603 }; 6604 6605 cpu10_alert1: trip-point1 { 6606 temperature = <95000>; 6607 hysteresis = <2000>; 6608 type = "passive"; 6609 }; 6610 6611 cpu10_crit: cpu-crit { 6612 temperature = <110000>; 6613 hysteresis = <0>; 6614 type = "critical"; 6615 }; 6616 }; 6617 6618 cooling-maps { 6619 map0 { 6620 trip = <&cpu10_alert0>; 6621 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6622 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6623 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6624 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6625 }; 6626 map1 { 6627 trip = <&cpu10_alert1>; 6628 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6629 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6630 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6631 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6632 }; 6633 }; 6634 }; 6635 6636 cpu11-thermal { 6637 polling-delay-passive = <250>; 6638 6639 thermal-sensors = <&tsens0 14>; 6640 6641 trips { 6642 cpu11_alert0: trip-point0 { 6643 temperature = <90000>; 6644 hysteresis = <2000>; 6645 type = "passive"; 6646 }; 6647 6648 cpu11_alert1: trip-point1 { 6649 temperature = <95000>; 6650 hysteresis = <2000>; 6651 type = "passive"; 6652 }; 6653 6654 cpu11_crit: cpu-crit { 6655 temperature = <110000>; 6656 hysteresis = <0>; 6657 type = "critical"; 6658 }; 6659 }; 6660 6661 cooling-maps { 6662 map0 { 6663 trip = <&cpu11_alert0>; 6664 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6665 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6666 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6667 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6668 }; 6669 map1 { 6670 trip = <&cpu11_alert1>; 6671 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6672 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6673 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6674 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6675 }; 6676 }; 6677 }; 6678 6679 aoss0-thermal { 6680 polling-delay-passive = <0>; 6681 6682 thermal-sensors = <&tsens0 0>; 6683 6684 trips { 6685 aoss0_alert0: trip-point0 { 6686 temperature = <90000>; 6687 hysteresis = <2000>; 6688 type = "hot"; 6689 }; 6690 6691 aoss0_crit: aoss0-crit { 6692 temperature = <110000>; 6693 hysteresis = <0>; 6694 type = "critical"; 6695 }; 6696 }; 6697 }; 6698 6699 aoss1-thermal { 6700 polling-delay-passive = <0>; 6701 6702 thermal-sensors = <&tsens1 0>; 6703 6704 trips { 6705 aoss1_alert0: trip-point0 { 6706 temperature = <90000>; 6707 hysteresis = <2000>; 6708 type = "hot"; 6709 }; 6710 6711 aoss1_crit: aoss1-crit { 6712 temperature = <110000>; 6713 hysteresis = <0>; 6714 type = "critical"; 6715 }; 6716 }; 6717 }; 6718 6719 cpuss0-thermal { 6720 polling-delay-passive = <0>; 6721 6722 thermal-sensors = <&tsens0 5>; 6723 6724 trips { 6725 cpuss0_alert0: trip-point0 { 6726 temperature = <90000>; 6727 hysteresis = <2000>; 6728 type = "hot"; 6729 }; 6730 cpuss0_crit: cluster0-crit { 6731 temperature = <110000>; 6732 hysteresis = <0>; 6733 type = "critical"; 6734 }; 6735 }; 6736 }; 6737 6738 cpuss1-thermal { 6739 polling-delay-passive = <0>; 6740 6741 thermal-sensors = <&tsens0 6>; 6742 6743 trips { 6744 cpuss1_alert0: trip-point0 { 6745 temperature = <90000>; 6746 hysteresis = <2000>; 6747 type = "hot"; 6748 }; 6749 cpuss1_crit: cluster0-crit { 6750 temperature = <110000>; 6751 hysteresis = <0>; 6752 type = "critical"; 6753 }; 6754 }; 6755 }; 6756 6757 gpuss0-thermal { 6758 polling-delay-passive = <100>; 6759 6760 thermal-sensors = <&tsens1 1>; 6761 6762 trips { 6763 gpuss0_alert0: trip-point0 { 6764 temperature = <95000>; 6765 hysteresis = <2000>; 6766 type = "passive"; 6767 }; 6768 6769 gpuss0_crit: gpuss0-crit { 6770 temperature = <110000>; 6771 hysteresis = <0>; 6772 type = "critical"; 6773 }; 6774 }; 6775 6776 cooling-maps { 6777 map0 { 6778 trip = <&gpuss0_alert0>; 6779 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6780 }; 6781 }; 6782 }; 6783 6784 gpuss1-thermal { 6785 polling-delay-passive = <100>; 6786 6787 thermal-sensors = <&tsens1 2>; 6788 6789 trips { 6790 gpuss1_alert0: trip-point0 { 6791 temperature = <95000>; 6792 hysteresis = <2000>; 6793 type = "passive"; 6794 }; 6795 6796 gpuss1_crit: gpuss1-crit { 6797 temperature = <110000>; 6798 hysteresis = <0>; 6799 type = "critical"; 6800 }; 6801 }; 6802 6803 cooling-maps { 6804 map0 { 6805 trip = <&gpuss1_alert0>; 6806 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6807 }; 6808 }; 6809 }; 6810 6811 nspss0-thermal { 6812 thermal-sensors = <&tsens1 3>; 6813 6814 trips { 6815 nspss0_alert0: trip-point0 { 6816 temperature = <90000>; 6817 hysteresis = <2000>; 6818 type = "hot"; 6819 }; 6820 6821 nspss0_crit: nspss0-crit { 6822 temperature = <110000>; 6823 hysteresis = <0>; 6824 type = "critical"; 6825 }; 6826 }; 6827 }; 6828 6829 nspss1-thermal { 6830 thermal-sensors = <&tsens1 4>; 6831 6832 trips { 6833 nspss1_alert0: trip-point0 { 6834 temperature = <90000>; 6835 hysteresis = <2000>; 6836 type = "hot"; 6837 }; 6838 6839 nspss1_crit: nspss1-crit { 6840 temperature = <110000>; 6841 hysteresis = <0>; 6842 type = "critical"; 6843 }; 6844 }; 6845 }; 6846 6847 video-thermal { 6848 thermal-sensors = <&tsens1 5>; 6849 6850 trips { 6851 video_alert0: trip-point0 { 6852 temperature = <90000>; 6853 hysteresis = <2000>; 6854 type = "hot"; 6855 }; 6856 6857 video_crit: video-crit { 6858 temperature = <110000>; 6859 hysteresis = <0>; 6860 type = "critical"; 6861 }; 6862 }; 6863 }; 6864 6865 ddr-thermal { 6866 thermal-sensors = <&tsens1 6>; 6867 6868 trips { 6869 ddr_alert0: trip-point0 { 6870 temperature = <90000>; 6871 hysteresis = <2000>; 6872 type = "hot"; 6873 }; 6874 6875 ddr_crit: ddr-crit { 6876 temperature = <110000>; 6877 hysteresis = <0>; 6878 type = "critical"; 6879 }; 6880 }; 6881 }; 6882 6883 mdmss0-thermal { 6884 thermal-sensors = <&tsens1 7>; 6885 6886 trips { 6887 mdmss0_alert0: trip-point0 { 6888 temperature = <90000>; 6889 hysteresis = <2000>; 6890 type = "hot"; 6891 }; 6892 6893 mdmss0_crit: mdmss0-crit { 6894 temperature = <110000>; 6895 hysteresis = <0>; 6896 type = "critical"; 6897 }; 6898 }; 6899 }; 6900 6901 mdmss1-thermal { 6902 thermal-sensors = <&tsens1 8>; 6903 6904 trips { 6905 mdmss1_alert0: trip-point0 { 6906 temperature = <90000>; 6907 hysteresis = <2000>; 6908 type = "hot"; 6909 }; 6910 6911 mdmss1_crit: mdmss1-crit { 6912 temperature = <110000>; 6913 hysteresis = <0>; 6914 type = "critical"; 6915 }; 6916 }; 6917 }; 6918 6919 mdmss2-thermal { 6920 thermal-sensors = <&tsens1 9>; 6921 6922 trips { 6923 mdmss2_alert0: trip-point0 { 6924 temperature = <90000>; 6925 hysteresis = <2000>; 6926 type = "hot"; 6927 }; 6928 6929 mdmss2_crit: mdmss2-crit { 6930 temperature = <110000>; 6931 hysteresis = <0>; 6932 type = "critical"; 6933 }; 6934 }; 6935 }; 6936 6937 mdmss3-thermal { 6938 thermal-sensors = <&tsens1 10>; 6939 6940 trips { 6941 mdmss3_alert0: trip-point0 { 6942 temperature = <90000>; 6943 hysteresis = <2000>; 6944 type = "hot"; 6945 }; 6946 6947 mdmss3_crit: mdmss3-crit { 6948 temperature = <110000>; 6949 hysteresis = <0>; 6950 type = "critical"; 6951 }; 6952 }; 6953 }; 6954 6955 camera0-thermal { 6956 thermal-sensors = <&tsens1 11>; 6957 6958 trips { 6959 camera0_alert0: trip-point0 { 6960 temperature = <90000>; 6961 hysteresis = <2000>; 6962 type = "hot"; 6963 }; 6964 6965 camera0_crit: camera0-crit { 6966 temperature = <110000>; 6967 hysteresis = <0>; 6968 type = "critical"; 6969 }; 6970 }; 6971 }; 6972 }; 6973 6974 timer { 6975 compatible = "arm,armv8-timer"; 6976 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6977 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6978 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6979 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6980 }; 6981}; 6982