xref: /aosp_15_r20/external/mesa3d/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2011 Red Hat All Rights Reserved.
3  * Copyright © 2014 Advanced Micro Devices, Inc.
4  *
5  * SPDX-License-Identifier: MIT
6  */
7 
8 #include "amdgpu_winsys.h"
9 #include "util/format/u_format.h"
10 
amdgpu_surface_sanity(const struct pipe_resource * tex)11 static int amdgpu_surface_sanity(const struct pipe_resource *tex)
12 {
13    switch (tex->target) {
14    case PIPE_TEXTURE_1D:
15       if (tex->height0 > 1)
16          return -EINVAL;
17       FALLTHROUGH;
18    case PIPE_TEXTURE_2D:
19    case PIPE_TEXTURE_RECT:
20       if (tex->depth0 > 1 || tex->array_size > 1)
21          return -EINVAL;
22       break;
23    case PIPE_TEXTURE_3D:
24       if (tex->array_size > 1)
25          return -EINVAL;
26       break;
27    case PIPE_TEXTURE_1D_ARRAY:
28       if (tex->height0 > 1)
29          return -EINVAL;
30       FALLTHROUGH;
31    case PIPE_TEXTURE_CUBE:
32    case PIPE_TEXTURE_2D_ARRAY:
33    case PIPE_TEXTURE_CUBE_ARRAY:
34       if (tex->depth0 > 1)
35          return -EINVAL;
36       break;
37    default:
38       return -EINVAL;
39    }
40    return 0;
41 }
42 
amdgpu_surface_init(struct radeon_winsys * rws,const struct radeon_info * info,const struct pipe_resource * tex,uint64_t flags,unsigned bpe,enum radeon_surf_mode mode,struct radeon_surf * surf)43 static int amdgpu_surface_init(struct radeon_winsys *rws,
44                                const struct radeon_info *info,
45                                const struct pipe_resource *tex,
46                                uint64_t flags, unsigned bpe,
47                                enum radeon_surf_mode mode,
48                                struct radeon_surf *surf)
49 {
50    struct amdgpu_winsys *aws = amdgpu_winsys(rws);
51    int r;
52 
53    r = amdgpu_surface_sanity(tex);
54    if (r)
55       return r;
56 
57    surf->blk_w = util_format_get_blockwidth(tex->format);
58    surf->blk_h = util_format_get_blockheight(tex->format);
59    surf->bpe = bpe;
60    surf->flags = flags;
61 
62    struct ac_surf_config config;
63 
64    config.info.width = tex->width0;
65    config.info.height = tex->height0;
66    config.info.depth = tex->depth0;
67    config.info.array_size = tex->array_size;
68    config.info.samples = tex->nr_samples;
69    config.info.storage_samples = tex->nr_storage_samples;
70    config.info.levels = tex->last_level + 1;
71    config.info.num_channels = util_format_get_nr_components(tex->format);
72    config.is_1d = tex->target == PIPE_TEXTURE_1D ||
73                   tex->target == PIPE_TEXTURE_1D_ARRAY;
74    config.is_3d = tex->target == PIPE_TEXTURE_3D;
75    config.is_cube = tex->target == PIPE_TEXTURE_CUBE;
76    config.is_array = tex->target == PIPE_TEXTURE_1D_ARRAY ||
77                      tex->target == PIPE_TEXTURE_2D_ARRAY ||
78                      tex->target == PIPE_TEXTURE_CUBE_ARRAY;
79 
80    /* Use different surface counters for color and FMASK, so that MSAA MRTs
81     * always use consecutive surface indices when FMASK is allocated between
82     * them.
83     */
84    config.info.surf_index = &aws->surf_index_color;
85    config.info.fmask_surf_index = &aws->surf_index_fmask;
86 
87    if (flags & RADEON_SURF_Z_OR_SBUFFER)
88       config.info.surf_index = NULL;
89 
90    /* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */
91    return ac_compute_surface(aws->addrlib, info, &config, mode, surf);
92 }
93 
amdgpu_surface_init_functions(struct amdgpu_screen_winsys * sws)94 void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *sws)
95 {
96    sws->base.surface_init = amdgpu_surface_init;
97 }
98