1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_PSP_H 4 #define AMD_BLOCK_PSP_H 5 6 #include <stdint.h> 7 8 #define SMM_TRIGGER_IO 0 9 #define SMM_TRIGGER_MEM 1 10 11 #define SMM_TRIGGER_BYTE 0 12 #define SMM_TRIGGER_WORD 1 13 #define SMM_TRIGGER_DWORD 2 14 15 struct smm_trigger_info { 16 uint64_t address; /* Memory or IO address */ 17 uint32_t address_type; /* 0=I/O, 1=memory */ 18 uint32_t value_width; /* 0=byte, 1=word, 2=qword */ 19 uint32_t value_and_mask; 20 uint32_t value_or_mask; 21 } __packed; 22 23 struct smm_register { 24 uint64_t address; /* Memory or IO address */ 25 uint32_t address_type; /* 0=I/O, 1=memory */ 26 uint32_t value_width; /* 0=byte, 1=word, 2=qword */ 27 uint32_t reg_bit_mask; 28 uint32_t expect_value; 29 } __packed; 30 31 struct smm_register_info { 32 struct smm_register smi_enb; 33 struct smm_register eos; 34 struct smm_register psp_smi_en; 35 struct smm_register reserved[5]; 36 } __packed; 37 38 void soc_fill_smm_trig_info(struct smm_trigger_info *trig); 39 void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */ 40 41 /* BIOS-to-PSP functions return 0 if successful, else negative value */ 42 #define PSPSTS_SUCCESS 0 43 #define PSPSTS_NOBASE 1 44 #define PSPSTS_HALTED 2 45 #define PSPSTS_RECOVERY 3 46 #define PSPSTS_SEND_ERROR 4 47 #define PSPSTS_INIT_TIMEOUT 5 48 #define PSPSTS_CMD_TIMEOUT 6 49 /* other error codes */ 50 #define PSPSTS_UNSUPPORTED 7 51 #define PSPSTS_INVALID_NAME 8 52 #define PSPSTS_INVALID_BLOB 9 53 54 /* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when 55 the x86 cores are released from reset. */ 56 int psp_notify_dram(void); 57 58 int psp_notify_smm(void); 59 60 /* 61 * type: identical to the corresponding PSP command, e.g. pass 62 * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. 63 * name: cbfs file name 64 */ 65 enum psp_blob_type { 66 BLOB_SMU_FW, 67 BLOB_SMU_FW2, 68 }; 69 70 /* 71 * Notify PSP that the system is entering a sleep state. sleep_state uses the 72 * same definition as Pm1Cnt[SlpTyp], typically 0, 1, 3, 4, 5. 73 */ 74 void psp_notify_sx_info(u8 sleep_type); 75 76 int psp_load_named_blob(enum psp_blob_type type, const char *name); 77 78 /* Sets the GPIO used for the TPM IRQ */ 79 void psp_set_tpm_irq_gpio(unsigned int gpio); 80 81 #endif /* AMD_BLOCK_PSP_H */ 82