1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_LPC_H 4 #define AMD_BLOCK_LPC_H 5 6 #include <types.h> 7 8 /* PCI registers for D14F3 */ 9 #define LPC_PCI_CONTROL 0x40 10 #define LEGACY_DMA_EN BIT(2) 11 #define VW_ROM_SHARING_EN BIT(3) 12 #define EXT_ROM_SHARING_EN BIT(4) 13 #define SPI_ROM_BIOS_SEMAPHORE BIT(5) 14 #define SPI_ROM_EC_SEMAPHORE BIT(6) 15 16 #define LPC_IO_PORT_DECODE_ENABLE 0x44 17 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) 18 #define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) 19 #define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) 20 #define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) 21 #define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) 22 #define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) 23 #define DECODE_ENABLE_SERIAL_PORT0 BIT(6) 24 #define DECODE_ENABLE_SERIAL_PORT1 BIT(7) 25 #define DECODE_ENABLE_SERIAL_PORT2 BIT(8) 26 #define DECODE_ENABLE_SERIAL_PORT3 BIT(9) 27 #define DECODE_ENABLE_SERIAL_PORT4 BIT(10) 28 #define DECODE_ENABLE_SERIAL_PORT5 BIT(11) 29 #define DECODE_ENABLE_SERIAL_PORT6 BIT(12) 30 #define DECODE_ENABLE_SERIAL_PORT7 BIT(13) 31 #define DECODE_ENABLE_AUDIO_PORT0 BIT(14) 32 #define DECODE_ENABLE_AUDIO_PORT1 BIT(15) 33 #define DECODE_ENABLE_AUDIO_PORT2 BIT(16) 34 #define DECODE_ENABLE_AUDIO_PORT3 BIT(17) 35 #define DECODE_ENABLE_MIDI_PORT0 BIT(18) 36 #define DECODE_ENABLE_MIDI_PORT1 BIT(19) 37 #define DECODE_ENABLE_MIDI_PORT2 BIT(20) 38 #define DECODE_ENABLE_MIDI_PORT3 BIT(21) 39 #define DECODE_ENABLE_MSS_PORT0 BIT(22) 40 #define DECODE_ENABLE_MSS_PORT1 BIT(23) 41 #define DECODE_ENABLE_MSS_PORT2 BIT(24) 42 #define DECODE_ENABLE_MSS_PORT3 BIT(25) 43 #define DECODE_ENABLE_FDC_PORT0 BIT(26) 44 #define DECODE_ENABLE_FDC_PORT1 BIT(27) 45 #define DECODE_ENABLE_GAME_PORT BIT(28) 46 #define DECODE_ENABLE_KBC_PORT BIT(29) 47 #define DECODE_ENABLE_ACPIUC_PORT BIT(30) 48 #define DECODE_ENABLE_ADLIB_PORT BIT(31) 49 50 #define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 51 #define LPC_WIDEIO2_ENABLE BIT(25) 52 #define LPC_WIDEIO1_ENABLE BIT(24) 53 #define DECODE_IO_PORT_ENABLE6 BIT(23) 54 #define DECODE_IO_PORT_ENABLE5 BIT(22) 55 #define DECODE_IO_PORT_ENABLE4 BIT(21) 56 #define DECODE_MEM_PORT_ENABLE1 BIT(20) 57 #define DECODE_IO_PORT_ENABLE3 BIT(19) 58 #define DECODE_IO_PORT_ENABLE2 BIT(18) 59 #define DECODE_IO_PORT_ENABLE1 BIT(17) 60 #define DECODE_IO_PORT_ENABLE0 BIT(16) 61 #define LPC_SYNC_TIMEOUT_COUNT_MASK (0xff << 8) 62 #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) 63 #define LPC_DECODE_RTC_IO_ENABLE BIT(6) 64 #define DECODE_MEM_PORT_ENABLE0 BIT(5) 65 #define LPC_WIDEIO0_ENABLE BIT(2) 66 #define DECODE_ALTERNATE_SIO_ENABLE BIT(1) 67 #define DECODE_SIO_ENABLE BIT(0) 68 #define LPC_SELECT_SIO_4E4F 1 69 #define LPC_SELECT_SIO_2E2F 0 70 #define WIDEIO_RANGE_ERROR -1 71 72 #define LPC_MEM_PORT1 0x4c 73 #define ROM_PROTECT_RANGE0 0x50 74 #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ 75 #define ROM_RANGE_WP BIT(10) 76 #define ROM_RANGE_RP BIT(9) 77 #define RANGE_UNIT BIT(8) /* 0: 4kiB, 1: 64kiB */ 78 #define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ 79 #define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) 80 #define MAX_ROM_PROTECT_RANGES 4 81 #define LPC_MEM_PORT0 0x60 82 83 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. 84 For ease of access, each sub-register is declared separately. */ 85 #define LPC_WIDEIO_GENERIC_PORT 0x64 86 #define LPC_WIDEIO1_GENERIC_PORT 0x66 87 #define ROM_ADDRESS_RANGE1_START 0x68 88 #define ROM_ADDRESS_RANGE1_END 0x6a 89 #define ROM_ADDRESS_RANGE2_START 0x6c 90 #define ROM_ADDRESS_RANGE2_END 0x6e 91 92 #define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 93 #define LPC_ALT_WIDEIO2_ENABLE BIT(3) 94 #define LPC_ALT_WIDEIO1_ENABLE BIT(2) 95 #define LPC_ALT_WIDEIO0_ENABLE BIT(0) 96 97 #define LPC_MISC_CONTROL_BITS 0x78 98 #define LPC_LDRQ1_EN BIT(3) 99 #define LPC_LDRQ0_EN BIT(2) 100 #define LPC_NOHOG BIT(0) 101 102 #define LPC_TRUSTED_PLATFORM_MODULE 0x7c 103 #define TPM_12_EN BIT(0) 104 #define TPM_LEGACY_EN BIT(2) 105 106 #define LPC_WIDEIO2_GENERIC_PORT 0x90 107 108 #define LPC_ROM_DMA_SRC_ADDR 0xb0 109 #define LPC_ROM_DMA_DST_ADDR 0xb4 110 /* LPC register 0xb8 is DWORD, here there are definitions for byte 111 access. For example, bits 31-24 are accessed through byte access 112 at register 0xbb. */ 113 #define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 114 #define SPI_FROM_HOST_PREFETCH_EN BIT(24) 115 #define SPI_FROM_USB_PREFETCH_EN BIT(23) 116 #define LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT 6 117 #define LPC_ROM_DMA_CTRL_DW_COUNT_MASK (0x3ffUL << LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) 118 #define LPC_ROM_DMA_CTRL_ERROR BIT(1) 119 #define LPC_ROM_DMA_CTRL_START BIT(0) 120 #define LPC_ROM_DMA_MIN_ALIGNMENT (1 << 6) 121 #define LPC_ROM_DMA_CTRL_DW_COUNT(bytes) \ 122 (((bytes / LPC_ROM_DMA_MIN_ALIGNMENT) - 1) << LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) 123 #define LPC_ROM_DMA_CTRL_MAX_BYTES \ 124 (((LPC_ROM_DMA_CTRL_DW_COUNT_MASK >> LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) + 1) \ 125 * LPC_ROM_DMA_MIN_ALIGNMENT) 126 127 #define LPC_HOST_CONTROL 0xbb 128 #define PREFETCH_EN_SPI_FROM_HOST BIT(0) 129 #define T_START_ENH BIT(3) 130 131 /* Clear all decoding to the LPC bus and erase any range registers associated 132 * with the enable bits. */ 133 void lpc_disable_decodes(void); 134 void lpc_enable_port80(void); 135 void lpc_enable_decode(uint32_t decodes); 136 /* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ 137 void lpc_enable_sio_decode(const bool addr); 138 uintptr_t lpc_spibase(void); 139 void lpc_tpm_decode(void); 140 void lpc_tpm_decode_spi(void); 141 void lpc_enable_rom(void); 142 void lpc_enable_spi_prefetch(void); 143 void lpc_disable_spi_rom_sharing(void); 144 145 /** 146 * @brief Find the size of a particular wide IO 147 * 148 * @param index = index of desired wide IO 149 * 150 * @return size of desired wide IO 151 */ 152 uint16_t lpc_wideio_size(int index); 153 /** 154 * @brief Identify if any LPC wide IO is covering the IO range 155 * 156 * @param start = start of IO range 157 * @param size = size of IO range 158 * 159 * @return Index of wide IO covering the range or error 160 */ 161 int lpc_find_wideio_range(uint16_t start, uint16_t size); 162 /** 163 * @brief Program a LPC wide IO to support an IO range 164 * 165 * @param start = start of range to be routed through wide IO 166 * @param size = size of range to be routed through wide IO 167 * 168 * @return Index of wide IO register used or error 169 */ 170 int lpc_set_wideio_range(uint16_t start, uint16_t size); 171 172 uintptr_t lpc_get_spibase(void); 173 174 /* 175 * Perform early initialization for LPC: 176 * 1. Enable LPC controller 177 * 2. Disable any LPC decodes 178 * 3. Set SPI Base which is the MMIO base for both SPI and eSPI controller (if supported by 179 * platform). 180 */ 181 void lpc_early_init(void); 182 183 /* 184 * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform). 185 * 186 * eSPI base = SPI base + 0x10000 187 */ 188 void lpc_set_spibase(uint32_t base); 189 190 /* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */ 191 void lpc_enable_spi_rom(uint32_t enable); 192 193 #endif /* AMD_BLOCK_LPC_H */ 194