1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_IOMAP_H 4 #define AMD_BLOCK_IOMAP_H 5 6 /* 7 * A maximum of 16 MBytes of the SPI flash can be mapped right below the 4 GB boundary. For 8 * region reservation and cacheability configuration purposes, we can use this maximum value 9 * and don't need to make this dependent on the flash size. This also makes sure that in case 10 * of flash sizes above 16 MByte the MMIO region right below won't get configured wrongly. 11 */ 12 #define FLASH_BELOW_4GB_MAPPING_REGION_BASE ((0xffffffff - 16 * MiB) + 1) 13 #define FLASH_BELOW_4GB_MAPPING_REGION_SIZE (16 * MiB) 14 15 #define IOMMU_RESERVED_MMIO_BASE 0xfd00000000 16 #define IOMMU_RESERVED_MMIO_SIZE (4ULL * GiB) 17 18 #endif /* AMD_BLOCK_IOMAP_H */ 19