1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef AMD_BLOCK_DATA_FABRIC_H
4 #define AMD_BLOCK_DATA_FABRIC_H
5
6 #include <amdblocks/data_fabric_defs.h>
7 #include <amdblocks/pci_devs.h>
8 #include <device/device.h>
9 #include <device/pci_ops.h>
10 #include <soc/data_fabric.h>
11 #include <soc/pci_devs.h>
12 #include <stdint.h>
13
14 #define BROADCAST_FABRIC_ID 0xff
15
16 #define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t))
17
18 /* The number of data fabric MMIO registers is SoC-specific */
19 #define DF_MMIO_BASE(reg) (DF_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg))
20 #define DF_MMIO_LIMIT(reg) (DF_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg))
21 #define DF_MMIO_CONTROL(reg) (DF_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg))
22 #if CONFIG(SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO)
23 #define DF_MMIO_ADDR_EXT(reg) (DF_MMIO_ADDR_EXT0 + DF_MMIO_REG_OFFSET(reg))
24 #endif
25
26 /* Last 12GB of the usable address space are reserved */
27 #define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB)
28
29 uint32_t data_fabric_read32(uint16_t fn_reg, uint8_t instance_id);
30 void data_fabric_write32(uint16_t fn_reg, uint8_t instance_id, uint32_t data);
31
32 static __always_inline
data_fabric_broadcast_read32(uint16_t fn_reg)33 uint32_t data_fabric_broadcast_read32(uint16_t fn_reg)
34 {
35 /* No bit masking required. Macros will apply mask to values. */
36 return pci_read_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_OFFSET(fn_reg));
37 }
38
39 static __always_inline
data_fabric_broadcast_write32(uint16_t fn_reg,uint32_t data)40 void data_fabric_broadcast_write32(uint16_t fn_reg, uint32_t data)
41 {
42 /* No bit masking required. Macros will apply mask to values. */
43 pci_write_config32(_SOC_DEV(DF_DEV, DF_REG_FN(fn_reg)), DF_REG_OFFSET(fn_reg), data);
44 }
45
46 void data_fabric_print_mmio_conf(void);
47
48 enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *segment_group,
49 uint8_t *first_bus, uint8_t *last_bus);
50
51 void data_fabric_get_mmio_base_size(unsigned int reg, resource_t *mmio_base,
52 resource_t *mmio_limit);
53
54 /* Inform the resource allocator about the usable IO and MMIO regions and PCI bus numbers */
55 void amd_pci_domain_read_resources(struct device *domain);
56 void amd_pci_domain_scan_bus(struct device *domain);
57
58 #endif /* AMD_BLOCK_DATA_FABRIC_H */
59