1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef AGX5_SOCFPGA_SYSTEMMANAGER_H 7 #define AGX5_SOCFPGA_SYSTEMMANAGER_H 8 9 #include "socfpga_plat_def.h" 10 11 /* System Manager Register Map */ 12 #define SOCFPGA_SYSMGR_SILICONID_1 0x00 13 #define SOCFPGA_SYSMGR_SILICONID_2 0x04 14 #define SOCFPGA_SYSMGR_WDDBG 0x08 15 #define SOCFPGA_SYSMGR_MPU_STATUS 0x10 16 #define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C 17 #define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 18 #define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 19 #define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C 20 #define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 21 #define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ 22 #define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ 23 #define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ 24 #define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 25 #define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 26 #define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 27 #define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 28 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C 29 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 30 #define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 31 #define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 32 #define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C 33 #define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 34 #define SOCFPGA_SYSMGR_OSC_TRIM 0x84 35 #define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 36 #define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C 37 #define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 38 #define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 39 #define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 40 #define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C 41 #define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 42 /* NOC configuration value */ 43 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 44 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 45 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 46 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC 47 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 48 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 49 #define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 50 #define SOCFPGA_SYSMGR_FPGA_CFG 0xDC 51 #define SOCFPGA_SYSMGR_GPO 0xE4 52 #define SOCFPGA_SYSMGR_GPI 0xE8 53 #define SOCFPGA_SYSMGR_MPU 0xF0 54 #define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 55 #define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 56 #define SOCFPGA_SYSMGR_DFI_INTF 0xFC 57 #define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 58 #define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 59 #define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 60 #define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C 61 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 62 #define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 63 #define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 64 #define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C 65 #define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 66 #define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 67 #define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 68 #define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C 69 #define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 70 #define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 71 #define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 72 #define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C 73 #define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 74 #define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 75 #define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 76 #define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C 77 #define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 78 #define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 79 #define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 80 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C 81 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 82 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 83 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 84 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C 85 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 86 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 87 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 88 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C 89 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 90 #define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 91 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 92 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C 93 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 94 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 95 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 96 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C 97 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 98 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 99 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 100 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC 101 #define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 102 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 103 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 104 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC 105 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 106 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 107 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 108 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC 109 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 110 #define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 111 #define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 112 113 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 114 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 115 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 116 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C 117 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 118 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 119 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 120 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C 121 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 122 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 123 #define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 124 #define SOCFPGA_SYSMGR_MPFE_status 0x22C 125 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 126 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 127 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 128 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C 129 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 130 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 131 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 132 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C 133 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 134 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 135 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 136 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C 137 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 138 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 139 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 140 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C 141 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 142 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 143 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 144 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C 145 #define SOCFPGA_SYSMGR_SDM_BE_AWADDR_REMAP 0x280 146 #define SOCFPGA_SYSMGR_SDM_BE_ARADDR_REMAP 0x284 147 148 /* QSPI ECC from SDM register */ 149 #define SOCFPGA_ECC_QSPI_CTRL 0x08 150 #define SOCFPGA_ECC_QSPI_ERRINTEN 0x10 151 #define SOCFPGA_ECC_QSPI_ERRINTENS 0x14 152 #define SOCFPGA_ECC_QSPI_ERRINTENR 0x18 153 #define SOCFPGA_ECC_QSPI_INTMODE 0x1C 154 #define SOCFPGA_ECC_QSPI_INTSTAT 0x20 155 #define SOCFPGA_ECC_QSPI_INTTEST 0x24 156 #define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78 157 #define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C 158 #define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80 159 160 #define DMA0_STREAM_CTRL_REG 0x10D1217C 161 #define DMA1_STREAM_CTRL_REG 0x10D12180 162 #define SDM_STREAM_CTRL_REG 0x10D12184 163 #define USB2_STREAM_CTRL_REG 0x10D12188 164 #define USB3_STREAM_CTRL_REG 0x10D1218C 165 #define SDMMC_STREAM_CTRL_REG 0x10D12190 166 #define NAND_STREAM_CTRL_REG 0x10D12194 167 #define ETR_STREAM_CTRL_REG 0x10D12198 168 #define TSN0_STREAM_CTRL_REG 0x10D1219C 169 #define TSN1_STREAM_CTRL_REG 0x10D121A0 170 #define TSN2_STREAM_CTRL_REG 0x10D121A4 171 172 /* Stream ID configuration value for Agilex5 */ 173 #define TSN0 0x00010001 174 #define TSN1 0x00020002 175 #define TSN2 0x00030003 176 #define NAND 0x00040004 177 #define SDMMC 0x00050005 178 #define USB0 0x00060006 179 #define USB1 0x00070007 180 #define DMA0 0x00080008 181 #define DMA1 0x00090009 182 #define SDM 0x000A000A 183 #define CORE_SIGHT_DEBUG 0x000B000B 184 185 /* Field Masking */ 186 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 187 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 188 189 #define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0) 190 #define IDLE_DATA_LWSOC2FPGA BIT(4) 191 #define IDLE_DATA_SOC2FPGA BIT(0) 192 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \ 193 | IDLE_DATA_SOC2FPGA) 194 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 195 #define SYSMGR_ECC_DDR0_MASK BIT(16) 196 #define SYSMGR_ECC_DDR1_MASK BIT(17) 197 198 #define WSTREAMIDEN_REG_CTRL BIT(0) 199 #define RSTREAMIDEN_REG_CTRL BIT(1) 200 #define WMMUSECSID_REG_VAL BIT(4) 201 #define RMMUSECSID_REG_VAL BIT(5) 202 203 /* Macros */ 204 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ 205 + (SOCFPGA_ECC_QSPI_##_reg)) 206 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 207 + (SOCFPGA_SYSMGR_##_reg)) 208 #define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \ 209 | RSTREAMIDEN_REG_CTRL 210 #define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \ 211 | RSTREAMIDEN_REG_CTRL \ 212 | WMMUSECSID_REG_VAL \ 213 | RMMUSECSID_REG_VAL 214 215 #endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */ 216