1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef POWERMANAGER_H 8 #define POWERMANAGER_H 9 10 #include "socfpga_handoff.h" 11 12 #define AGX5_PWRMGR_BASE 0x10d14000 13 14 /* DSU */ 15 #define AGX5_PWRMGR_DSU_FWENCTL 0x0 16 #define AGX5_PWRMGR_DSU_PGENCTL 0x4 17 #define AGX5_PWRMGR_DSU_PGSTAT 0x8 18 #define AGX5_PWRMGR_DSU_PWRCTLR 0xc 19 #define AGX5_PWRMGR_DSU_PWRSTAT0 0x10 20 #define AGX5_PWRMGR_DSU_PWRSTAT1 0x14 21 22 /* DSU Macros*/ 23 #define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf) 24 #define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf) 25 #define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf) 26 #define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1) 27 #define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1) 28 #define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8) 29 #define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31) 30 #define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff) 31 #define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8) 32 #define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16) 33 #define AGX5_PWRMGR_DSU_MULTI_PCH_DONE(x) (((x) & 0x1) << 31) 34 35 /* CPU */ 36 #define AGX5_PWRMGR_CPU_PWRCTLR0 0x18 37 #define AGX5_PWRMGR_CPU_PWRCTLR1 0x20 38 #define AGX5_PWRMGR_CPU_PWRCTLR2 0x28 39 #define AGX5_PWRMGR_CPU_PWRCTLR3 0x30 40 #define AGX5_PWRMGR_CPU_PWRSTAT0 0x1c 41 #define AGX5_PWRMGR_CPU_PWRSTAT1 0x24 42 #define AGX5_PWRMGR_CPU_PWRSTAT2 0x2c 43 #define AGX5_PWRMGR_CPU_PWRSTAT3 0x34 44 45 /* APS */ 46 #define AGX5_PWRMGR_APS_FWENCTL 0x38 47 #define AGX5_PWRMGR_APS_PGENCTL 0x3C 48 #define AGX5_PWRMGR_APS_PGSTAT 0x40 49 50 /* PSS */ 51 #define AGX5_PWRMGR_PSS_FWENCTL 0x44 52 #define AGX5_PWRMGR_PSS_PGENCTL 0x48 53 #define AGX5_PWRMGR_PSS_PGSTAT 0x4c 54 55 /* PSS Macros*/ 56 #define AGX5_PWRMGR_PSS_FWEN(x) ((x) & 0xff) 57 #define AGX5_PWRMGR_PSS_PGEN(x) ((x) & 0xff) 58 #define AGX5_PWRMGR_PSS_PGEN_OUT(x) ((x) & 0xff) 59 60 /* MPU */ 61 #define AGX5_PWRMGR_MPU_PCHCTLR 0x50 62 #define AGX5_PWRMGR_MPU_PCHSTAT 0x54 63 #define AGX5_PWRMGR_MPU_BOOTCONFIG 0x58 64 #define AGX5_PWRMGR_CPU_POWER_STATE_MASK 0x1E 65 66 /* MPU Macros*/ 67 #define AGX5_PWRMGR_MPU_TRIGGER_PCH_DSU(x) ((x) & 0x1) 68 #define AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(x) (((x) & 0xf) << 1) 69 #define AGX5_PWRMGR_MPU_STATUS_PCH_CPU(x) (((x) & 0xf) << 1) 70 71 /* Shared Macros */ 72 #define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ 73 (AGX5_PWRMGR_##_reg)) 74 75 /* POWER MANAGER ERROR CODE */ 76 #define AGX5_PWRMGR_HANDOFF_PERIPHERAL -1 77 #define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0 78 #define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0) 79 80 int pss_sram_power_off(handoff *hoff_ptr); 81 int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff); 82 83 #endif 84