xref: /aosp_15_r20/external/mesa3d/src/amd/common/ac_nir_helpers.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2024 Valve Corporation
3  *
4  * SPDX-License-Identifier: MIT
5  */
6 
7 
8 #ifndef AC_NIR_HELPERS_H
9 #define AC_NIR_HELPERS_H
10 
11 #include "ac_hw_stage.h"
12 #include "ac_shader_args.h"
13 #include "ac_shader_util.h"
14 #include "nir.h"
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 #define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \
21    do { \
22       if ((store_val)->bit_size >= 32) { \
23          const unsigned store_write_mask = (write_mask); \
24          const unsigned store_const_offset = (const_offset); \
25          func((b), (store_val), __VA_ARGS__); \
26       } else { \
27          u_foreach_bit(c, (write_mask)) { \
28             const unsigned store_write_mask = 1; \
29             const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \
30             nir_def *store_component = nir_channel(b, (store_val), c); \
31             func((b), store_component, __VA_ARGS__); \
32          } \
33       } \
34    } while (0)
35 
36 #define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \
37    do { \
38       const unsigned load_bit_size = MAX2(32, (bit_size)); \
39       (load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \
40       if ((bit_size) < load_bit_size) { \
41          if ((hi_16bit)) { \
42             (load) = nir_unpack_32_2x16_split_y(b, load); \
43          } else { \
44             (load) = nir_unpack_32_2x16_split_x(b, load); \
45          } \
46       } \
47    } while (0)
48 
49 typedef struct
50 {
51    /* GS output stream index, 2 bit per component */
52    uint8_t stream;
53    /* Bitmask of components used: 4 bits per slot, 1 bit per component. */
54    uint8_t components_mask : 4;
55 } ac_nir_prerast_per_output_info;
56 
57 typedef struct
58 {
59    nir_def *outputs[VARYING_SLOT_MAX][4];
60    nir_def *outputs_16bit_lo[16][4];
61    nir_def *outputs_16bit_hi[16][4];
62 
63    nir_alu_type types[VARYING_SLOT_MAX][4];
64    nir_alu_type types_16bit_lo[16][4];
65    nir_alu_type types_16bit_hi[16][4];
66 
67    ac_nir_prerast_per_output_info infos[VARYING_SLOT_MAX];
68    ac_nir_prerast_per_output_info infos_16bit_lo[16];
69    ac_nir_prerast_per_output_info infos_16bit_hi[16];
70 } ac_nir_prerast_out;
71 
72 /* Maps I/O semantics to the actual location used by the lowering pass. */
73 typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
74 
75 /* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
76 struct nir_builder;
77 typedef struct nir_builder nir_builder;
78 
79 /* Executed by ac_nir_cull when the current primitive is accepted. */
80 typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state);
81 
82 void
83 ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value,
84                             unsigned component, unsigned writemask);
85 
86 void
87 ac_nir_gather_prerast_store_output_info(nir_builder *b,
88                                         nir_intrinsic_instr *intrin,
89                                         ac_nir_prerast_out *out);
90 
91 void
92 ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row);
93 
94 void
95 ac_nir_export_position(nir_builder *b,
96                        enum amd_gfx_level gfx_level,
97                        uint32_t clip_cull_mask,
98                        bool no_param_export,
99                        bool force_vrs,
100                        bool done,
101                        uint64_t outputs_written,
102                        nir_def *(*outputs)[4],
103                        nir_def *row);
104 
105 void
106 ac_nir_export_parameters(nir_builder *b,
107                          const uint8_t *param_offsets,
108                          uint64_t outputs_written,
109                          uint16_t outputs_written_16bit,
110                          nir_def *(*outputs)[4],
111                          nir_def *(*outputs_16bit_lo)[4],
112                          nir_def *(*outputs_16bit_hi)[4]);
113 
114 nir_def *
115 ac_nir_calc_io_off(nir_builder *b,
116                              nir_intrinsic_instr *intrin,
117                              nir_def *base_stride,
118                              unsigned component_stride,
119                              unsigned mapped_location);
120 
121 unsigned
122 ac_nir_map_io_location(unsigned location,
123                        uint64_t mask,
124                        ac_nir_map_io_driver_location map_io);
125 
126 nir_def *
127 ac_nir_cull_primitive(nir_builder *b,
128                       nir_def *initially_accepted,
129                       nir_def *pos[3][4],
130                       unsigned num_vertices,
131                       ac_nir_cull_accepted accept_func,
132                       void *state);
133 
134 void
135 ac_nir_sleep(nir_builder *b, unsigned num_cycles);
136 
137 nir_def *
138 ac_average_samples(nir_builder *b, nir_def **samples, unsigned num_samples);
139 
140 void
141 ac_optimization_barrier_vgpr_array(const struct radeon_info *info, nir_builder *b,
142                                    nir_def **array, unsigned num_elements,
143                                    unsigned num_components);
144 
145 nir_def *
146 ac_get_global_ids(nir_builder *b, unsigned num_components, unsigned bit_size);
147 
148 #ifdef __cplusplus
149 }
150 #endif
151 
152 #endif /* AC_NIR_HELPERS_H */
153