xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2013 Rob Clark <[email protected]>
3  * SPDX-License-Identifier: MIT
4  *
5  * Authors:
6  *    Rob Clark <[email protected]>
7  */
8 
9 #include "pipe/p_state.h"
10 #include "util/u_memory.h"
11 #include "util/u_string.h"
12 
13 #include "fd3_context.h"
14 #include "fd3_format.h"
15 #include "fd3_zsa.h"
16 
17 void *
fd3_zsa_state_create(struct pipe_context * pctx,const struct pipe_depth_stencil_alpha_state * cso)18 fd3_zsa_state_create(struct pipe_context *pctx,
19                      const struct pipe_depth_stencil_alpha_state *cso)
20 {
21    struct fd3_zsa_stateobj *so;
22 
23    so = CALLOC_STRUCT(fd3_zsa_stateobj);
24    if (!so)
25       return NULL;
26 
27    so->base = *cso;
28 
29    so->rb_depth_control |=
30       A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */
31 
32    if (cso->depth_enabled)
33       so->rb_depth_control |=
34          A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE | A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE;
35 
36    if (cso->depth_writemask)
37       so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
38 
39    if (cso->stencil[0].enabled) {
40       const struct pipe_stencil_state *s = &cso->stencil[0];
41 
42       so->rb_stencil_control |=
43          A3XX_RB_STENCIL_CONTROL_STENCIL_READ |
44          A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
45          A3XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
46          A3XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
47          A3XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
48          A3XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
49       so->rb_stencilrefmask |=
50          0xff000000 | /* ??? */
51          A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
52          A3XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
53 
54       if (cso->stencil[1].enabled) {
55          const struct pipe_stencil_state *bs = &cso->stencil[1];
56 
57          so->rb_stencil_control |=
58             A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
59             A3XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
60             A3XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
61             A3XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
62             A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
63          so->rb_stencilrefmask_bf |=
64             0xff000000 | /* ??? */
65             A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
66             A3XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
67       }
68    }
69 
70    if (cso->alpha_enabled) {
71       so->rb_render_control =
72          A3XX_RB_RENDER_CONTROL_ALPHA_TEST |
73          A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);
74       so->rb_alpha_ref = A3XX_RB_ALPHA_REF_UINT(cso->alpha_ref_value * 255.0f) |
75                          A3XX_RB_ALPHA_REF_FLOAT(cso->alpha_ref_value);
76       so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
77    }
78 
79    return so;
80 }
81