1 /*============================================================================== 2 Copyright(c) 2024 Intel Corporation 3 Permission is hereby granted, free of charge, to any person obtaining a 4 copy of this software and associated documentation files(the "Software"), 5 to deal in the Software without restriction, including without limitation 6 the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 and / or sell copies of the Software, and to permit persons to whom the 8 Software is furnished to do so, subject to the following conditions: 9 10 The above copyright notice and this permission notice shall be included 11 in all copies or substantial portions of the Software. 12 13 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 14 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 OTHER DEALINGS IN THE SOFTWARE. 20 ============================================================================*/ 21 22 #pragma once 23 24 #ifdef __cplusplus 25 #include "../GmmCachePolicyCommon.h" 26 27 #define GMM_XE2_NUM_MOCS_ENTRIES (16) 28 #define GMM_XE2_DEFAULT_PAT_INDEX (PAT2) 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif /*__cplusplus*/ 34 35 typedef enum GMM_GFX_PHY_L4_MEMORY_TYPE_REC 36 { 37 GMM_GFX_PHY_L4_MT_WB = 0x0, 38 GMM_GFX_PHY_L4_MT_WT = 0x1, 39 GMM_GFX_PHY_L4_MT_UC = 0x3, 40 } GMM_GFX_PHY_L4_MEMORY_TYPE; 41 42 typedef enum GMM_GFX_PHY_L3_MEMORY_TYPE_REC 43 { 44 GMM_GFX_PHY_L3_MT_WB = 0x0, 45 GMM_GFX_PHY_L3_MT_WB_XD = 0x1, // Transient Flush Display 46 GMM_GFX_PHY_L3_MT_UC = 0x3, 47 } GMM_GFX_PHY_L3_MEMORY_TYPE; 48 49 typedef enum GMM_GFX_PHY_CACHE_COHERENCY_TYPE_REC 50 { 51 GMM_GFX_PHY_NON_COHERENT_NO_SNOOP = 0x0, 52 GMM_GFX_PHY_NON_COHERENT = 0x1, 53 GMM_GFX_PHY_COHERENT_ONE_WAY_IA_SNOOP = 0x2, 54 GMM_GFX_PHY_COHERENT_TWO_WAY_IA_GPU_SNOOP = 0x3 55 } GMM_GFX_PHY_CACHE_COHERENCY_TYPE; 56 57 typedef union GMM_XE2_PRIVATE_PAT_REC 58 { 59 struct 60 { 61 uint32_t Coherency : 2; 62 uint32_t L4CC : 2; 63 uint32_t L3CC : 2; 64 uint32_t L3CLOS : 2; 65 uint32_t Reserved1 : 1; 66 uint32_t LosslessCompressionEn: 1; 67 uint32_t Reserved2 : 22; 68 } Xe2; 69 uint32_t Value; 70 } GMM_XE2_PRIVATE_PAT; 71 72 namespace GmmLib 73 { 74 class NON_PAGED_SECTION GmmXe2_LPGCachePolicy : public GmmXe_LPGCachePolicy 75 { 76 protected: 77 78 public: 79 /* Constructors */ GmmXe2_LPGCachePolicy(GMM_CACHE_POLICY_ELEMENT * pCachePolicyContext,Context * pGmmLibContext)80 GmmXe2_LPGCachePolicy(GMM_CACHE_POLICY_ELEMENT *pCachePolicyContext, Context *pGmmLibContext) 81 : GmmXe_LPGCachePolicy(pCachePolicyContext, pGmmLibContext) 82 { 83 NumPATRegisters = GMM_NUM_PAT_ENTRIES; 84 NumMOCSRegisters = GMM_XE2_NUM_MOCS_ENTRIES; 85 CurrentMaxPATIndex = 0; 86 CurrentMaxMocsIndex = 0; 87 } ~GmmXe2_LPGCachePolicy()88 virtual ~GmmXe2_LPGCachePolicy() 89 { 90 } 91 92 /* Function prototypes */ 93 GMM_STATUS InitCachePolicy(); 94 GMM_STATUS SetupPAT(); 95 void SetUpMOCSTable(); 96 void GetL3L4(GMM_CACHE_POLICY_TBL_ELEMENT *pUsageEle, GMM_XE2_PRIVATE_PAT *pUsagePATElement, uint32_t Usage); 97 uint32_t GMM_STDCALL CachePolicyGetPATIndex(GMM_RESOURCE_INFO *pResInfo, GMM_RESOURCE_USAGE_TYPE Usage, bool *pCompressionEnable, bool IsCpuCacheable); 98 }; 99 } // namespace GmmLib 100 #endif // #ifdef __cplusplus 101 102 #ifdef __cplusplus 103 } 104 #endif /* end__cplusplus*/ 105