1 /**
2 ******************************************************************************
3 * @file stm32wbxx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.</center></h2>
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32wbxx_hal.h"
27
28 /** @addtogroup STM32WBxx_HAL_Driver
29 * @{
30 */
31
32 /** @addtogroup PWR
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40 /* Private macro -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup PWR_Private_Defines
44 * @{
45 */
46
47 /** @defgroup PWR_Register_Reset_Values PWR Register Reset Values
48 * @{
49 */
50 /* Definitions of PWR registers reset value */
51 #define PWR_CR1_RESET_VALUE (0x00000200U)
52 #define PWR_CR2_RESET_VALUE (0x00000000U)
53 #define PWR_CR3_RESET_VALUE (0x00008000U)
54 #define PWR_CR4_RESET_VALUE (0x00000000U)
55 #define PWR_CR5_RESET_VALUE (0x00004204U)
56 #define PWR_PUCRA_RESET_VALUE (0x00000000U)
57 #define PWR_PDCRA_RESET_VALUE (0x00000000U)
58 #define PWR_PUCRB_RESET_VALUE (0x00000000U)
59 #define PWR_PDCRB_RESET_VALUE (0x00000000U)
60 #define PWR_PUCRC_RESET_VALUE (0x00000000U)
61 #define PWR_PDCRC_RESET_VALUE (0x00000000U)
62 #define PWR_PUCRD_RESET_VALUE (0x00000000U)
63 #define PWR_PDCRD_RESET_VALUE (0x00000000U)
64 #define PWR_PUCRE_RESET_VALUE (0x00000000U)
65 #define PWR_PDCRE_RESET_VALUE (0x00000000U)
66 #define PWR_PUCRH_RESET_VALUE (0x00000000U)
67 #define PWR_PDCRH_RESET_VALUE (0x00000000U)
68 #define PWR_C2CR1_RESET_VALUE (0x00000000U)
69 #define PWR_C2CR3_RESET_VALUE (0x00008000U)
70 /**
71 * @}
72 */
73
74 /**
75 * @}
76 */
77
78 /* Private function prototypes -----------------------------------------------*/
79 /* Exported functions --------------------------------------------------------*/
80 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
81 * @{
82 */
83
84 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
85 * @brief Initialization and de-initialization functions
86 *
87 @verbatim
88 ===============================================================================
89 ##### Initialization and de-initialization functions #####
90 ===============================================================================
91 [..]
92
93 @endverbatim
94 * @{
95 */
96
97 /**
98 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
99 * @retval None
100 */
HAL_PWR_DeInit(void)101 void HAL_PWR_DeInit(void)
102 {
103 /* Apply reset values to all PWR registers */
104 /* Note: Update of each register required since PWR global reset is not */
105 /* available at RCC level on this STM32 serie. */
106 LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
107 LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
108 LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
109 LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
110 LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
111 LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
112 LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
113 LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
114 LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
115 LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
116 LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
117 #if defined(GPIOD)
118 LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
119 LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
120 #endif
121 LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
122 LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
123 LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
124 LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
125 LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
126 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
127
128 /* Clear all flags */
129 LL_PWR_WriteReg(SCR,
130 LL_PWR_SCR_CC2HF
131 | LL_PWR_SCR_C802AF
132 | LL_PWR_SCR_CBLEAF
133 | LL_PWR_SCR_CCRPEF
134 | LL_PWR_SCR_C802WUF
135 | LL_PWR_SCR_CBLEWUF
136 #if defined(PWR_CR5_SMPSEN)
137 | LL_PWR_SCR_CBORHF
138 | LL_PWR_SCR_CSMPSFBF
139 #endif
140 | LL_PWR_SCR_CWUF
141 );
142
143 LL_PWR_WriteReg(EXTSCR,
144 LL_PWR_EXTSCR_CCRPF
145 | LL_PWR_EXTSCR_C2CSSF
146 | LL_PWR_EXTSCR_C1CSSF
147 );
148 }
149
150
151 /**
152 * @brief Enable access to the backup domain
153 * (RTC registers, RTC backup data registers).
154 * @note After reset, the backup domain is protected against
155 * possible unwanted write accesses.
156 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
157 * In order to set or modify the RTC clock, the backup domain access must be
158 * disabled.
159 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
160 * back-up domain.
161 * @retval None
162 */
HAL_PWR_EnableBkUpAccess(void)163 void HAL_PWR_EnableBkUpAccess(void)
164 {
165 SET_BIT(PWR->CR1, PWR_CR1_DBP);
166 }
167
168 /**
169 * @brief Disable access to the backup domain
170 * (RTC registers, RTC backup data registers).
171 * @retval None
172 */
HAL_PWR_DisableBkUpAccess(void)173 void HAL_PWR_DisableBkUpAccess(void)
174 {
175 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
176 }
177
178 /**
179 * @}
180 */
181
182
183 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
184 * @brief Low Power modes configuration functions
185 *
186 @verbatim
187
188 ===============================================================================
189 ##### Peripheral Control functions #####
190 ===============================================================================
191
192 [..]
193 *** PVD configuration ***
194 =========================
195 [..]
196 (+) The PVD is used to monitor the VDD power supply by comparing it to a
197 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
198 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
199 than the PVD threshold. This event is internally connected to the EXTI
200 line16 and can generate an interrupt if enabled. This is done through
201 __HAL_PVD_EXTI_ENABLE_IT() macro.
202 (+) The PVD is stopped in Standby mode.
203
204 *** WakeUp pin configuration ***
205 ================================
206 [..]
207 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
208 The polarity of these pins can be set to configure event detection on high
209 level (rising edge) or low level (falling edge).
210
211 *** Low Power modes configuration ***
212 =====================================
213 [..]
214 The devices feature 8 low-power modes:
215
216 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
217
218 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
219 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
220
221 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
222 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
223 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
224
225 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
226 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
227
228 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
229
230
231 *** Low-power run mode ***
232 ==========================
233 [..]
234 (+) Entry: (from main run mode)
235 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
236 (+) Exit:
237 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
238 then can the system clock frequency be increased above 2 MHz.
239
240 *** Sleep mode / Low-power sleep mode ***
241 =========================================
242 [..]
243 (+) Entry:
244 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
245 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
246 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
247 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
248 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
249 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
250 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
251
252 (+) WFI Exit:
253 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
254 controller (NVIC) or any wake-up event.
255
256 (+) WFE Exit:
257 (++) Any wake-up event such as an EXTI line configured in event mode.
258
259 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
260 the MCU is in Low-power Run mode.
261
262 *** Stop 0, Stop 1 and Stop 2 modes ***
263 ===============================
264 [..]
265 (+) Entry:
266 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
267 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
268 or for porting reasons HAL_PWR_EnterSTOPMode().
269
270 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
271 (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
272 (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
273 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
274 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
275 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
276 (+) WFI Exit:
277 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
278 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
279 when programmed in wakeup mode.
280 (+) WFE Exit:
281 (++) Any EXTI Line (Internal or External) configured in Event mode.
282
283 [..]
284 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
285 depending on the LPR bit setting.
286 When exiting Stop 2 mode, the MCU is in Run mode.
287
288 *** Standby mode ***
289 ====================
290 [..] The Standby mode offers two options:
291 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
292 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
293 and Standby circuitry.
294 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
295 SRAM and register contents are lost except for the RTC registers, RTC backup registers
296 and Standby circuitry.
297
298 (++) Entry:
299 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
300 SRAM1 and register contents are lost except for registers in the Backup domain and
301 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
302 To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
303 to set RRS bit.
304 (++) Exit:
305 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
306 external reset in NRST pin, IWDG reset.
307 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
308
309
310 *** Shutdown mode ***
311 ======================
312 [..]
313 In Shutdown mode,
314 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
315 SRAM and registers contents are lost except for backup domain registers.
316 (+) Entry:
317 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
318 (+) Exit:
319 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
320 external reset in NRST pin.
321 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
322
323
324 *** Auto-wakeup (AWU) from low-power mode ***
325 =============================================
326 [..]
327 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
328 Wakeup event, a tamper event or a time-stamp event, without depending on
329 an external interrupt (Auto-wakeup mode).
330
331 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
332
333
334 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
335 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
336
337 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
338 is necessary to configure the RTC to detect the tamper or time stamp event using the
339 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
340
341 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
342 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
343
344 @endverbatim
345 * @{
346 */
347
348 /**
349 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
350 * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
351 * configuration information.
352 * @note Refer to the electrical characteristics of your device datasheet for
353 * more details about the voltage thresholds corresponding to each
354 * detection level.
355 * @note If "sConfigPVD->Mode" is set to PVD_MODE_IT,
356 * wake-up target is set by default to wake-up target CPU1.
357 * To select wake-up target to CPU2, additional configuration must be
358 * performed using macro "__HAL_PWR_PVD_EXTIC2_ENABLE_IT()"
359 * (and optionally, to select CPU2 only (not both CPU1 and CPU2):
360 * "__HAL_PWR_PVD_EXTI_DISABLE_IT()").
361 * @retval None
362 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)363 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
364 {
365 /* Check the parameters */
366 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
367 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
368
369 /* Set PLS bits according to PVDLevel value */
370 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
371
372 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
373
374 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
375 /* (only interruption is available through AIEC line 16). */
376 __HAL_PWR_PVD_EXTI_DISABLE_IT(); /*CPU1*/
377 __HAL_PWR_PVD_EXTIC2_DISABLE_IT(); /*CPU2*/
378
379 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
380 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
381
382 /* Configure interrupt mode */
383 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
384 {
385 /* Set CPU1 as wakeup target */
386 __HAL_PWR_PVD_EXTI_ENABLE_IT();
387 }
388
389 /* Configure the edge */
390 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
391 {
392 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
393 }
394
395 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
396 {
397 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
398 }
399
400 return HAL_OK;
401 }
402
403 /**
404 * @brief Enables the Power Voltage Detector(PVD).
405 * @retval None
406 */
HAL_PWR_EnablePVD(void)407 void HAL_PWR_EnablePVD(void)
408 {
409 /* Enable the power voltage detector */
410 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
411 }
412
413 /**
414 * @brief Disables the Power Voltage Detector(PVD).
415 * @retval None
416 */
HAL_PWR_DisablePVD(void)417 void HAL_PWR_DisablePVD(void)
418 {
419 /* Disable the power voltage detector */
420 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
421 }
422
423
424 /**
425 * @brief Enable the WakeUp PINx functionality.
426 * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
427 * This parameter can be one of the following legacy values which set the default polarity
428 * i.e. detection on high level (rising edge):
429 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
430 *
431 * or one of the following value where the user can explicitly specify the enabled pin and
432 * the chosen polarity:
433 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
434 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
435 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
436 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
437 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
438 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
439 * @retval None
440 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)441 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
442 {
443 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
444
445 /* Specifies the Wake-Up pin polarity for the event detection
446 (rising or falling edge) */
447 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
448
449 /* Enable wake-up pin */
450 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
451 }
452
453 /**
454 * @brief Disable the WakeUp PINx functionality.
455 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
456 * This parameter can be one of the following values:
457 * @arg PWR_WAKEUP_PIN1: An event on PA0 PIN wakes-up the system from Standby mode.
458 * @arg PWR_WAKEUP_PIN2: An event on PC13 PIN wakes-up the system from Standby mode.
459 * @arg PWR_WAKEUP_PIN3: An event on PC12 PIN wakes-up the system from Standby mode.
460 * @arg PWR_WAKEUP_PIN4: An event on PA2 PIN wakes-up the system from Standby mode.
461 * @arg PWR_WAKEUP_PIN5: An event on PC5 PIN wakes-up the system from Standby mode.
462 * @retval None
463 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)464 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
465 {
466 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
467
468 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
469 }
470
471 /**
472 * @brief Enter Sleep or Low-power Sleep mode.
473 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
474 * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode.
475 * This parameter can be one of the following values:
476 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
477 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
478 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
479 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
480 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
481 * Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register.
482 * Additionally, the clock frequency must be reduced below 2 MHz.
483 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
484 * be done before calling HAL_PWR_EnterSLEEPMode() API.
485 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
486 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
487 * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction.
488 * This parameter can be one of the following values:
489 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
490 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
491 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
492 * the interrupt wake up source.
493 * @retval None
494 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)495 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
496 {
497 /* Check the parameters */
498 assert_param(IS_PWR_REGULATOR(Regulator));
499 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
500
501 /* Set Regulator parameter */
502 if (Regulator == PWR_MAINREGULATOR_ON)
503 {
504 /* If in low-power run mode at this point, exit it */
505 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
506 {
507 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
508 {
509 return ;
510 }
511 }
512 /* Regulator now in main mode. */
513 }
514 else
515 {
516 /* If in run mode, first move to low-power run mode.
517 The system clock frequency must be below 2 MHz at this point. */
518 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
519 {
520 HAL_PWREx_EnableLowPowerRunMode();
521 }
522 }
523
524 /* Clear SLEEPDEEP bit of Cortex System Control Register */
525 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
526
527 /* Select SLEEP mode entry -------------------------------------------------*/
528 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
529 {
530 /* Request Wait For Interrupt */
531 __WFI();
532 }
533 else
534 {
535 /* Request Wait For Event */
536 __SEV();
537 __WFE();
538 __WFE();
539 }
540 }
541
542
543 /**
544 * @brief Enter Stop mode
545 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
546 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
547 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
548 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
549 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
550 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
551 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
552 * only to the peripheral requesting it.
553 * SRAM1, SRAM2 and register contents are preserved.
554 * The BOR is available.
555 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
556 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
557 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
558 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
559 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
560 * startup delay is incurred when waking up.
561 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
562 * is higher although the startup time is reduced.
563 * @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
564 * the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
565 * @note According to system power policy, system entering in Stop mode
566 * is depending on other CPU power mode.
567 * @param Regulator Specifies the regulator state in Stop mode.
568 * This parameter can be one of the following values:
569 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
570 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
571 * @param STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction.
572 * This parameter can be one of the following values:
573 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
574 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
575 * @retval None
576 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)577 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
578 {
579 /* Check the parameters */
580 assert_param(IS_PWR_REGULATOR(Regulator));
581
582 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
583 {
584 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
585 }
586 else
587 {
588 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
589 }
590 }
591
592
593 /**
594 * @brief Enter Standby mode.
595 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
596 * off. The voltage regulator is disabled, except when BKRAM content is preserved
597 * in which case the regulator is in low-power mode.
598 * SRAM and register contents are lost except for registers in the Backup domain and
599 * Standby circuitry. BKRAM content can be preserved if the bit RRS is set in PWR_CR3 register.
600 * To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
601 * to set RRS bit.
602 * The BOR is available.
603 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
604 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
605 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
606 * same.
607 * These states are effective in Standby mode only if APC bit is set through
608 * HAL_PWREx_EnablePullUpPullDownConfig() API.
609 * @note According to system power policy, system entering in Standby mode
610 * is depending on other CPU power mode.
611 * @retval None
612 */
HAL_PWR_EnterSTANDBYMode(void)613 void HAL_PWR_EnterSTANDBYMode(void)
614 {
615 /* Set Stand-by mode */
616 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
617
618 /* Set SLEEPDEEP bit of Cortex System Control Register */
619 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
620
621 /* This option is used to ensure that store operations are completed */
622 #if defined ( __CC_ARM)
623 __force_stores();
624 #endif
625
626 /* Request Wait For Interrupt */
627 __WFI();
628
629 /* Following code is executed after wake up if system did not go to STANDBY
630 mode according to system power policy */
631
632 /* Reset SLEEPDEEP bit of Cortex System Control Register */
633 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
634 }
635
636 /**
637 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
638 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
639 * re-enters SLEEP mode when an interruption handling is over.
640 * Setting this bit is useful when the processor is expected to run only on
641 * interruptions handling.
642 * @retval None
643 */
HAL_PWR_EnableSleepOnExit(void)644 void HAL_PWR_EnableSleepOnExit(void)
645 {
646 /* Set SLEEPONEXIT bit of Cortex System Control Register */
647 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
648 }
649
650 /**
651 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
652 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
653 * re-enters SLEEP mode when an interruption handling is over.
654 * @retval None
655 */
HAL_PWR_DisableSleepOnExit(void)656 void HAL_PWR_DisableSleepOnExit(void)
657 {
658 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
659 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
660 }
661
662
663 /**
664 * @brief Enable CORTEX M4 SEVONPEND bit.
665 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
666 * WFE to wake up when an interrupt moves from inactive to pended.
667 * @retval None
668 */
HAL_PWR_EnableSEVOnPend(void)669 void HAL_PWR_EnableSEVOnPend(void)
670 {
671 /* Set SEVONPEND bit of Cortex System Control Register */
672 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
673 }
674
675
676 /**
677 * @brief Disable CORTEX M4 SEVONPEND bit.
678 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
679 * WFE to wake up when an interrupt moves from inactive to pended.
680 * @retval None
681 */
HAL_PWR_DisableSEVOnPend(void)682 void HAL_PWR_DisableSEVOnPend(void)
683 {
684 /* Clear SEVONPEND bit of Cortex System Control Register */
685 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
686 }
687
688
689 /**
690 * @brief PWR PVD interrupt callback
691 * @retval None
692 */
HAL_PWR_PVDCallback(void)693 __weak void HAL_PWR_PVDCallback(void)
694 {
695 /* NOTE : This function should not be modified; when the callback is needed,
696 the HAL_PWR_PVDCallback can be implemented in the user file
697 */
698 }
699
700 /**
701 * @}
702 */
703
704 /**
705 * @}
706 */
707
708 #endif /* HAL_PWR_MODULE_ENABLED */
709 /**
710 * @}
711 */
712
713 /**
714 * @}
715 */
716
717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
718