1 /**
2 ******************************************************************************
3 * @file stm32wbxx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 *** How to configure Interrupts using CORTEX HAL driver ***
17 ===========================================================
18 [..]
19 This section provides functions allowing to configure the NVIC interrupts (IRQ).
20 The Cortex M0+ exceptions are managed by CMSIS functions.
21 (#) Enable and Configure the priority of the selected IRQ Channels.
22 The priority can be 0..3.
23
24 -@- Lower priority values gives higher priority.
25 -@- Priority Order:
26 (#@) Lowest priority.
27 (#@) Lowest hardware priority (IRQn position).
28
29 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
30
31 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
32
33 -@- Negative value of IRQn_Type are not allowed.
34
35 *** How to configure Systick using CORTEX HAL driver ***
36 ========================================================
37 [..]
38 Setup SysTick Timer for time base.
39
40 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
41 is a CMSIS function that:
42 (++) Configures the SysTick Reload register with value passed as function parameter.
43 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
44 (++) Resets the SysTick Counter register.
45 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
46 (++) Enables the SysTick Interrupt.
47 (++) Starts the SysTick Counter.
48
49 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
50 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
51 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
52 inside the stm32wbxx_hal_cortex.h file.
53
54 (+) You can change the SysTick IRQ priority by calling the
55 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
56 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
57
58 (+) To adjust the SysTick time base, use the following formula:
59
60 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
61 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
62 (++) Reload Value should not exceed 0xFFFFFF
63
64 @endverbatim
65 ******************************************************************************
66 * @attention
67 *
68 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
69 * All rights reserved.</center></h2>
70 *
71 * This software component is licensed by ST under BSD 3-Clause license,
72 * the "License"; You may not use this file except in compliance with the
73 * License. You may obtain a copy of the License at:
74 * opensource.org/licenses/BSD-3-Clause
75 *
76 ******************************************************************************
77 */
78
79 /* Includes ------------------------------------------------------------------*/
80 #include "stm32wbxx_hal.h"
81
82 /** @addtogroup STM32WBxx_HAL_Driver
83 * @{
84 */
85
86 /** @addtogroup CORTEX
87 * @{
88 */
89
90 #ifdef HAL_CORTEX_MODULE_ENABLED
91
92 /* Private types -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private constants ---------------------------------------------------------*/
95 /* Private macros ------------------------------------------------------------*/
96 /* Private function prototypes -----------------------------------------------*/
97 /* Exported functions --------------------------------------------------------*/
98
99 /** @addtogroup CORTEX_Exported_Functions
100 * @{
101 */
102
103
104 /** @addtogroup CORTEX_Exported_Functions_Group1
105 * @brief Initialization and Configuration functions
106 *
107 @verbatim
108 ==============================================================================
109 ##### Initialization and Configuration functions #####
110 ==============================================================================
111 [..]
112 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
113 Systick functionalities
114
115 @endverbatim
116 * @{
117 */
118
119 /**
120 * @brief Set the priority grouping field (pre-emption priority and subpriority)
121 * using the required unlock sequence.
122 * @param PriorityGroup The priority grouping bits length.
123 * This parameter can be one of the following values:
124 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
125 * 4 bits for subpriority
126 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
127 * 3 bits for subpriority
128 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
129 * 2 bits for subpriority
130 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
131 * 1 bit for subpriority
132 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
133 * 0 bit for subpriority
134 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
135 * The pending IRQ priority will be managed only by the subpriority.
136 * @retval None
137 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)138 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
139 {
140 /* Check the parameters */
141 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
142
143 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
144 NVIC_SetPriorityGrouping(PriorityGroup);
145 }
146
147 /**
148 * @brief Set the priority of an interrupt.
149 * @param IRQn External interrupt number.
150 * This parameter can be an enumerator of IRQn_Type enumeration
151 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
152 * @param PreemptPriority The pre-emption priority for the IRQn channel.
153 * This parameter can be a value between 0 and 15
154 * A lower priority value indicates a higher priority
155 * @param SubPriority the subpriority level for the IRQ channel.
156 * This parameter can be a value between 0 and 15
157 * A lower priority value indicates a higher priority.
158 * @retval None
159 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)160 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
161 {
162 uint32_t prioritygroup;
163
164 /* Check the parameters */
165 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
166 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
167
168 prioritygroup = NVIC_GetPriorityGrouping();
169
170 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
171 }
172
173 /**
174 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
175 * @param IRQn External interrupt number.
176 * This parameter can be an enumerator of IRQn_Type enumeration
177 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
178 * @retval None
179 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)180 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
181 {
182 /* Check the parameters */
183 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
184
185 /* Enable interrupt */
186 NVIC_EnableIRQ(IRQn);
187 }
188
189 /**
190 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
191 * @param IRQn External interrupt number.
192 * This parameter can be an enumerator of IRQn_Type enumeration
193 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
194 * @retval None
195 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)196 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
197 {
198 /* Check the parameters */
199 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
200
201 /* Disable interrupt */
202 NVIC_DisableIRQ(IRQn);
203 }
204
205 /**
206 * @brief Initiate a system reset request to reset the MCU.
207 * @retval None
208 */
HAL_NVIC_SystemReset(void)209 void HAL_NVIC_SystemReset(void)
210 {
211 /* System Reset */
212 NVIC_SystemReset();
213 }
214
215 /**
216 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
217 * Counter is in free running mode to generate periodic interrupts.
218 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
219 * @retval status: - 0 Function succeeded.
220 * - 1 Function failed.
221 */
HAL_SYSTICK_Config(uint32_t TicksNumb)222 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
223 {
224 return SysTick_Config(TicksNumb);
225 }
226 /**
227 * @}
228 */
229
230 /** @addtogroup CORTEX_Exported_Functions_Group2
231 * @brief Cortex control functions
232 *
233 @verbatim
234 ==============================================================================
235 ##### Peripheral Control functions #####
236 ==============================================================================
237 [..]
238 This subsection provides a set of functions allowing to control the CORTEX
239 (NVIC, SYSTICK, MPU) functionalities.
240
241
242 @endverbatim
243 * @{
244 */
245
246
247 /**
248 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
249 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
250 */
HAL_NVIC_GetPriorityGrouping(void)251 uint32_t HAL_NVIC_GetPriorityGrouping(void)
252 {
253 /* Get the PRIGROUP[10:8] field value */
254 return NVIC_GetPriorityGrouping();
255 }
256
257 /**
258 * @brief Get the priority of an interrupt.
259 * @param IRQn External interrupt number.
260 * This parameter can be an enumerator of IRQn_Type enumeration
261 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
262 * @param PriorityGroup the priority grouping bits length.
263 * This parameter can be one of the following values:
264 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
265 * 4 bits for subpriority
266 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
267 * 3 bits for subpriority
268 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
269 * 2 bits for subpriority
270 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
271 * 1 bit for subpriority
272 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
273 * 0 bit for subpriority
274 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
275 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
276 * @retval None
277 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)278 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
279 {
280 /* Check the parameters */
281 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
282 /* Get priority for Cortex-M system or device specific interrupts */
283 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
284 }
285
286 /**
287 * @brief Set Pending bit of an external interrupt.
288 * @param IRQn External interrupt number
289 * This parameter can be an enumerator of IRQn_Type enumeration
290 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
291 * @retval None
292 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)293 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
294 {
295 /* Check the parameters */
296 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
297
298 /* Set interrupt pending */
299 NVIC_SetPendingIRQ(IRQn);
300 }
301
302 /**
303 * @brief Get Pending Interrupt (read the pending register in the NVIC
304 * and return the pending bit for the specified interrupt).
305 * @param IRQn External interrupt number.
306 * This parameter can be an enumerator of IRQn_Type enumeration
307 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
308 * @retval status: - 0 Interrupt status is not pending.
309 * - 1 Interrupt status is pending.
310 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)311 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
312 {
313 /* Check the parameters */
314 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
315
316 /* Return 1 if pending else 0 */
317 return NVIC_GetPendingIRQ(IRQn);
318 }
319
320 /**
321 * @brief Clear the pending bit of an external interrupt.
322 * @param IRQn External interrupt number.
323 * This parameter can be an enumerator of IRQn_Type enumeration
324 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
325 * @retval None
326 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)327 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
328 {
329 /* Check the parameters */
330 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
331
332 /* Clear pending interrupt */
333 NVIC_ClearPendingIRQ(IRQn);
334 }
335
336 /**
337 * @brief Configure the SysTick clock source.
338 * @param CLKSource specifies the SysTick clock source.
339 * This parameter can be one of the following values:
340 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
341 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
342 * @retval None
343 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)344 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
345 {
346 /* Check the parameters */
347 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
348 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
349 {
350 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
351 }
352 else
353 {
354 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
355 }
356 }
357
358 /**
359 * @brief Handle SYSTICK interrupt request.
360 * @retval None
361 */
HAL_SYSTICK_IRQHandler(void)362 void HAL_SYSTICK_IRQHandler(void)
363 {
364 HAL_SYSTICK_Callback();
365 }
366
367 /**
368 * @brief SYSTICK callback.
369 * @retval None
370 */
HAL_SYSTICK_Callback(void)371 __weak void HAL_SYSTICK_Callback(void)
372 {
373 /* NOTE : This function should not be modified, when the callback is needed,
374 the HAL_SYSTICK_Callback could be implemented in the user file
375 */
376 }
377
378 #if (__MPU_PRESENT == 1U)
379 /**
380 * @brief Disables the MPU
381 * @retval None
382 */
HAL_MPU_Disable(void)383 void HAL_MPU_Disable(void)
384 {
385 /* Make sure outstanding transfers are done */
386 __DMB();
387
388 /* Disable fault exceptions */
389 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
390
391 /* Disable the MPU and clear the control register*/
392 MPU->CTRL = 0U;
393 }
394
395 /**
396 * @brief Enable the MPU.
397 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
398 * NMI, FAULTMASK and privileged access to the default memory
399 * This parameter can be one of the following values:
400 * @arg MPU_HFNMI_PRIVDEF_NONE
401 * @arg MPU_HARDFAULT_NMI
402 * @arg MPU_PRIVILEGED_DEFAULT
403 * @arg MPU_HFNMI_PRIVDEF
404 * @retval None
405 */
HAL_MPU_Enable(uint32_t MPU_Control)406 void HAL_MPU_Enable(uint32_t MPU_Control)
407 {
408 /* Enable the MPU */
409 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
410
411 /* Enable fault exceptions */
412 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
413
414 /* Ensure MPU setting take effects */
415 __DSB();
416 __ISB();
417 }
418
419 /**
420 * @brief Initialize and configure the Region and the memory to be protected.
421 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
422 * the initialization and configuration information.
423 * @retval None
424 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)425 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
426 {
427 /* Check the parameters */
428 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
429 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
430
431 /* Set the Region number */
432 MPU->RNR = MPU_Init->Number;
433
434 if ((MPU_Init->Enable) != 0U)
435 {
436 /* Check the parameters */
437 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
438 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
439 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
440 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
441 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
442 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
443 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
444 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
445
446 MPU->RBAR = MPU_Init->BaseAddress;
447 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
448 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
449 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
450 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
451 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
452 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
453 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
454 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
455 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
456 }
457 else
458 {
459 MPU->RBAR = 0x00U;
460 MPU->RASR = 0x00U;
461 }
462 }
463 #endif /* __MPU_PRESENT */
464
465 /**
466 * @}
467 */
468
469 /**
470 * @}
471 */
472
473 #endif /* HAL_CORTEX_MODULE_ENABLED */
474 /**
475 * @}
476 */
477
478 /**
479 * @}
480 */
481
482 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
483