1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2018 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32_HAL_LEGACY 23 #define STM32_HAL_LEGACY 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 /* Exported types ------------------------------------------------------------*/ 31 /* Exported constants --------------------------------------------------------*/ 32 33 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 34 * @{ 35 */ 36 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 37 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 38 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 39 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 40 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 41 42 /** 43 * @} 44 */ 45 46 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 47 * @{ 48 */ 49 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 50 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 51 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 52 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 53 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 54 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 55 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 56 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 57 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 58 #define REGULAR_GROUP ADC_REGULAR_GROUP 59 #define INJECTED_GROUP ADC_INJECTED_GROUP 60 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 61 #define AWD_EVENT ADC_AWD_EVENT 62 #define AWD1_EVENT ADC_AWD1_EVENT 63 #define AWD2_EVENT ADC_AWD2_EVENT 64 #define AWD3_EVENT ADC_AWD3_EVENT 65 #define OVR_EVENT ADC_OVR_EVENT 66 #define JQOVF_EVENT ADC_JQOVF_EVENT 67 #define ALL_CHANNELS ADC_ALL_CHANNELS 68 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 69 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 70 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 71 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 72 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 73 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 74 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 75 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 76 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 77 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 78 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 79 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 80 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 81 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 82 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 83 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 84 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 85 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 86 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 87 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 88 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 89 90 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 91 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 92 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 93 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 94 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 95 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 96 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 97 98 #if defined(STM32H7) 99 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 100 #endif /* STM32H7 */ 101 /** 102 * @} 103 */ 104 105 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 106 * @{ 107 */ 108 109 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 110 111 /** 112 * @} 113 */ 114 115 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 116 * @{ 117 */ 118 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 119 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 120 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 121 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 122 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 123 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 124 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 125 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 126 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 127 #if defined(STM32L0) 128 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 129 #endif 130 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 131 #if defined(STM32F373xC) || defined(STM32F378xx) 132 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 133 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 134 #endif /* STM32F373xC || STM32F378xx */ 135 136 #if defined(STM32L0) || defined(STM32L4) 137 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 138 139 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 140 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 141 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 142 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 143 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 144 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 145 146 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 147 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 148 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 149 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 150 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 151 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 152 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 153 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 154 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 155 #if defined(STM32L0) 156 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 157 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 158 /* to the second dedicated IO (only for COMP2). */ 159 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 160 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 161 #else 162 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 163 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 164 #endif 165 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 166 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 167 168 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 169 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 170 171 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 172 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 173 #if defined(COMP_CSR_LOCK) 174 #define COMP_FLAG_LOCK COMP_CSR_LOCK 175 #elif defined(COMP_CSR_COMP1LOCK) 176 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 177 #elif defined(COMP_CSR_COMPxLOCK) 178 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 179 #endif 180 181 #if defined(STM32L4) 182 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 183 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 184 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 185 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 186 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 187 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 188 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 189 #endif 190 191 #if defined(STM32L0) 192 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 193 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 194 #else 195 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 196 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 197 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 198 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 199 #endif 200 201 #endif 202 /** 203 * @} 204 */ 205 206 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 207 * @{ 208 */ 209 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 210 /** 211 * @} 212 */ 213 214 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 215 * @{ 216 */ 217 218 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 219 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 220 221 /** 222 * @} 223 */ 224 225 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 226 * @{ 227 */ 228 229 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 230 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 231 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 232 #define DAC_WAVE_NONE 0x00000000U 233 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 234 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 235 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 236 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 237 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 238 239 /** 240 * @} 241 */ 242 243 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 244 * @{ 245 */ 246 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 247 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 248 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 249 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 250 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 251 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 252 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 253 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 254 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 255 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 256 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 257 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 258 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 259 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 260 261 #define IS_HAL_REMAPDMA IS_DMA_REMAP 262 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 263 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 264 265 #if defined(STM32L4) 266 267 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 268 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 269 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 270 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 271 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 272 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 273 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 274 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 275 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 276 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 277 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 278 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 279 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 280 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 281 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 282 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 283 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 284 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 285 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 286 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 287 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 288 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 289 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 290 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 291 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 292 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 293 294 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 295 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 296 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 297 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 298 299 #endif /* STM32L4 */ 300 301 #if defined(STM32H7) 302 303 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 304 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 305 306 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 307 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 308 309 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 310 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 311 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 312 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 313 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 314 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 315 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 316 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 317 318 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 319 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 320 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 321 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 322 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 323 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 324 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 325 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 326 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 327 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 328 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 329 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 330 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 331 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 332 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 333 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 334 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 335 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 336 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 337 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 338 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 339 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 340 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 341 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 342 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 343 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 344 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 345 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 346 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 347 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 348 349 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 350 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 351 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 352 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 353 354 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 355 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 356 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 357 358 #endif /* STM32H7 */ 359 360 /** 361 * @} 362 */ 363 364 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 365 * @{ 366 */ 367 368 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 369 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 370 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 371 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 372 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 373 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 374 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 375 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 376 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 377 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 378 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 379 #define OBEX_PCROP OPTIONBYTE_PCROP 380 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 381 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 382 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 383 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 384 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 385 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 386 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 387 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 388 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 389 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 390 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 391 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 392 #define PAGESIZE FLASH_PAGE_SIZE 393 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 394 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 395 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 396 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 397 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 398 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 399 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 400 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 401 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 402 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 403 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 404 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 405 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 406 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 407 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 408 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 409 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 410 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 411 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 412 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 413 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 414 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 415 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 416 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 417 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 418 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 419 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 420 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 421 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 422 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 423 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 424 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 425 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 426 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 427 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 428 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 429 #define OB_WDG_SW OB_IWDG_SW 430 #define OB_WDG_HW OB_IWDG_HW 431 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 432 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 433 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 434 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 435 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 436 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 437 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 438 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 439 #if defined(STM32G0) 440 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 441 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 442 #else 443 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 444 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 445 #endif 446 #if defined(STM32H7) 447 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 448 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 449 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 450 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 451 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 452 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 453 #endif 454 455 /** 456 * @} 457 */ 458 459 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 460 * @{ 461 */ 462 463 #if defined(STM32H7) 464 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 465 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 466 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 467 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 468 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 469 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 470 #endif /* STM32H7 */ 471 472 /** 473 * @} 474 */ 475 476 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 477 * @{ 478 */ 479 480 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 481 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 482 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 483 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 484 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 485 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 486 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 487 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 488 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 489 /** 490 * @} 491 */ 492 493 494 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 495 * @{ 496 */ 497 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) 498 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 499 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 500 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 501 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 502 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 503 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 504 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 505 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 506 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 507 #endif 508 /** 509 * @} 510 */ 511 512 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 513 * @{ 514 */ 515 516 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 517 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 518 /** 519 * @} 520 */ 521 522 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 523 * @{ 524 */ 525 #define GET_GPIO_SOURCE GPIO_GET_INDEX 526 #define GET_GPIO_INDEX GPIO_GET_INDEX 527 528 #if defined(STM32F4) 529 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 530 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 531 #endif 532 533 #if defined(STM32F7) 534 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 535 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 536 #endif 537 538 #if defined(STM32L4) 539 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 540 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 541 #endif 542 543 #if defined(STM32H7) 544 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 545 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 546 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 547 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 548 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 549 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 550 #endif 551 552 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 553 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 554 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 555 556 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) 557 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 558 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 559 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 560 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 561 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ 562 563 #if defined(STM32L1) 564 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 565 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 566 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 567 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 568 #endif /* STM32L1 */ 569 570 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 571 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 572 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 573 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 574 #endif /* STM32F0 || STM32F3 || STM32F1 */ 575 576 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 577 /** 578 * @} 579 */ 580 581 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 582 * @{ 583 */ 584 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 585 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 586 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 587 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 588 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 589 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 590 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 591 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 592 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 593 594 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 595 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 596 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 597 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 598 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 599 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 600 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 601 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 602 /** 603 * @} 604 */ 605 606 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 607 * @{ 608 */ 609 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 610 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 611 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 612 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 613 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 614 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 615 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 616 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 617 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 618 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 619 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 620 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 621 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 622 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 623 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 624 #endif 625 /** 626 * @} 627 */ 628 629 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 630 * @{ 631 */ 632 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 633 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 634 635 /** 636 * @} 637 */ 638 639 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 640 * @{ 641 */ 642 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 643 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 644 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 645 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 646 /** 647 * @} 648 */ 649 650 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 651 * @{ 652 */ 653 654 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 655 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 656 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 657 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 658 659 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 660 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 661 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 662 663 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 664 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 665 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 666 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 667 668 /* The following 3 definition have also been present in a temporary version of lptim.h */ 669 /* They need to be renamed also to the right name, just in case */ 670 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 671 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 672 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 673 674 /** 675 * @} 676 */ 677 678 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 679 * @{ 680 */ 681 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 682 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 683 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 684 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 685 686 #define NAND_AddressTypedef NAND_AddressTypeDef 687 688 #define __ARRAY_ADDRESS ARRAY_ADDRESS 689 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 690 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 691 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 692 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 693 /** 694 * @} 695 */ 696 697 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 698 * @{ 699 */ 700 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 701 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 702 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 703 #define NOR_ERROR HAL_NOR_STATUS_ERROR 704 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 705 706 #define __NOR_WRITE NOR_WRITE 707 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 708 /** 709 * @} 710 */ 711 712 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 713 * @{ 714 */ 715 716 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 717 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 718 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 719 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 720 721 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 722 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 723 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 724 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 725 726 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 727 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 728 729 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 730 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 731 732 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 733 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 734 735 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 736 737 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 738 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 739 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 740 741 /** 742 * @} 743 */ 744 745 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 746 * @{ 747 */ 748 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 749 750 #if defined(STM32H7) 751 #define I2S_IT_TXE I2S_IT_TXP 752 #define I2S_IT_RXNE I2S_IT_RXP 753 754 #define I2S_FLAG_TXE I2S_FLAG_TXP 755 #define I2S_FLAG_RXNE I2S_FLAG_RXP 756 #define I2S_FLAG_FRE I2S_FLAG_TIFRE 757 #endif 758 759 #if defined(STM32F7) 760 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 761 #endif 762 /** 763 * @} 764 */ 765 766 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 767 * @{ 768 */ 769 770 /* Compact Flash-ATA registers description */ 771 #define CF_DATA ATA_DATA 772 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 773 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 774 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 775 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 776 #define CF_CARD_HEAD ATA_CARD_HEAD 777 #define CF_STATUS_CMD ATA_STATUS_CMD 778 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 779 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 780 781 /* Compact Flash-ATA commands */ 782 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 783 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 784 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 785 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 786 787 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 788 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 789 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 790 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 791 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 792 /** 793 * @} 794 */ 795 796 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 797 * @{ 798 */ 799 800 #define FORMAT_BIN RTC_FORMAT_BIN 801 #define FORMAT_BCD RTC_FORMAT_BCD 802 803 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 804 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 805 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 806 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 807 808 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 809 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 810 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 811 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 812 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 813 814 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 815 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 816 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 817 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 818 819 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 820 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 821 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 822 823 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 824 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 825 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 826 827 /** 828 * @} 829 */ 830 831 832 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 833 * @{ 834 */ 835 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 836 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 837 838 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 839 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 840 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 841 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 842 843 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 844 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 845 846 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 847 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 848 /** 849 * @} 850 */ 851 852 853 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 854 * @{ 855 */ 856 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 857 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 858 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 859 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 860 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 861 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 862 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 863 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 864 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 865 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 866 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 867 /** 868 * @} 869 */ 870 871 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 872 * @{ 873 */ 874 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 875 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 876 877 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 878 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 879 880 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 881 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 882 883 #if defined(STM32H7) 884 885 #define SPI_FLAG_TXE SPI_FLAG_TXP 886 #define SPI_FLAG_RXNE SPI_FLAG_RXP 887 888 #define SPI_IT_TXE SPI_IT_TXP 889 #define SPI_IT_RXNE SPI_IT_RXP 890 891 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 892 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 893 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 894 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 895 896 #endif /* STM32H7 */ 897 898 /** 899 * @} 900 */ 901 902 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 903 * @{ 904 */ 905 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 906 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 907 908 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 909 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 910 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 911 #define TIM_DMABase_DIER TIM_DMABASE_DIER 912 #define TIM_DMABase_SR TIM_DMABASE_SR 913 #define TIM_DMABase_EGR TIM_DMABASE_EGR 914 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 915 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 916 #define TIM_DMABase_CCER TIM_DMABASE_CCER 917 #define TIM_DMABase_CNT TIM_DMABASE_CNT 918 #define TIM_DMABase_PSC TIM_DMABASE_PSC 919 #define TIM_DMABase_ARR TIM_DMABASE_ARR 920 #define TIM_DMABase_RCR TIM_DMABASE_RCR 921 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 922 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 923 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 924 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 925 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 926 #define TIM_DMABase_DCR TIM_DMABASE_DCR 927 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 928 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 929 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 930 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 931 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 932 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 933 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 934 #define TIM_DMABase_OR TIM_DMABASE_OR 935 936 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 937 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 938 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 939 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 940 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 941 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 942 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 943 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 944 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 945 946 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 947 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 948 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 949 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 950 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 951 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 952 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 953 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 954 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 955 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 956 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 957 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 958 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 959 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 960 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 961 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 962 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 963 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 964 965 #if defined(STM32L0) 966 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 967 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 968 #endif 969 970 #if defined(STM32F3) 971 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 972 #endif 973 /** 974 * @} 975 */ 976 977 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 978 * @{ 979 */ 980 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 981 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 982 /** 983 * @} 984 */ 985 986 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 987 * @{ 988 */ 989 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 990 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 991 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 992 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 993 994 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 995 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 996 997 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 998 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 999 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1000 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1001 1002 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1003 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1004 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1005 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1006 1007 #define __DIV_LPUART UART_DIV_LPUART 1008 1009 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1010 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1011 1012 /** 1013 * @} 1014 */ 1015 1016 1017 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1018 * @{ 1019 */ 1020 1021 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1022 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1023 1024 #define USARTNACK_ENABLED USART_NACK_ENABLE 1025 #define USARTNACK_DISABLED USART_NACK_DISABLE 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1031 * @{ 1032 */ 1033 #define CFR_BASE WWDG_CFR_BASE 1034 1035 /** 1036 * @} 1037 */ 1038 1039 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1040 * @{ 1041 */ 1042 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1043 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1044 #define CAN_IT_RQCP0 CAN_IT_TME 1045 #define CAN_IT_RQCP1 CAN_IT_TME 1046 #define CAN_IT_RQCP2 CAN_IT_TME 1047 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1048 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1049 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1050 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1051 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1052 1053 /** 1054 * @} 1055 */ 1056 1057 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1058 * @{ 1059 */ 1060 1061 #define VLAN_TAG ETH_VLAN_TAG 1062 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1063 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1064 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1065 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1066 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1067 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1068 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1069 1070 #define ETH_MMCCR 0x00000100U 1071 #define ETH_MMCRIR 0x00000104U 1072 #define ETH_MMCTIR 0x00000108U 1073 #define ETH_MMCRIMR 0x0000010CU 1074 #define ETH_MMCTIMR 0x00000110U 1075 #define ETH_MMCTGFSCCR 0x0000014CU 1076 #define ETH_MMCTGFMSCCR 0x00000150U 1077 #define ETH_MMCTGFCR 0x00000168U 1078 #define ETH_MMCRFCECR 0x00000194U 1079 #define ETH_MMCRFAECR 0x00000198U 1080 #define ETH_MMCRGUFCR 0x000001C4U 1081 1082 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1083 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1084 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1085 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1086 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1087 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1088 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1089 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1090 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1091 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1092 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1093 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1094 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1095 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1096 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1097 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1098 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1099 #if defined(STM32F1) 1100 #else 1101 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1102 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1103 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1104 #endif 1105 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1106 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1107 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1108 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1109 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1110 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1111 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1112 1113 /** 1114 * @} 1115 */ 1116 1117 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1118 * @{ 1119 */ 1120 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1121 #define DCMI_IT_OVF DCMI_IT_OVR 1122 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1123 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1124 1125 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1126 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1127 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1128 1129 /** 1130 * @} 1131 */ 1132 1133 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1134 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1135 || defined(STM32H7) 1136 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1137 * @{ 1138 */ 1139 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1140 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1141 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1142 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1143 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1144 1145 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1146 #define CM_RGB888 DMA2D_INPUT_RGB888 1147 #define CM_RGB565 DMA2D_INPUT_RGB565 1148 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1149 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1150 #define CM_L8 DMA2D_INPUT_L8 1151 #define CM_AL44 DMA2D_INPUT_AL44 1152 #define CM_AL88 DMA2D_INPUT_AL88 1153 #define CM_L4 DMA2D_INPUT_L4 1154 #define CM_A8 DMA2D_INPUT_A8 1155 #define CM_A4 DMA2D_INPUT_A4 1156 /** 1157 * @} 1158 */ 1159 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1160 1161 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1162 * @{ 1163 */ 1164 1165 /** 1166 * @} 1167 */ 1168 1169 /* Exported functions --------------------------------------------------------*/ 1170 1171 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1172 * @{ 1173 */ 1174 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1175 /** 1176 * @} 1177 */ 1178 1179 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1180 * @{ 1181 */ 1182 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1183 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1184 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1185 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1186 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1187 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1188 1189 /*HASH Algorithm Selection*/ 1190 1191 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1192 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1193 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1194 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1195 1196 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1197 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1198 1199 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1200 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1201 /** 1202 * @} 1203 */ 1204 1205 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1206 * @{ 1207 */ 1208 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1209 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1210 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1211 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1212 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1213 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1214 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1215 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1216 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1217 #if defined(STM32L0) 1218 #else 1219 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1220 #endif 1221 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1222 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1228 * @{ 1229 */ 1230 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1231 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1232 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1233 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1234 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1235 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1236 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1237 1238 /** 1239 * @} 1240 */ 1241 1242 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1243 * @{ 1244 */ 1245 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1246 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1247 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1248 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1249 1250 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1251 1252 #if defined(STM32H7) || defined(STM32G0) || defined(STM32L0) 1253 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1254 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1255 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1256 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1257 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1258 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1259 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1260 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1261 #endif /* STM32H7 || STM32G0 || STM32L0 */ 1262 /** 1263 * @} 1264 */ 1265 1266 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1267 * @{ 1268 */ 1269 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1270 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1271 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1272 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1273 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1274 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1275 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1276 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1277 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1278 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1279 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1280 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1281 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1282 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1283 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1284 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1285 1286 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1287 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1288 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1289 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1290 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1291 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1292 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1293 1294 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1295 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1296 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1297 #define CR_PMODE_BB CR_VOS_BB 1298 1299 #define DBP_BitNumber DBP_BIT_NUMBER 1300 #define PVDE_BitNumber PVDE_BIT_NUMBER 1301 #define PMODE_BitNumber PMODE_BIT_NUMBER 1302 #define EWUP_BitNumber EWUP_BIT_NUMBER 1303 #define FPDS_BitNumber FPDS_BIT_NUMBER 1304 #define ODEN_BitNumber ODEN_BIT_NUMBER 1305 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1306 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1307 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1308 #define BRE_BitNumber BRE_BIT_NUMBER 1309 1310 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1311 1312 /** 1313 * @} 1314 */ 1315 1316 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1317 * @{ 1318 */ 1319 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1320 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1321 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1322 /** 1323 * @} 1324 */ 1325 1326 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1327 * @{ 1328 */ 1329 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1330 /** 1331 * @} 1332 */ 1333 1334 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1335 * @{ 1336 */ 1337 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1338 #define HAL_TIM_DMAError TIM_DMAError 1339 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1340 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1341 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) 1342 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1343 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1344 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1345 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1346 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1347 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1348 #endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ 1349 /** 1350 * @} 1351 */ 1352 1353 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1354 * @{ 1355 */ 1356 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1357 /** 1358 * @} 1359 */ 1360 1361 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1362 * @{ 1363 */ 1364 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1365 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1366 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1367 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1368 /** 1369 * @} 1370 */ 1371 1372 1373 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1374 * @{ 1375 */ 1376 1377 /** 1378 * @} 1379 */ 1380 1381 /* Exported macros ------------------------------------------------------------*/ 1382 1383 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1384 * @{ 1385 */ 1386 #define AES_IT_CC CRYP_IT_CC 1387 #define AES_IT_ERR CRYP_IT_ERR 1388 #define AES_FLAG_CCF CRYP_FLAG_CCF 1389 /** 1390 * @} 1391 */ 1392 1393 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1394 * @{ 1395 */ 1396 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1397 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1398 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1399 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1400 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1401 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1402 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1403 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1404 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1405 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1406 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1407 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1408 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1409 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1410 1411 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1412 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1413 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1414 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1415 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1416 1417 /** 1418 * @} 1419 */ 1420 1421 1422 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1423 * @{ 1424 */ 1425 #define __ADC_ENABLE __HAL_ADC_ENABLE 1426 #define __ADC_DISABLE __HAL_ADC_DISABLE 1427 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1428 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1429 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1430 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1431 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1432 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1433 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1434 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1435 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1436 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1437 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1438 1439 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1440 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1441 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1442 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1443 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1444 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1445 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1446 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1447 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1448 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1449 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1450 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1451 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1452 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1453 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1454 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1455 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1456 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1457 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1458 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1459 1460 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1461 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1462 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1463 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1464 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1465 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1466 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1467 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1468 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1469 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1470 1471 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1472 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1473 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1474 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1475 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1476 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1477 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1478 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1479 1480 #define __HAL_ADC_SQR1 ADC_SQR1 1481 #define __HAL_ADC_SMPR1 ADC_SMPR1 1482 #define __HAL_ADC_SMPR2 ADC_SMPR2 1483 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1484 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1485 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1486 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1487 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1488 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1489 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1490 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1491 #define __HAL_ADC_JSQR ADC_JSQR 1492 1493 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1494 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1495 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1496 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1497 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1498 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1499 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1500 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1501 1502 /** 1503 * @} 1504 */ 1505 1506 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1507 * @{ 1508 */ 1509 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1510 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1511 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1512 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1513 1514 /** 1515 * @} 1516 */ 1517 1518 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1519 * @{ 1520 */ 1521 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1522 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1523 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1524 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1525 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1526 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1527 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1528 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1529 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1530 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1531 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1532 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1533 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1534 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1535 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1536 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1537 1538 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1539 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1540 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1541 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1542 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1543 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1544 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1545 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1546 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1547 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1548 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1549 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1550 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1551 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1552 1553 1554 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1555 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1556 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1557 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1558 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1559 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1560 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1561 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1562 #if defined(STM32H7) 1563 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 1564 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 1565 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 1566 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 1567 #else 1568 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1569 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1570 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1571 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1572 #endif /* STM32H7 */ 1573 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1574 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1575 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1576 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1577 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1578 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1579 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1580 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1581 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1582 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1583 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1584 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1585 1586 /** 1587 * @} 1588 */ 1589 1590 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 1591 * @{ 1592 */ 1593 #if defined(STM32F3) 1594 #define COMP_START __HAL_COMP_ENABLE 1595 #define COMP_STOP __HAL_COMP_DISABLE 1596 #define COMP_LOCK __HAL_COMP_LOCK 1597 1598 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1599 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1600 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1601 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1602 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1603 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1604 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1605 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1606 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1607 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1608 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1609 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1610 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1611 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1612 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1613 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1614 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1615 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1616 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1617 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1618 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1619 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1620 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1621 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1622 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1623 # endif 1624 # if defined(STM32F302xE) || defined(STM32F302xC) 1625 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1626 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1627 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1628 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1629 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1630 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1631 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1632 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1633 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1634 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1635 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1636 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1637 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1638 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1639 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1640 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1641 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1642 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1643 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1644 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1645 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1646 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1647 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1648 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1649 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1650 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1651 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1652 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1653 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1654 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1655 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1656 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1657 # endif 1658 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 1659 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1660 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1661 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 1662 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1663 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 1664 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 1665 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 1666 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1667 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1668 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 1669 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1670 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 1671 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 1672 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 1673 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1674 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1675 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 1676 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1677 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 1678 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 1679 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 1680 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1681 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1682 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 1683 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1684 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 1685 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 1686 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 1687 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1688 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1689 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 1690 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1691 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 1692 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 1693 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 1694 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1695 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1696 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 1697 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1698 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 1699 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 1700 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 1701 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1702 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1703 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 1704 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1705 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 1706 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 1707 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 1708 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1709 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1710 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 1711 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1712 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 1713 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 1714 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 1715 # endif 1716 # if defined(STM32F373xC) ||defined(STM32F378xx) 1717 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1718 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 1719 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1720 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 1721 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1722 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 1723 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1724 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 1725 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1726 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 1727 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1728 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 1729 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1730 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 1731 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1732 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 1733 # endif 1734 #else 1735 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1736 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 1737 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1738 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 1739 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1740 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 1741 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1742 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 1743 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1744 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 1745 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1746 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 1747 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1748 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 1749 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1750 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 1751 #endif 1752 1753 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 1754 1755 #if defined(STM32L0) || defined(STM32L4) 1756 /* Note: On these STM32 families, the only argument of this macro */ 1757 /* is COMP_FLAG_LOCK. */ 1758 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 1759 /* argument. */ 1760 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 1761 #endif 1762 /** 1763 * @} 1764 */ 1765 1766 #if defined(STM32L0) || defined(STM32L4) 1767 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 1768 * @{ 1769 */ 1770 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 1771 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 1772 /** 1773 * @} 1774 */ 1775 #endif 1776 1777 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1778 * @{ 1779 */ 1780 1781 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 1782 ((WAVE) == DAC_WAVE_NOISE)|| \ 1783 ((WAVE) == DAC_WAVE_TRIANGLE)) 1784 1785 /** 1786 * @} 1787 */ 1788 1789 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 1790 * @{ 1791 */ 1792 1793 #define IS_WRPAREA IS_OB_WRPAREA 1794 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 1795 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 1796 #define IS_TYPEERASE IS_FLASH_TYPEERASE 1797 #define IS_NBSECTORS IS_FLASH_NBSECTORS 1798 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 1799 1800 /** 1801 * @} 1802 */ 1803 1804 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 1805 * @{ 1806 */ 1807 1808 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 1809 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 1810 #if defined(STM32F1) 1811 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 1812 #else 1813 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 1814 #endif /* STM32F1 */ 1815 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 1816 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 1817 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 1818 #define __HAL_I2C_SPEED I2C_SPEED 1819 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 1820 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 1821 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 1822 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 1823 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 1824 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 1825 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 1826 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 1827 /** 1828 * @} 1829 */ 1830 1831 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 1832 * @{ 1833 */ 1834 1835 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 1836 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 1837 1838 #if defined(STM32H7) 1839 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 1840 #endif 1841 1842 /** 1843 * @} 1844 */ 1845 1846 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 1847 * @{ 1848 */ 1849 1850 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 1851 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 1852 1853 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 1854 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 1855 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 1856 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 1857 1858 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 1859 1860 1861 /** 1862 * @} 1863 */ 1864 1865 1866 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 1867 * @{ 1868 */ 1869 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 1870 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 1871 /** 1872 * @} 1873 */ 1874 1875 1876 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 1877 * @{ 1878 */ 1879 1880 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 1881 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 1882 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 1883 1884 /** 1885 * @} 1886 */ 1887 1888 1889 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 1890 * @{ 1891 */ 1892 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 1893 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 1894 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 1895 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 1896 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 1897 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 1898 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 1899 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 1900 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 1901 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 1902 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 1903 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 1904 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 1905 1906 /** 1907 * @} 1908 */ 1909 1910 1911 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 1912 * @{ 1913 */ 1914 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 1915 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 1916 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 1917 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1918 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 1919 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1920 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 1921 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 1922 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 1923 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 1924 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 1925 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 1926 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 1927 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 1928 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 1929 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 1930 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 1931 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 1932 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 1933 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 1934 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1935 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 1936 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1937 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1938 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1939 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 1940 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 1941 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 1942 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 1943 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 1944 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 1945 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 1946 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 1947 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 1948 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 1949 1950 #if defined (STM32F4) 1951 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 1952 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 1953 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 1954 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 1955 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 1956 #else 1957 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 1958 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 1959 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 1960 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 1961 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 1962 #endif /* STM32F4 */ 1963 /** 1964 * @} 1965 */ 1966 1967 1968 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 1969 * @{ 1970 */ 1971 1972 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 1973 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 1974 1975 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 1976 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 1977 1978 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 1979 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 1980 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 1981 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 1982 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 1983 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 1984 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 1985 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 1986 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 1987 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 1988 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 1989 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 1990 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 1991 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 1992 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 1993 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 1994 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 1995 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 1996 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 1997 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 1998 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 1999 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2000 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2001 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2002 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2003 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2004 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2005 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2006 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2007 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2008 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2009 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2010 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2011 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2012 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2013 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2014 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2015 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2016 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2017 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2018 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2019 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2020 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2021 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2022 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2023 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2024 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2025 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2026 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2027 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2028 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2029 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2030 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2031 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2032 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2033 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2034 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2035 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2036 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2037 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2038 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2039 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2040 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2041 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2042 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2043 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2044 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2045 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2046 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2047 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2048 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2049 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2050 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2051 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2052 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2053 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2054 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2055 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2056 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2057 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2058 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2059 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2060 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2061 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2062 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2063 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2064 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2065 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2066 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2067 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2068 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2069 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2070 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2071 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2072 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2073 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2074 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2075 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2076 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2077 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2078 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2079 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2080 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2081 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2082 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2083 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2084 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2085 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2086 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2087 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2088 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2089 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2090 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2091 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2092 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2093 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2094 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2095 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2096 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2097 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2098 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2099 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2100 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2101 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2102 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2103 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2104 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2105 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2106 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2107 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2108 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2109 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2110 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2111 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2112 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2113 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2114 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2115 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2116 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2117 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2118 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2119 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2120 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2121 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2122 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2123 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2124 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2125 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2126 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2127 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2128 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2129 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2130 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2131 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2132 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2133 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2134 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2135 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2136 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2137 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2138 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2139 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2140 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2141 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2142 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2143 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2144 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2145 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2146 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2147 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2148 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2149 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2150 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2151 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2152 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2153 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2154 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2155 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2156 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2157 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2158 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2159 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2160 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2161 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2162 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2163 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2164 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2165 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2166 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2167 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2168 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2169 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2170 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2171 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2172 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2173 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2174 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2175 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2176 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2177 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2178 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2179 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2180 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2181 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2182 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2183 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2184 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2185 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2186 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2187 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2188 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2189 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2190 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2191 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2192 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2193 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2194 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2195 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2196 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2197 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2198 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2199 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2200 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2201 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2202 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2203 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2204 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2205 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2206 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2207 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2208 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2209 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2210 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2211 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2212 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2213 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2214 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2215 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2216 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2217 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2218 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2219 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2220 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2221 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2222 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2223 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2224 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2225 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2226 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2227 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2228 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2229 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2230 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2231 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2232 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2233 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2234 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2235 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2236 2237 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2238 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2239 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2240 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2241 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2242 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2243 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2244 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2245 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2246 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2247 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2248 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2249 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2250 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2251 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2252 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2253 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2254 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2255 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2256 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2257 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2258 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2259 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2260 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2261 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2262 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2263 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2264 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2265 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2266 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2267 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2268 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2269 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2270 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2271 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2272 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2273 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2274 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2275 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2276 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2277 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2278 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2279 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2280 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2281 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2282 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2283 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2284 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2285 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2286 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2287 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2288 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2289 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2290 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2291 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2292 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2293 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2294 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2295 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2296 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2297 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2298 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2299 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2300 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2301 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2302 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2303 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2304 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2305 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2306 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2307 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2308 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2309 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2310 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2311 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2312 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2313 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2314 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2315 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2316 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2317 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2318 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2319 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2320 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2321 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2322 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2323 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2324 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2325 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2326 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2327 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2328 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2329 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2330 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2331 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2332 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2333 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2334 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2335 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2336 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2337 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2338 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2339 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2340 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2341 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2342 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2343 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2344 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2345 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2346 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2347 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2348 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2349 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2350 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2351 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2352 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2353 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2354 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2355 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2356 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2357 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2358 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2359 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2360 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2361 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2362 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2363 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2364 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2365 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2366 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2367 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2368 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2369 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2370 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2371 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2372 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2373 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2374 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2375 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2376 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2377 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2378 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2379 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2380 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2381 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2382 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2383 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2384 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2385 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2386 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2387 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2388 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2389 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2390 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2391 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2392 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2393 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2394 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2395 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2396 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2397 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2398 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2399 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2400 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2401 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2402 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2403 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2404 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2405 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2406 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2407 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2408 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2409 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2410 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2411 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2412 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2413 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2414 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2415 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2416 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2417 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2418 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2419 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2420 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2421 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2422 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2423 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2424 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2425 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2426 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2427 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2428 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2429 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2430 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2431 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2432 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2433 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2434 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2435 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2436 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2437 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2438 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2439 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2440 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2441 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2442 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2443 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2444 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2445 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2446 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2447 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2448 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2449 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2450 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2451 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2452 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2453 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2454 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2455 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2456 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2457 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2458 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2459 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2460 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2461 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2462 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2463 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2464 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2465 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2466 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2467 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2468 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2469 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2470 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2471 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2472 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2473 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2474 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2475 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2476 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2477 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2478 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2479 2480 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2481 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2482 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2483 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2484 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2485 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2486 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2487 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2488 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2489 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2490 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2491 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2492 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2493 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2494 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2495 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2496 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2497 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2498 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2499 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2500 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2501 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2502 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2503 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2504 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2505 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2506 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2507 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2508 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2509 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2510 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2511 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2512 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2513 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2514 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2515 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2516 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2517 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2518 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2519 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2520 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2521 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2522 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2523 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2524 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2525 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2526 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2527 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2528 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2529 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2530 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2531 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2532 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2533 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2534 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2535 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2536 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2537 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2538 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2539 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2540 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2541 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2542 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2543 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2544 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2545 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2546 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2547 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2548 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2549 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2550 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2551 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2552 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2553 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2554 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2555 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2556 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2557 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 2558 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 2559 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 2560 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 2561 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 2562 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 2563 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 2564 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 2565 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 2566 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 2567 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 2568 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 2569 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 2570 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 2571 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 2572 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 2573 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 2574 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 2575 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 2576 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2577 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2578 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2579 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2580 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 2581 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 2582 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2583 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2584 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2585 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2586 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 2587 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 2588 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2589 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2590 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2591 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2592 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2593 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2594 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2595 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2596 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 2597 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 2598 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2599 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2600 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2601 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2602 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 2603 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 2604 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 2605 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 2606 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 2607 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 2608 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 2609 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 2610 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 2611 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 2612 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 2613 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 2614 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 2615 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 2616 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 2617 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2618 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2619 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2620 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2621 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 2622 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 2623 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 2624 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 2625 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 2626 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 2627 2628 /* alias define maintained for legacy */ 2629 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2630 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2631 2632 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 2633 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 2634 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 2635 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 2636 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 2637 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 2638 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 2639 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 2640 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 2641 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 2642 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 2643 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 2644 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 2645 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 2646 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 2647 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 2648 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 2649 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 2650 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 2651 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 2652 2653 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 2654 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 2655 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 2656 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 2657 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 2658 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 2659 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 2660 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 2661 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 2662 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 2663 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 2664 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 2665 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 2666 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 2667 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 2668 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 2669 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 2670 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 2671 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 2672 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 2673 2674 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 2675 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 2676 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 2677 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 2678 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 2679 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 2680 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 2681 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 2682 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 2683 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 2684 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 2685 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 2686 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 2687 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 2688 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 2689 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 2690 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 2691 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 2692 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 2693 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 2694 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 2695 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 2696 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 2697 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 2698 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 2699 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 2700 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 2701 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 2702 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 2703 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 2704 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 2705 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 2706 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 2707 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 2708 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 2709 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 2710 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 2711 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 2712 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 2713 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 2714 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 2715 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 2716 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 2717 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 2718 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 2719 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 2720 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 2721 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 2722 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 2723 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 2724 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 2725 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 2726 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 2727 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 2728 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 2729 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 2730 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 2731 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 2732 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 2733 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 2734 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 2735 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 2736 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 2737 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 2738 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 2739 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 2740 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 2741 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 2742 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 2743 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 2744 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 2745 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 2746 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 2747 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 2748 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 2749 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 2750 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 2751 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 2752 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 2753 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 2754 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 2755 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 2756 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 2757 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 2758 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 2759 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 2760 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 2761 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 2762 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 2763 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 2764 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 2765 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 2766 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 2767 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 2768 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 2769 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 2770 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 2771 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 2772 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 2773 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 2774 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 2775 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 2776 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 2777 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 2778 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 2779 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 2780 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 2781 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 2782 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 2783 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 2784 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 2785 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 2786 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 2787 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 2788 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 2789 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 2790 2791 #if defined(STM32F4) 2792 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2793 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2794 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2795 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2796 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2797 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2798 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 2799 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 2800 #define Sdmmc1ClockSelection SdioClockSelection 2801 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 2802 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 2803 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 2804 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 2805 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 2806 #endif 2807 2808 #if defined(STM32F7) || defined(STM32L4) 2809 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 2810 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 2811 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 2812 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 2813 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 2814 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 2815 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 2816 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 2817 #define SdioClockSelection Sdmmc1ClockSelection 2818 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 2819 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 2820 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 2821 #endif 2822 2823 #if defined(STM32F7) 2824 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 2825 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 2826 #endif 2827 2828 #if defined(STM32H7) 2829 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 2830 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 2831 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 2832 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 2833 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 2834 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 2835 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 2836 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 2837 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 2838 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 2839 2840 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 2841 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 2842 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 2843 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 2844 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 2845 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 2846 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 2847 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 2848 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 2849 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 2850 #endif 2851 2852 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 2853 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 2854 2855 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 2856 2857 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 2858 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 2859 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 2860 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 2861 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 2862 2863 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 2864 2865 #define RCC_IT_CSSLSE RCC_IT_LSECSS 2866 #define RCC_IT_CSSHSE RCC_IT_CSS 2867 2868 #define RCC_PLLMUL_3 RCC_PLL_MUL3 2869 #define RCC_PLLMUL_4 RCC_PLL_MUL4 2870 #define RCC_PLLMUL_6 RCC_PLL_MUL6 2871 #define RCC_PLLMUL_8 RCC_PLL_MUL8 2872 #define RCC_PLLMUL_12 RCC_PLL_MUL12 2873 #define RCC_PLLMUL_16 RCC_PLL_MUL16 2874 #define RCC_PLLMUL_24 RCC_PLL_MUL24 2875 #define RCC_PLLMUL_32 RCC_PLL_MUL32 2876 #define RCC_PLLMUL_48 RCC_PLL_MUL48 2877 2878 #define RCC_PLLDIV_2 RCC_PLL_DIV2 2879 #define RCC_PLLDIV_3 RCC_PLL_DIV3 2880 #define RCC_PLLDIV_4 RCC_PLL_DIV4 2881 2882 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 2883 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 2884 #define RCC_MCO_NODIV RCC_MCODIV_1 2885 #define RCC_MCO_DIV1 RCC_MCODIV_1 2886 #define RCC_MCO_DIV2 RCC_MCODIV_2 2887 #define RCC_MCO_DIV4 RCC_MCODIV_4 2888 #define RCC_MCO_DIV8 RCC_MCODIV_8 2889 #define RCC_MCO_DIV16 RCC_MCODIV_16 2890 #define RCC_MCO_DIV32 RCC_MCODIV_32 2891 #define RCC_MCO_DIV64 RCC_MCODIV_64 2892 #define RCC_MCO_DIV128 RCC_MCODIV_128 2893 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 2894 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 2895 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 2896 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 2897 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 2898 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 2899 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 2900 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 2901 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 2902 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 2903 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 2904 2905 #if defined(STM32L4) 2906 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 2907 #elif defined(STM32G0) 2908 #else 2909 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 2910 #endif 2911 2912 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 2913 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 2914 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 2915 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 2916 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 2917 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 2918 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 2919 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 2920 2921 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 2922 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 2923 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 2924 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 2925 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 2926 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 2927 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 2928 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 2929 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 2930 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 2931 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 2932 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 2933 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 2934 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 2935 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 2936 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 2937 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 2938 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 2939 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 2940 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 2941 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 2942 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 2943 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 2944 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 2945 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 2946 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 2947 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 2948 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 2949 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 2950 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 2951 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 2952 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 2953 2954 #define CR_HSION_BB RCC_CR_HSION_BB 2955 #define CR_CSSON_BB RCC_CR_CSSON_BB 2956 #define CR_PLLON_BB RCC_CR_PLLON_BB 2957 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 2958 #define CR_MSION_BB RCC_CR_MSION_BB 2959 #define CSR_LSION_BB RCC_CSR_LSION_BB 2960 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 2961 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 2962 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 2963 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 2964 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 2965 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 2966 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 2967 #define CR_HSEON_BB RCC_CR_HSEON_BB 2968 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 2969 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 2970 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 2971 2972 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 2973 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 2974 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 2975 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 2976 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 2977 2978 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 2979 2980 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 2981 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 2982 2983 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 2984 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 2985 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 2986 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 2987 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 2988 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 2989 2990 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 2991 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 2992 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 2993 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 2994 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 2995 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 2996 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 2997 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 2998 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 2999 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3000 #define DfsdmClockSelection Dfsdm1ClockSelection 3001 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3002 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3003 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3004 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3005 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3006 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3007 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3008 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3009 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3010 3011 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3012 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3013 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3014 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3015 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3016 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3017 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3018 3019 /** 3020 * @} 3021 */ 3022 3023 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3024 * @{ 3025 */ 3026 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3027 3028 /** 3029 * @} 3030 */ 3031 3032 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3033 * @{ 3034 */ 3035 #if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 3036 #else 3037 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3038 #endif 3039 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3040 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3041 3042 #if defined (STM32F1) 3043 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3044 3045 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3046 3047 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3048 3049 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3050 3051 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3052 #else 3053 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3054 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3055 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3056 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3057 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3058 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3059 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3060 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3061 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3062 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3063 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3064 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3065 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3066 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3067 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3068 #endif /* STM32F1 */ 3069 3070 #define IS_ALARM IS_RTC_ALARM 3071 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3072 #define IS_TAMPER IS_RTC_TAMPER 3073 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3074 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3075 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3076 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3077 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3078 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3079 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3080 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3081 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3082 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3083 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3084 3085 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3086 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3087 3088 /** 3089 * @} 3090 */ 3091 3092 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose 3093 * @{ 3094 */ 3095 3096 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3097 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3098 3099 #if defined(STM32F4) || defined(STM32F2) 3100 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3101 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3102 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3103 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3104 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3105 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3106 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3107 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3108 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3109 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3110 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3111 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3112 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3113 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3114 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3115 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3116 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3117 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3118 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3119 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3120 /* alias CMSIS */ 3121 #define SDMMC1_IRQn SDIO_IRQn 3122 #define SDMMC1_IRQHandler SDIO_IRQHandler 3123 #endif 3124 3125 #if defined(STM32F7) || defined(STM32L4) 3126 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3127 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3128 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3129 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3130 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3131 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3132 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3133 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3134 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3135 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3136 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3137 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3138 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3139 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3140 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3141 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3142 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3143 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3144 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3145 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3146 /* alias CMSIS for compatibilities */ 3147 #define SDIO_IRQn SDMMC1_IRQn 3148 #define SDIO_IRQHandler SDMMC1_IRQHandler 3149 #endif 3150 3151 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) 3152 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3153 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3154 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3155 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3156 #endif 3157 3158 #if defined(STM32H7) 3159 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3160 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3161 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3162 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3163 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3164 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3165 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3166 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3167 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3168 #endif 3169 /** 3170 * @} 3171 */ 3172 3173 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3174 * @{ 3175 */ 3176 3177 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3178 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3179 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3180 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3181 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3182 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3183 3184 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3185 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3186 3187 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3188 3189 /** 3190 * @} 3191 */ 3192 3193 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3194 * @{ 3195 */ 3196 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3197 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3198 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3199 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3200 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3201 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3202 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3203 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3204 /** 3205 * @} 3206 */ 3207 3208 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3209 * @{ 3210 */ 3211 3212 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3213 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3214 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3215 3216 /** 3217 * @} 3218 */ 3219 3220 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3221 * @{ 3222 */ 3223 3224 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3225 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3226 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3227 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3228 3229 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3230 3231 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3232 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3233 3234 /** 3235 * @} 3236 */ 3237 3238 3239 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3240 * @{ 3241 */ 3242 3243 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3244 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3245 #define __USART_ENABLE __HAL_USART_ENABLE 3246 #define __USART_DISABLE __HAL_USART_DISABLE 3247 3248 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3249 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3250 3251 /** 3252 * @} 3253 */ 3254 3255 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3256 * @{ 3257 */ 3258 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3259 3260 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3261 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3262 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3263 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3264 3265 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3266 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3267 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3268 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3269 3270 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3271 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3272 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3273 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3274 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3275 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3276 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3277 3278 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3279 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3280 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3281 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3282 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3283 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3284 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3285 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3286 3287 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3288 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3289 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3290 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3291 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3292 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3293 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3294 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3295 3296 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3297 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3298 3299 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3300 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3301 /** 3302 * @} 3303 */ 3304 3305 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3306 * @{ 3307 */ 3308 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3309 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3310 3311 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3312 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3313 3314 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3315 3316 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3317 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3318 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3319 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3320 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3321 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3322 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3323 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3324 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3325 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3326 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3327 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3328 3329 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3330 /** 3331 * @} 3332 */ 3333 3334 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3335 * @{ 3336 */ 3337 3338 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3339 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3340 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3341 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3342 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3343 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3344 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3345 3346 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3347 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3348 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3349 /** 3350 * @} 3351 */ 3352 3353 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3354 * @{ 3355 */ 3356 #define __HAL_LTDC_LAYER LTDC_LAYER 3357 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3358 /** 3359 * @} 3360 */ 3361 3362 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3363 * @{ 3364 */ 3365 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3366 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3367 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3368 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3369 #define SAI_STREOMODE SAI_STEREOMODE 3370 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3371 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3372 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3373 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3374 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3375 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3376 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3377 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3378 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3379 /** 3380 * @} 3381 */ 3382 3383 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3384 * @{ 3385 */ 3386 #if defined(STM32H7) 3387 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3388 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3389 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3390 #endif 3391 /** 3392 * @} 3393 */ 3394 3395 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3396 * @{ 3397 */ 3398 #if defined (STM32H7) || defined (STM32F3) 3399 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3400 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3401 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3402 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3403 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3404 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3405 #endif 3406 /** 3407 * @} 3408 */ 3409 3410 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3411 * @{ 3412 */ 3413 3414 /** 3415 * @} 3416 */ 3417 3418 #ifdef __cplusplus 3419 } 3420 #endif 3421 3422 #endif /* STM32_HAL_LEGACY */ 3423 3424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3425