1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: CPM Host Controller device tree for Xilinx Versal SoCs
8
9maintainers:
10  - Bharat Kumar Gogada <[email protected]>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14
15properties:
16  compatible:
17    enum:
18      - xlnx,versal-cpm-host-1.00
19      - xlnx,versal-cpm5-host
20      - xlnx,versal-cpm5-host1
21
22  reg:
23    items:
24      - description: CPM system level control and status registers.
25      - description: Configuration space region and bridge registers.
26      - description: CPM5 control and status registers.
27    minItems: 2
28
29  reg-names:
30    items:
31      - const: cpm_slcr
32      - const: cfg
33      - const: cpm_csr
34    minItems: 2
35
36  interrupts:
37    maxItems: 1
38
39  msi-map:
40    description:
41      Maps a Requester ID to an MSI controller and associated MSI sideband data.
42
43  ranges:
44    maxItems: 2
45
46  "#interrupt-cells":
47    const: 1
48
49  interrupt-controller:
50    description: Interrupt controller node for handling legacy PCI interrupts.
51    type: object
52    additionalProperties: false
53
54    properties:
55      "#address-cells":
56        const: 0
57
58      "#interrupt-cells":
59        const: 1
60
61      interrupt-controller: true
62
63required:
64  - reg
65  - reg-names
66  - "#interrupt-cells"
67  - interrupts
68  - interrupt-map
69  - interrupt-map-mask
70  - bus-range
71  - msi-map
72  - interrupt-controller
73
74unevaluatedProperties: false
75
76examples:
77  - |
78
79    versal {
80               #address-cells = <2>;
81               #size-cells = <2>;
82               cpm_pcie: pcie@fca10000 {
83                       compatible = "xlnx,versal-cpm-host-1.00";
84                       device_type = "pci";
85                       #address-cells = <3>;
86                       #interrupt-cells = <1>;
87                       #size-cells = <2>;
88                       interrupts = <0 72 4>;
89                       interrupt-parent = <&gic>;
90                       interrupt-map-mask = <0 0 0 7>;
91                       interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
92                                       <0 0 0 2 &pcie_intc_0 1>,
93                                       <0 0 0 3 &pcie_intc_0 2>,
94                                       <0 0 0 4 &pcie_intc_0 3>;
95                       bus-range = <0x00 0xff>;
96                       ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
97                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
98                       msi-map = <0x0 &its_gic 0x0 0x10000>;
99                       reg = <0x0 0xfca10000 0x0 0x1000>,
100                             <0x6 0x00000000 0x0 0x10000000>;
101                       reg-names = "cpm_slcr", "cfg";
102                       pcie_intc_0: interrupt-controller {
103                               #address-cells = <0>;
104                               #interrupt-cells = <1>;
105                               interrupt-controller;
106                       };
107               };
108
109               cpm5_pcie: pcie@fcdd0000 {
110                       compatible = "xlnx,versal-cpm5-host";
111                       device_type = "pci";
112                       #address-cells = <3>;
113                       #interrupt-cells = <1>;
114                       #size-cells = <2>;
115                       interrupts = <0 72 4>;
116                       interrupt-parent = <&gic>;
117                       interrupt-map-mask = <0 0 0 7>;
118                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
119                                       <0 0 0 2 &pcie_intc_1 1>,
120                                       <0 0 0 3 &pcie_intc_1 2>,
121                                       <0 0 0 4 &pcie_intc_1 3>;
122                       bus-range = <0x00 0xff>;
123                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
124                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
125                       msi-map = <0x0 &its_gic 0x0 0x10000>;
126                       reg = <0x00 0xfcdd0000 0x00 0x1000>,
127                             <0x06 0x00000000 0x00 0x1000000>,
128                             <0x00 0xfce20000 0x00 0x1000000>;
129                       reg-names = "cpm_slcr", "cfg", "cpm_csr";
130
131                       pcie_intc_1: interrupt-controller {
132                               #address-cells = <0>;
133                               #interrupt-cells = <1>;
134                               interrupt-controller;
135                       };
136               };
137
138    };
139