1/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. 2/// 3/// SPDX-License-Identifier: MIT 4/// 5 6namespace armnn 7{ 8/** 9@page operator_list Arm NN Operators 10 11@tableofcontents 12 13@section S5_1_operator_list Arm NN Operators 14 15Arm NN supports operators that are listed in below table. 16 17Arm NN supports a wide list of data-types. 18The main data-types that the Machine Learning functions support are the following: 19 <ul> 20 <li><b>BFLOAT16:</b> 16-bit non-standard brain floating point 21 <li><b>QASYMMU8:</b> 8-bit unsigned asymmetric quantized 22 <li><b>QASYMMS8:</b> 8-bit signed asymmetric quantized 23 <li><b>QUANTIZEDSYMM8PERAXIS:</b> 8-bit signed symmetric quantized 24 <li><b>QSYMMS8:</b> 8-bit signed symmetric quantized 25 <li><b>QSYMMS16:</b> 16-bit signed symmetric quantized 26 <li><b>FLOAT32:</b> 32-bit single precision floating point 27 <li><b>FLOAT16:</b> 16-bit half precision floating point 28 <li><b>SIGNED32:</b> 32-bit signed integer 29 <li><b>BOOLEAN:</b> 8-bit unsigned char 30 <li><b>All:</b> Agnostic to any specific data type 31 </ul> 32 33Arm NN supports the following data layouts (fast changing dimension from right to left): 34 <ul> 35 <li><b>NHWC:</b> Layout where channels are in the fastest changing dimension 36 <li><b>NCHW:</b> Layout where width is in the fastest changing dimension 37 <li><b>All:</b> Agnostic to any specific data layout 38 </ul> 39where N = batches, C = channels, H = height, W = width 40 41<table> 42<caption id="multi_row"></caption> 43<tr> 44 <th>Operator 45 <th>Description 46 <th>Equivalent Android NNAPI Operator 47 <th>Backends 48 <th>Data Layouts 49 <th>Data Types 50<tr> 51 <td rowspan="3">AbsLayer 52 <td rowspan="3"> Layer to perform absolute operation. 53 <td rowspan="3"> 54 <ul> 55 <li>ANEURALNETWORKS_ABS 56 </ul> 57 <td>CpuRef 58 <td> 59 <ul> 60 <li>All 61 </ul> 62 <td> 63 <table> 64 <tr><th> 65 <tr><td>BFLOAT16 66 <tr><td>FLOAT16 67 <tr><td>FLOAT32 68 <tr><td>QASYMMS8 69 <tr><td>QASYMMU8 70 <tr><td>QSYMMS16 71 <tr><td>SIGNED32 72 </table> 73<tr> 74 <td>CpuAcc 75 <td> 76 <ul> 77 <li>All 78 </ul> 79 <td> 80 <table> 81 <tr><th> 82 <tr><td>FLOAT16 83 <tr><td>FLOAT32 84 <tr><td>SIGNED32 85 </table> 86<tr> 87 <td>GpuAcc 88 <td> 89 <ul> 90 <li>All 91 </ul> 92 <td> 93 <table> 94 <tr><th> 95 <tr><td>FLOAT16 96 <tr><td>FLOAT32 97 </table> 98<tr> 99 <td rowspan="3">ActivationLayer 100 <td rowspan="3" style="width:200px;"> Layer to simulate an activation layer with the specified activation function. 101 <td rowspan="3"> 102 <ul> 103 <li>ANEURALNETWORKS_ABS 104 <li>ANEURALNETWORKS_ELU 105 <li>ANEURALNETWORKS_HARD_SWISH 106 <li>ANEURALNETWORKS_LOGISTIC 107 <li>ANEURALNETWORKS_PRELU 108 <li>ANEURALNETWORKS_RELU 109 <li>ANEURALNETWORKS_RELU1 110 <li>ANEURALNETWORKS_RELU6 111 <li>ANEURALNETWORKS_SQRT 112 <li>ANEURALNETWORKS_TANH 113 </ul> 114 <td>CpuRef 115 <td> 116 <ul> 117 <li>All 118 </ul> 119 <td> 120 <table> 121 <tr><th> 122 <tr><td>BFLOAT16 123 <tr><td>FLOAT16 124 <tr><td>FLOAT32 125 <tr><td>QASYMMS8 126 <tr><td>QASYMMU8 127 <tr><td>QSYMMS16 128 </table> 129<tr> 130 <td>CpuAcc 131 <td> 132 <ul> 133 <li>All 134 </ul> 135 <td> 136 <table> 137 <tr><th> 138 <tr><td>QASYMMU8 139 <tr><td>QASYMMS8 140 <tr><td>QSYMMS16 141 <tr><td>FLOAT16 142 <tr><td>FLOAT32 143 </table> 144<tr> 145 <td>GpuAcc 146 <td> 147 <ul> 148 <li>All 149 </ul> 150 <td> 151 <table> 152 <tr><th> 153 <tr><td>QASYMMU8 154 <tr><td>QASYMMS8 155 <tr><td>QSYMMS16 156 <tr><td>FLOAT16 157 <tr><td>FLOAT32 158 </table> 159<tr> 160 <td rowspan="3">AdditionLayer 161 <td rowspan="3" style="width:200px;"> Layer to add 2 tensors. 162 <td rowspan="3"> 163 <ul> 164 <li>ANEURALNETWORKS_ADD 165 </ul> 166 <td>CpuRef 167 <td> 168 <ul> 169 <li>All 170 </ul> 171 <td> 172 <table> 173 <tr><th> 174 <tr><td>BFLOAT16 175 <tr><td>FLOAT16 176 <tr><td>FLOAT32 177 <tr><td>QASYMMS8 178 <tr><td>QASYMMU8 179 <tr><td>QSYMMS16 180 <tr><td>SIGNED32 181 </table> 182<tr> 183 <td>CpuAcc 184 <td> 185 <ul> 186 <li>All 187 </ul> 188 <td> 189 <table> 190 <tr><th> 191 <tr><td>QASYMMU8 192 <tr><td>QASYMMS8 193 <tr><td>QSYMMS16 194 <tr><td>SIGNED32 195 <tr><td>FLOAT16 196 <tr><td>FLOAT32 197 </table> 198<tr> 199 <td>GpuAcc 200 <td> 201 <ul> 202 <li>All 203 </ul> 204 <td> 205 <table> 206 <tr><th> 207 <tr><td>QASYMMU8 208 <tr><td>QASYMMS8 209 <tr><td>QSYMMS16 210 <tr><td>SIGNED32 211 <tr><td>FLOAT16 212 <tr><td>FLOAT32 213 </table> 214<tr> 215 <td rowspan="3">ArgMinMaxLayer 216 <td rowspan="3" style="width:200px;"> Layer to calculate the index of the minimum or maximum values in a tensor 217 based on an axis. 218 <td rowspan="3"> 219 <ul> 220 <li>ANEURALNETWORKS_ARGMAX 221 <li>ANEURALNETWORKS_ARGMIN 222 </ul> 223 <td>CpuRef 224 <td> 225 <ul> 226 <li>All 227 </ul> 228 <td> 229 <table> 230 <tr><th> 231 <tr><td>BFLOAT16 232 <tr><td>FLOAT16 233 <tr><td>FLOAT32 234 <tr><td>QASYMMS8 235 <tr><td>QASYMMU8 236 <tr><td>QSYMMS16 237 <tr><td>SIGNED32 238 <tr><td>SIGNED64 239 </table> 240<tr> 241 <td>CpuAcc 242 <td> 243 <ul> 244 <li>All 245 </ul> 246 <td> 247 <table> 248 <tr><th> 249 <tr><td>QASYMMU8 250 <tr><td>QASYMMS8 251 <tr><td>SIGNED32 252 <tr><td>FLOAT16 253 <tr><td>FLOAT32 254 </table> 255<tr> 256 <td>GpuAcc 257 <td> 258 <ul> 259 <li>All 260 </ul> 261 <td> 262 <table> 263 <tr><th> 264 <tr><td>QASYMMU8 265 <tr><td>QASYMMS8 266 <tr><td>SIGNED32 267 <tr><td>FLOAT16 268 <tr><td>FLOAT32 269 </table> 270<tr> 271 <td rowspan="3">BatchMatMulLayer 272 <td rowspan="3" style="width:200px;"> Layer to perform batch matrix multiplication. 273 <td rowspan="3"> 274 <ul> 275 <li>N/A 276 </ul> 277 <td>CpuRef 278 <td> 279 <ul> 280 <li>All 281 </ul> 282 <td> 283 <table> 284 <tr><th> 285 <tr><td>BFLOAT16 286 <tr><td>FLOAT16 287 <tr><td>FLOAT32 288 <tr><td>QASYMMS8 289 <tr><td>QASYMMU8 290 <tr><td>QSYMMS16 291 </table> 292<tr> 293 <td>CpuAcc 294 <td> 295 <ul> 296 <li>All 297 </ul> 298 <td> 299 <table> 300 <tr><th> 301 <tr><td>FLOAT32 302 </table> 303<tr> 304 <td>GpuAcc 305 <td> 306 <ul> 307 <li>All 308 </ul> 309 <td> 310 <table> 311 <tr><th> 312 <tr><td>FLOAT32 313 </table> 314<tr> 315 <td rowspan="3">BatchNormalizationLayer 316 <td rowspan="3" style="width:200px;"> Layer to perform batch normalization. 317 <td rowspan="3"> 318 <ul> 319 <li>N/A 320 </ul> 321 <td>CpuRef 322 <td> 323 <ul> 324 <li>All 325 </ul> 326 <td> 327 <table> 328 <tr><th> 329 <tr><td>BFLOAT16 330 <tr><td>FLOAT16 331 <tr><td>FLOAT32 332 <tr><td>QASYMMS8 333 <tr><td>QASYMMU8 334 <tr><td>QSYMMS16 335 </table> 336<tr> 337 <td>CpuAcc 338 <td> 339 <ul> 340 <li>NHWC 341 <li>NCHW 342 </ul> 343 <td> 344 <table> 345 <tr><th> 346 <tr><td>FLOAT32 347 <tr><td>FLOAT16 348 </table> 349<tr> 350 <td>GpuAcc 351 <td> 352 <ul> 353 <li>NHWC 354 <li>NCHW 355 </ul> 356 <td> 357 <table> 358 <tr><th> 359 <tr><td>FLOAT32 360 <tr><td>FLOAT16 361 </table> 362<tr> 363 <td rowspan="3">BatchToSpaceNdLayer 364 <td rowspan="3" style="width:200px;"> Layer to perform a batch to space transformation. 365 <td rowspan="3"> 366 <ul> 367 <li>ANEURALNETWORKS_BATCH_TO_SPACE_ND 368 </ul> 369 <td>CpuRef 370 <td> 371 <ul> 372 <li>All 373 </ul> 374 <td> 375 <table> 376 <tr><th> 377 <tr><td>BFLOAT16 378 <tr><td>FLOAT16 379 <tr><td>FLOAT32 380 <tr><td>QASYMMS8 381 <tr><td>QASYMMU8 382 <tr><td>QSYMMS16 383 </table> 384<tr> 385 <td>CpuAcc 386 <td> 387 <ul> 388 <li>NHWC 389 <li>NCHW 390 </ul> 391 <td> 392 <table> 393 <tr><th> 394 <tr><td>All 395 </table> 396<tr> 397 <td>GpuAcc 398 <td> 399 <ul> 400 <li>NHWC 401 <li>NCHW 402 </ul> 403 <td> 404 <table> 405 <tr><th> 406 <tr><td>All 407 </table> 408<tr> 409 <td rowspan="3">CastLayer 410 <td rowspan="3" style="width:200px;"> Layer to cast a tensor to a type. 411 <td rowspan="3"> 412 <ul> 413 <li>ANEURALNETWORKS_CAST 414 </ul> 415 <td>CpuRef 416 <td> 417 <ul> 418 <li>All 419 </ul> 420 <td> 421 <table> 422 <tr><th> 423 <tr><td>BFLOAT16 424 <tr><td>FLOAT16 425 <tr><td>FLOAT32 426 <tr><td>QSYMMS8 427 <tr><td>QASYMMS8 428 <tr><td>QASYMMU8 429 <tr><td>QSYMMS16 430 <tr><td>SIGNED32 431 </table> 432<tr> 433 <td>CpuAcc 434 <td> 435 <ul> 436 <li>All 437 </ul> 438 <td> 439 <table> 440 <tr><th> 441 <tr><td>QASYMMS8 442 <tr><td>QASYMMU8 443 <tr><td>FLOAT16 444 <tr><td>SIGNED32 445 <tr><td>FLOAT32 446 </table> 447<tr> 448 <td>GpuAcc 449 <td> 450 <ul> 451 <li>All 452 </ul> 453 <td> 454 <table> 455 <tr><th> 456 <tr><td>QASYMMS8 457 <tr><td>QASYMMU8 458 <tr><td>SIGNED32 459 <tr><td>FLOAT16 460 <tr><td>FLOAT32 461 </table> 462<tr> 463 <td rowspan="3">ChannelShuffleLayer 464 <td rowspan="3" style="width:200px;"> Layer to reorganize the channels of a tensor. 465 <td rowspan="3"> 466 <ul> 467 <li>ANEURALNETWORKS_CHANNEL_SHUFFLE 468 </ul> 469 <td>CpuRef 470 <td> 471 <ul> 472 <li>All 473 </ul> 474 <td> 475 <table> 476 <tr><th> 477 <tr><td>FLOAT16 478 <tr><td>FLOAT32 479 <tr><td>QSYMMS8 480 <tr><td>QASYMMS8 481 <tr><td>QASYMMU8 482 </table> 483<tr> 484 <td>CpuAcc 485 <td> 486 <ul> 487 <li>All 488 </ul> 489 <td> 490 <table> 491 <tr><th> 492 <tr><td>QASYMMS8 493 <tr><td>QASYMMU8 494 <tr><td>FLOAT16 495 <tr><td>FLOAT32 496 </table> 497<tr> 498 <td>GpuAcc 499 <td> 500 <ul> 501 <li>All 502 </ul> 503 <td> 504 <table> 505 <tr><th> 506 <tr><td>QASYMMS8 507 <tr><td>QASYMMU8 508 <tr><td>FLOAT16 509 <tr><td>FLOAT32 510 </table> 511<tr> 512 <td rowspan="3">ComparisonLayer 513 <td rowspan="3" style="width:200px;"> Layer to compare 2 tensors. 514 <td rowspan="3"> 515 <ul> 516 <li>ANEURALNETWORKS_EQUAL 517 <li>ANEURALNETWORKS_GREATER 518 <li>ANEURALNETWORKS_GREATER_EQUAL 519 <li>ANEURALNETWORKS_LESS 520 <li>ANEURALNETWORKS_LESS_EQUAL 521 <li>ANEURALNETWORKS_NOT_EQUAL 522 </ul> 523 <td>CpuRef 524 <td> 525 <ul> 526 <li>All 527 </ul> 528 <td> 529 <table> 530 <tr><th> 531 <tr><td>BFLOAT16 532 <tr><td>FLOAT16 533 <tr><td>FLOAT32 534 <tr><td>BOOLEAN 535 <tr><td>QASYMMS8 536 <tr><td>QASYMMU8 537 <tr><td>QSYMMS16 538 <tr><td>SIGNED32 539 </table> 540<tr> 541 <td>CpuAcc 542 <td> 543 <ul> 544 <li>All 545 </ul> 546 <td> 547 <table> 548 <tr><th> 549 <tr><td>All 550 </table> 551<tr> 552 <td>GpuAcc 553 <td> 554 <ul> 555 <li>All 556 </ul> 557 <td> 558 <table> 559 <tr><th> 560 <tr><td>All 561 </table> 562<tr> 563 <td rowspan="3">ConcatLayer 564 <td rowspan="3" style="width:200px;"> Layer to concatenate tensors along a given axis. 565 <td rowspan="3"> 566 <ul> 567 <li>ANEURALNETWORKS_CONCATENATION 568 </ul> 569 <td>CpuRef 570 <td> 571 <ul> 572 <li>All 573 </ul> 574 <td> 575 <table> 576 <tr><th> 577 <tr><td>BFLOAT16 578 <tr><td>FLOAT16 579 <tr><td>FLOAT32 580 <tr><td>QASYMMS8 581 <tr><td>QASYMMU8 582 <tr><td>QSYMMS16 583 </table> 584<tr> 585 <td>CpuAcc 586 <td> 587 <ul> 588 <li>All 589 </ul> 590 <td> 591 <table> 592 <tr><th> 593 <tr><td>QASYMMU8 594 <tr><td>QASYMMS8 595 <tr><td>FLOAT16 596 <tr><td>FLOAT32 597 </table> 598<tr> 599 <td>GpuAcc 600 <td> 601 <ul> 602 <li>All 603 </ul> 604 <td> 605 <table> 606 <tr><th> 607 <tr><td>QASYMMU8 608 <tr><td>QASYMMS8 609 <tr><td>FLOAT16 610 <tr><td>FLOAT32 611 </table> 612<tr> 613 <td rowspan="3">ConstantLayer 614 <td rowspan="3" style="width:200px;"> Layer to provide a constant tensor. 615 <td rowspan="3"> 616 <ul> 617 <li>N/A 618 </ul> 619 <td>CpuRef 620 <td> 621 <ul> 622 <li>All 623 </ul> 624 <td> 625 <table> 626 <tr><th> 627 <tr><td>BFLOAT16 628 <tr><td>FLOAT16 629 <tr><td>FLOAT32 630 <tr><td>QASYMMS8 631 <tr><td>QASYMMU8 632 <tr><td>QSYMMS8 633 <tr><td>QSYMMS16 634 <tr><td>SIGNED32 635 </table> 636<tr> 637 <td>CpuAcc 638 <td> 639 <ul> 640 <li>All 641 </ul> 642 <td> 643 <table> 644 <tr><th> 645 <tr><td>All 646 </table> 647<tr> 648 <td>GpuAcc 649 <td> 650 <ul> 651 <li>All 652 </ul> 653 <td> 654 <table> 655 <tr><th> 656 <tr><td>All 657 </table> 658<tr> 659 <td rowspan="3">ConvertFp16ToFp32Layer 660 <td rowspan="3" style="width:200px;"> Layer to convert Float16 tensor to Float32 tensor. 661 <td rowspan="3"> 662 <ul> 663 <li>N/A 664 </ul> 665 <td>CpuRef 666 <td> 667 <ul> 668 <li>All 669 </ul> 670 <td> 671 <table> 672 <tr><th> 673 <tr><td>FLOAT16 674 <tr><td>FLOAT32 675 </table> 676<tr> 677 <td>CpuAcc 678 <td> 679 <ul> 680 <li>All 681 </ul> 682 <td> 683 <table> 684 <tr><th> 685 <tr><td>FLOAT16 686 <tr><td>FLOAT32 687 </table> 688<tr> 689 <td>GpuAcc 690 <td> 691 <ul> 692 <li>All 693 </ul> 694 <td> 695 <table> 696 <tr><th> 697 <tr><td>FLOAT16 698 <tr><td>FLOAT32 699 </table> 700<tr> 701 <td rowspan="3">ConvertFp32ToFp16Layer 702 <td rowspan="3" style="width:200px;"> Layer to convert Float32 tensor to Float16 tensor. 703 <td rowspan="3"> 704 <ul> 705 <li>N/A 706 </ul> 707 <td>CpuRef 708 <td> 709 <ul> 710 <li>All 711 </ul> 712 <td> 713 <table> 714 <tr><th> 715 <tr><td>FLOAT16 716 <tr><td>FLOAT32 717 </table> 718<tr> 719 <td>CpuAcc 720 <td> 721 <ul> 722 <li>All 723 </ul> 724 <td> 725 <table> 726 <tr><th> 727 <tr><td>FLOAT16 728 <tr><td>FLOAT32 729 </table> 730<tr> 731 <td>GpuAcc 732 <td> 733 <ul> 734 <li>All 735 </ul> 736 <td> 737 <table> 738 <tr><th> 739 <tr><td>FLOAT16 740 <tr><td>FLOAT32 741 </table> 742<tr> 743 <td rowspan="3">Convolution2dLayer 744 <td rowspan="3" style="width:200px;"> Layer to compute a convolution operation. 745 <td rowspan="3"> 746 <ul> 747 <li>ANEURALNETWORKS_CONV_2D 748 <li>ANEURALNETWORKS_GROUPED_CONV_2D 749 </ul> 750 <td>CpuRef 751 <td> 752 <ul> 753 <li>All 754 </ul> 755 <td> 756 <table> 757 <tr><th> 758 <tr><td>BFLOAT16 759 <tr><td>FLOAT16 760 <tr><td>FLOAT32 761 <tr><td>QASYMMS8 762 <tr><td>QASYMMU8 763 <tr><td>QSYMMS16 764 </table> 765<tr> 766 <td>CpuAcc 767 <td> 768 <ul> 769 <li>NHWC 770 <li>NCHW 771 </ul> 772 <td> 773 <table> 774 <tr><th> 775 <tr><td>SIGNED32 776 <tr><td>FLOAT16 777 <tr><td>FLOAT32 778 <tr><td>QASYMMU8 779 <tr><td>QASYMMS8 780 <tr><td>QUANTIZEDSYMM8PERAXIS 781 </table> 782<tr> 783 <td>GpuAcc 784 <td> 785 <ul> 786 <li>NHWC 787 <li>NCHW 788 </ul> 789 <td> 790 <table> 791 <tr><th> 792 <tr><td>SIGNED32 793 <tr><td>FLOAT16 794 <tr><td>FLOAT32 795 <tr><td>QASYMMU8 796 <tr><td>QASYMMS8 797 <tr><td>QUANTIZEDSYMM8PERAXIS 798 </table> 799<tr> 800 <td rowspan="3">Convolution3dLayer 801 <td rowspan="3" style="width:200px;"> Layer to compute a 3D convolution operation. 802 <td rowspan="3"> 803 <ul> 804 <li>N/A 805 </ul> 806 <td>CpuRef 807 <td> 808 <ul> 809 <li>NDHWC 810 </ul> 811 <td> 812 <table> 813 <tr><th> 814 <tr><td>BFLOAT16 815 <tr><td>FLOAT16 816 <tr><td>FLOAT32 817 <tr><td>QASYMMS8 818 <tr><td>QASYMMU8 819 <tr><td>QSYMMS8 820 <tr><td>QSYMMS16 821 </table> 822<tr> 823 <td>CpuAcc 824 <td> 825 <ul> 826 <li>N/A 827 </ul> 828 <td> 829 <ul> 830 <li>N/A 831 </ul> 832<tr> 833 <td>GpuAcc 834 <td> 835 <ul> 836 <li>N/A 837 </ul> 838 <td> 839 <ul> 840 <li>N/A 841 </ul> 842<tr> 843 <td rowspan="1">DebugLayer 844 <td rowspan="1" style="width:200px;"> Layer to print out inter layer tensor information. 845 <td rowspan="1"> 846 <ul> 847 <li>N/A 848 </ul> 849 <td>CpuRef 850 <td> 851 <ul> 852 <li>All 853 </ul> 854 <td> 855 <table> 856 <tr><th> 857 <tr><td>BFLOAT16 858 <tr><td>FLOAT16 859 <tr><td>FLOAT32 860 <tr><td>QASYMMS8 861 <tr><td>QASYMMU8 862 <tr><td>QSYMMS8 863 <tr><td>QSYMMS16 864 <tr><td>SIGNED32 865 </table> 866<tr> 867 <td rowspan="3">DepthToSpaceLayer 868 <td rowspan="3" style="width:200px;"> Layer to perform Depth to Space transformation. 869 <td rowspan="3"> 870 <ul> 871 <li>ANEURALNETWORKS_DEPTH_TO_SPACE 872 </ul> 873 <td>CpuRef 874 <td> 875 <ul> 876 <li>All 877 </ul> 878 <td> 879 <table> 880 <tr><th> 881 <tr><td>BFLOAT16 882 <tr><td>FLOAT16 883 <tr><td>FLOAT32 884 <tr><td>QASYMMS8 885 <tr><td>QASYMMU8 886 <tr><td>QSYMMS16 887 </table> 888<tr> 889 <td>CpuAcc 890 <td> 891 <ul> 892 <li>NHWC 893 <li>NCHW 894 </ul> 895 <td> 896 <table> 897 <tr><th> 898 <tr><td>All 899 </table> 900<tr> 901 <td>GpuAcc 902 <td> 903 <ul> 904 <li>NHWC 905 <li>NCHW 906 </ul> 907 <td> 908 <table> 909 <tr><th> 910 <tr><td>All 911 </table> 912<tr> 913 <td rowspan="3">DepthwiseConvolution2dLayer 914 <td rowspan="3" style="width:200px;"> Layer to compute a deconvolution or transpose convolution. 915 <td rowspan="3"> 916 <ul> 917 <li>ANEURALNETWORKS_DEPTHWISE_CONV_2D 918 </ul> 919 <td>CpuRef 920 <td> 921 <ul> 922 <li>All 923 </ul> 924 <td> 925 <table> 926 <tr><th> 927 <tr><td>BFLOAT16 928 <tr><td>FLOAT16 929 <tr><td>FLOAT32 930 <tr><td>QASYMMS8 931 <tr><td>QASYMMU8 932 <tr><td>QSYMMS8 933 <tr><td>QSYMMS16 934 </table> 935<tr> 936 <td>CpuAcc 937 <td> 938 <ul> 939 <li>NHWC 940 <li>NCHW 941 </ul> 942 <td> 943 <table> 944 <tr><th> 945 <tr><td>FLOAT16 946 <tr><td>FLOAT32 947 <tr><td>SIGNED32 948 <tr><td>QASYMMU8 949 <tr><td>QASYMMS8 950 <tr><td>QUANTIZEDSYMM8PERAXIS 951 </table> 952<tr> 953 <td>GpuAcc 954 <td> 955 <ul> 956 <li>NHWC 957 <li>NCHW 958 </ul> 959 <td> 960 <table> 961 <tr><th> 962 <tr><td>FLOAT16 963 <tr><td>FLOAT32 964 <tr><td>SIGNED32 965 <tr><td>QASYMMU8 966 <tr><td>QASYMMS8 967 <tr><td>QUANTIZEDSYMM8PERAXIS 968 </table> 969<tr> 970 <td rowspan="3">DequantizeLayer 971 <td rowspan="3" style="width:200px;"> Layer to dequantize the values in a tensor. 972 <td rowspan="3"> 973 <ul> 974 <li>ANEURALNETWORKS_DEQUANTIZE 975 </ul> 976 <td>CpuRef 977 <td> 978 <ul> 979 <li>All 980 </ul> 981 <td> 982 <table> 983 <tr><th> 984 <tr><td>QASYMMS8 985 <tr><td>QASYMMU8 986 <tr><td>QSYMMS8 987 <tr><td>QSYMMS16 988 </table> 989<tr> 990 <td>CpuAcc 991 <td> 992 <ul> 993 <li>All 994 </ul> 995 <td> 996 <table> 997 <tr><th> 998 <tr><td>FLOAT16 999 <tr><td>FLOAT32 1000 <tr><td>QASYMMU8 1001 <tr><td>QASYMMS8 1002 <tr><td>QUANTIZEDSYMM8PERAXIS 1003 <tr><td>QSYMMS8 1004 <tr><td>QSYMMS16 1005 </table> 1006<tr> 1007 <td>GpuAcc 1008 <td> 1009 <ul> 1010 <li>All 1011 </ul> 1012 <td> 1013 <table> 1014 <tr><th> 1015 <tr><td>FLOAT16 1016 <tr><td>FLOAT32 1017 <tr><td>QASYMMU8 1018 <tr><td>QASYMMS8 1019 <tr><td>QUANTIZEDSYMM8PERAXIS 1020 <tr><td>QSYMMS8 1021 <tr><td>QSYMMS16 1022 </table> 1023<tr> 1024 <td rowspan="2">DetectionPostProcessLayer 1025 <td rowspan="2" style="width:200px;"> Layer to generate the detection output based on center size encoded boxes, class prediction and anchors by doing non maximum suppression (NMS). 1026 <td rowspan="2"> 1027 <ul> 1028 <li>ANEURALNETWORKS_DETECTION_POSTPROCESSING 1029 </ul> 1030 <td>CpuRef 1031 <td> 1032 <ul> 1033 <li>All 1034 </ul> 1035 <td> 1036 <table> 1037 <tr><th> 1038 <tr><td>BFLOAT16 1039 <tr><td>FLOAT16 1040 <tr><td>FLOAT32 1041 <tr><td>QASYMMS8 1042 <tr><td>QASYMMU8 1043 <tr><td>QSYMMS16 1044 </table> 1045<tr> 1046 <td>CpuAcc 1047 <td> 1048 <ul> 1049 <li>All 1050 </ul> 1051 <td> 1052 <table> 1053 <tr><th> 1054 <tr><td>QASYMMU8 1055 <tr><td>QASYMMS8 1056 <tr><td>FLOAT32 1057 </table> 1058<tr> 1059 <td rowspan="3">DivisionLayer 1060 <td rowspan="3" style="width:200px;"> Layer to divide 2 tensors. 1061 <td rowspan="3"> 1062 <ul> 1063 <li>ANEURALNETWORKS_DIV 1064 </ul> 1065 <td>CpuRef 1066 <td> 1067 <ul> 1068 <li>All 1069 </ul> 1070 <td> 1071 <table> 1072 <tr><th> 1073 <tr><td>BFLOAT16 1074 <tr><td>FLOAT16 1075 <tr><td>FLOAT32 1076 <tr><td>QASYMMS8 1077 <tr><td>QASYMMU8 1078 <tr><td>QSYMMS16 1079 <tr><td>SIGNED32 1080 </table> 1081<tr> 1082 <td>CpuAcc 1083 <td> 1084 <ul> 1085 <li>All 1086 </ul> 1087 <td> 1088 <table> 1089 <tr><th> 1090 <tr><td>FLOAT16 1091 <tr><td>FLOAT32 1092 </table> 1093<tr> 1094 <td>GpuAcc 1095 <td> 1096 <ul> 1097 <li>All 1098 </ul> 1099 <td> 1100 <table> 1101 <tr><th> 1102 <tr><td>FLOAT16 1103 <tr><td>FLOAT32 1104 </table> 1105<tr> 1106 <td rowspan="3">ElementwiseBaseLayer 1107 <td rowspan="3" style="width:200px;"> Layer to perform Add - Div - Max - Min - Mul operations. 1108 <td rowspan="3"> 1109 <ul> 1110 <li>ANEURALNETWORKS_ADD 1111 <li>ANEURALNETWORKS_DIV 1112 <li>ANEURALNETWORKS_MAXIMUM 1113 <li>ANEURALNETWORKS_MINIMUM 1114 <li>ANEURALNETWORKS_MUL 1115 </ul> 1116 <td>CpuRef 1117 <td> 1118 <ul> 1119 <li>All 1120 </ul> 1121 <td> 1122 <table> 1123 <tr><th> 1124 <tr><td>BFLOAT16 1125 <tr><td>FLOAT16 1126 <tr><td>FLOAT32 1127 <tr><td>QASYMMS8 1128 <tr><td>QASYMMU8 1129 <tr><td>QSYMMS16 1130 <tr><td>SIGNED32 1131 </table> 1132<tr> 1133 <td>CpuAcc 1134 <td> 1135 <ul> 1136 <li>All 1137 </ul> 1138 <td> 1139 <table> 1140 <tr><th> 1141 <tr><td>QASYMMU8 1142 <tr><td>QASYMMS8 1143 <tr><td>QSYMMS16 1144 <tr><td>SIGNED32 1145 <tr><td>FLOAT16 1146 <tr><td>FLOAT32 1147 </table> 1148<tr> 1149 <td>GpuAcc 1150 <td> 1151 <ul> 1152 <li>All 1153 </ul> 1154 <td> 1155 <table> 1156 <tr><th> 1157 <tr><td>QASYMMU8 1158 <tr><td>QASYMMS8 1159 <tr><td>QSYMMS16 1160 <tr><td>SIGNED32 1161 <tr><td>FLOAT16 1162 <tr><td>FLOAT32 1163 </table> 1164<tr> 1165 <td rowspan="3">ElementwiseUnaryLayer 1166 <td rowspan="3" style="width:200px;"> Layer to perform Rsqrt - Exp - Neg - Log - Abs - Sin - Sqrt operations. 1167 <td rowspan="3"> 1168 <ul> 1169 <li>ANEURALNETWORKS_ABS 1170 <li>ANEURALNETWORKS_EXP 1171 <li>ANEURALNETWORKS_LOG 1172 <li>ANEURALNETWORKS_NEG 1173 <li>ANEURALNETWORKS_RSQRT 1174 <li>ANEURALNETWORKS_SIN 1175 <li>ANEURALNETWORKS_SQRT 1176 </ul> 1177 <td>CpuRef 1178 <td> 1179 <ul> 1180 <li>All 1181 </ul> 1182 <td> 1183 <table> 1184 <tr><th> 1185 <tr><td>BFLOAT16 1186 <tr><td>FLOAT16 1187 <tr><td>FLOAT32 1188 <tr><td>QASYMMS8 1189 <tr><td>QASYMMU8 1190 <tr><td>QSYMMS16 1191 </table> 1192<tr> 1193 <td>CpuAcc 1194 <td> 1195 <ul> 1196 <li>All 1197 </ul> 1198 <td> 1199 <table> 1200 <tr><th> 1201 <tr><td>FLOAT16 1202 <tr><td>FLOAT32 1203 <tr><td>SIGNED32 1204 </table> 1205<tr> 1206 <td>GpuAcc 1207 <td> 1208 <ul> 1209 <li>All 1210 </ul> 1211 <td> 1212 <table> 1213 <tr><th> 1214 <tr><td>FLOAT16 1215 <tr><td>FLOAT32 1216 </table> 1217<tr> 1218 <td rowspan="1">FakeQuantizationLayer 1219 <td rowspan="1" style="width:200px;"> Layer to quantize float values and dequantize afterwards. The current implementation does not dequantize the values. 1220 <td rowspan="1"> 1221 <ul> 1222 <li>N/A 1223 </ul> 1224 <td>CpuRef 1225 <td> 1226 <ul> 1227 <li>All 1228 </ul> 1229 <td> 1230 <table> 1231 <tr><th> 1232 <tr><td>FLOAT32 1233 </table> 1234<tr> 1235 <td rowspan="3">FillLayer 1236 <td rowspan="3" style="width:200px;"> Layer to set the values of a tensor with a given value. 1237 <td rowspan="3"> 1238 <ul> 1239 <li>ANEURALNETWORKS_FILL 1240 </ul> 1241 <td>CpuRef 1242 <td> 1243 <ul> 1244 <li>All 1245 </ul> 1246 <td> 1247 <table> 1248 <tr><th> 1249 <tr><td>FLOAT16 1250 <tr><td>FLOAT32 1251 <tr><td>SIGNED32 1252 </table> 1253<tr> 1254 <td>CpuAcc 1255 <td> 1256 <ul> 1257 <li>All 1258 </ul> 1259 <td> 1260 <table> 1261 <tr><th> 1262 <tr><td>All 1263 </table> 1264<tr> 1265 <td>GpuAcc 1266 <td> 1267 <ul> 1268 <li>All 1269 </ul> 1270 <td> 1271 <table> 1272 <tr><th> 1273 <tr><td>All 1274 </table> 1275<tr> 1276 <td rowspan="3">FloorLayer 1277 <td rowspan="3" style="width:200px;"> Layer to round the value to the lowest whole number. 1278 <td rowspan="3"> 1279 <ul> 1280 <li>ANEURALNETWORKS_FLOOR 1281 </ul> 1282 <td>CpuRef 1283 <td> 1284 <ul> 1285 <li>All 1286 </ul> 1287 <td> 1288 <table> 1289 <tr><th> 1290 <tr><td>BFLOAT16 1291 <tr><td>FLOAT16 1292 <tr><td>FLOAT32 1293 </table> 1294<tr> 1295 <td>CpuAcc 1296 <td> 1297 <ul> 1298 <li>All 1299 </ul> 1300 <td> 1301 <table> 1302 <tr><th> 1303 <tr><td>FLOAT32 1304 <tr><td>FLOAT16 1305 </table> 1306<tr> 1307 <td>GpuAcc 1308 <td> 1309 <ul> 1310 <li>All 1311 </ul> 1312 <td> 1313 <table> 1314 <tr><th> 1315 <tr><td>FLOAT32 1316 <tr><td>FLOAT16 1317 </table> 1318<tr> 1319 <td rowspan="3">FullyConnectedLayer 1320 <td rowspan="3" style="width:200px;"> Layer to perform a fully connected / dense operation. 1321 <td rowspan="3"> 1322 <ul> 1323 <li>ANEURALNETWORKS_FULLY_CONNECTED 1324 </ul> 1325 <td>CpuRef 1326 <td> 1327 <ul> 1328 <li>All 1329 </ul> 1330 <td> 1331 <table> 1332 <tr><th> 1333 <tr><td>BFLOAT16 1334 <tr><td>FLOAT16 1335 <tr><td>FLOAT32 1336 <tr><td>QASYMMS8 1337 <tr><td>QASYMMU8 1338 <tr><td>QSYMMS16 1339 </table> 1340<tr> 1341 <td>CpuAcc 1342 <td> 1343 <ul> 1344 <li>NHWC 1345 <li>NCHW 1346 </ul> 1347 <td> 1348 <table> 1349 <tr><th> 1350 <tr><td>SIGNED32 1351 <tr><td>FLOAT16 1352 <tr><td>FLOAT32 1353 <tr><td>QASYMMU8 1354 <tr><td>QASYMMS8 1355 </table> 1356<tr> 1357 <td>GpuAcc 1358 <td> 1359 <ul> 1360 <li>NHWC 1361 <li>NCHW 1362 </ul> 1363 <td> 1364 <table> 1365 <tr><th> 1366 <tr><td>SIGNED32 1367 <tr><td>FLOAT16 1368 <tr><td>FLOAT32 1369 <tr><td>QASYMMU8 1370 <tr><td>QASYMMS8 1371 </table> 1372<tr> 1373 <td rowspan="3">GatherLayer 1374 <td rowspan="3" style="width:200px;"> Layer to perform the gather operation along the chosen axis. 1375 <td rowspan="3"> 1376 <ul> 1377 <li>ANEURALNETWORKS_GATHER 1378 </ul> 1379 <td>CpuRef 1380 <td> 1381 <ul> 1382 <li>All 1383 </ul> 1384 <td> 1385 <table> 1386 <tr><th> 1387 <tr><td>BFLOAT16 1388 <tr><td>FLOAT16 1389 <tr><td>FLOAT32 1390 <tr><td>QASYMMS8 1391 <tr><td>QASYMMU8 1392 <tr><td>QSYMMS16 1393 <tr><td>SIGNED32 1394 </table> 1395<tr> 1396 <td>CpuAcc 1397 <td> 1398 <ul> 1399 <li>All 1400 </ul> 1401 <td> 1402 <table> 1403 <tr><th> 1404 <tr><td>All 1405 </table> 1406<tr> 1407 <td>GpuAcc 1408 <td> 1409 <ul> 1410 <li>All 1411 </ul> 1412 <td> 1413 <table> 1414 <tr><th> 1415 <tr><td>All 1416 </table> 1417<tr> 1418 <td rowspan="3">GatherNdLayer 1419 <td rowspan="3" style="width:200px;"> Layer to perform the gatherNd operation. 1420 <td rowspan="3"> 1421 <ul> 1422 <li>N/A 1423 </ul> 1424 <td>CpuRef 1425 <td> 1426 <ul> 1427 <li>All 1428 </ul> 1429 <td> 1430 <table> 1431 <tr><th> 1432 <tr><td>BFLOAT16 1433 <tr><td>FLOAT16 1434 <tr><td>FLOAT32 1435 <tr><td>QASYMMS8 1436 <tr><td>QASYMMU8 1437 <tr><td>QSYMMS16 1438 <tr><td>SIGNED32 1439 </table> 1440<tr> 1441 <td>CpuAcc 1442 <td> 1443 <ul> 1444 <li>All 1445 </ul> 1446 <td> 1447 <table> 1448 <tr><th> 1449 <tr><td>BFLOAT16 1450 <tr><td>FLOAT16 1451 <tr><td>FLOAT32 1452 <tr><td>QASYMMS8 1453 <tr><td>QASYMMU8 1454 <tr><td>QSYMMS16 1455 <tr><td>SIGNED32 1456 </table> 1457<tr> 1458 <td>GpuAcc 1459 <td> 1460 <ul> 1461 <li>All 1462 </ul> 1463 <td> 1464 <table> 1465 <tr><th> 1466 <tr><td>BFLOAT16 1467 <tr><td>FLOAT16 1468 <tr><td>FLOAT32 1469 <tr><td>QASYMMS8 1470 <tr><td>QASYMMU8 1471 <tr><td>QSYMMS16 1472 <tr><td>SIGNED32 1473 </table> 1474<tr> 1475 <td rowspan="1">InputLayer 1476 <td rowspan="1" style="width:200px;"> Special layer used to provide input data to the computational network. 1477 <td rowspan="1"> 1478 <ul> 1479 <li>N/A 1480 </ul> 1481 <td>All 1482 <td> 1483 <ul> 1484 <li>All 1485 </ul> 1486 <td> 1487 <table> 1488 <tr><th> 1489 <tr><td>All 1490 </table> 1491<tr> 1492 <td rowspan="3">InstanceNormalizationLayer 1493 <td rowspan="3" style="width:200px;"> Layer to perform an instance normalization on a given axis. 1494 <td rowspan="3"> 1495 <ul> 1496 <li>ANEURALNETWORKS_INSTANCE_NORMALIZATION 1497 </ul> 1498 <td>CpuRef 1499 <td> 1500 <ul> 1501 <li>All 1502 </ul> 1503 <td> 1504 <table> 1505 <tr><th> 1506 <tr><td>BFLOAT16 1507 <tr><td>FLOAT16 1508 <tr><td>FLOAT32 1509 </table> 1510<tr> 1511 <td>CpuAcc 1512 <td> 1513 <ul> 1514 <li>NHWC 1515 <li>NCHW 1516 </ul> 1517 <td> 1518 <table> 1519 <tr><th> 1520 <tr><td>FLOAT16 1521 <tr><td>FLOAT32 1522 </table> 1523<tr> 1524 <td>GpuAcc 1525 <td> 1526 <ul> 1527 <li>NHWC 1528 <li>NCHW 1529 </ul> 1530 <td> 1531 <table> 1532 <tr><th> 1533 <tr><td>FLOAT16 1534 <tr><td>FLOAT32 1535 </table> 1536<tr> 1537 <td rowspan="3">L2NormalizationLayer 1538 <td rowspan="3" style="width:200px;"> Layer to perform an L2 normalization on a given axis. 1539 <td rowspan="3"> 1540 <ul> 1541 <li>ANEURALNETWORKS_L2_NORMALIZATION 1542 </ul> 1543 <td>CpuRef 1544 <td> 1545 <ul> 1546 <li>All 1547 </ul> 1548 <td> 1549 <table> 1550 <tr><th> 1551 <tr><td>BFLOAT16 1552 <tr><td>FLOAT16 1553 <tr><td>FLOAT32 1554 <tr><td>QASYMMS8 1555 <tr><td>QASYMMU8 1556 <tr><td>QSYMMS16 1557 </table> 1558<tr> 1559 <td>CpuAcc 1560 <td> 1561 <ul> 1562 <li>NHWC 1563 <li>NCHW 1564 </ul> 1565 <td> 1566 <table> 1567 <tr><th> 1568 <tr><td>FLOAT16 1569 <tr><td>FLOAT32 1570 </table> 1571<tr> 1572 <td>GpuAcc 1573 <td> 1574 <ul> 1575 <li>NHWC 1576 <li>NCHW 1577 </ul> 1578 <td> 1579 <table> 1580 <tr><th> 1581 <tr><td>FLOAT16 1582 <tr><td>FLOAT32 1583 </table> 1584<tr> 1585 <td rowspan="3">LogSoftmaxLayer 1586 <td rowspan="3" style="width:200px;"> Layer to perform the log softmax activations given logits. 1587 <td rowspan="3"> 1588 <ul> 1589 <li>N/A 1590 </ul> 1591 <td>CpuRef 1592 <td> 1593 <ul> 1594 <li>All 1595 </ul> 1596 <td> 1597 <table> 1598 <tr><th> 1599 <tr><td>BFLOAT16 1600 <tr><td>FLOAT16 1601 <tr><td>FLOAT32 1602 </table> 1603<tr> 1604 <td>CpuAcc 1605 <td> 1606 <ul> 1607 <li>All 1608 </ul> 1609 <td> 1610 <table> 1611 <tr><th> 1612 <tr><td>QASYMMU8 1613 <tr><td>QASYMMS8 1614 <tr><td>FLOAT16 1615 <tr><td>FLOAT32 1616 </table> 1617<tr> 1618 <td>GpuAcc 1619 <td> 1620 <ul> 1621 <li>All 1622 </ul> 1623 <td> 1624 <table> 1625 <tr><th> 1626 <tr><td>QASYMMU8 1627 <tr><td>QASYMMS8 1628 <tr><td>FLOAT16 1629 <tr><td>FLOAT32 1630 </table> 1631<tr> 1632 <td rowspan="3">LogicalBinaryLayer 1633 <td rowspan="3" style="width:200px;"> Layer to perform Logical AND - Logical NOT - Logical OR operations. 1634 <td rowspan="3"> 1635 <ul> 1636 <li>ANEURALNETWORKS_LOGICAL_AND 1637 <li>ANEURALNETWORKS_LOGICAL_NOT 1638 <li>ANEURALNETWORKS_LOGICAL_OR 1639 </ul> 1640 <td>CpuRef 1641 <td> 1642 <ul> 1643 <li>All 1644 </ul> 1645 <td> 1646 <table> 1647 <tr><th> 1648 <tr><td>BOOLEAN 1649 </table> 1650<tr> 1651 <td>CpuAcc 1652 <td> 1653 <ul> 1654 <li>All 1655 </ul> 1656 <td> 1657 <table> 1658 <tr><th> 1659 <tr><td>BOOLEAN 1660 </table> 1661<tr> 1662 <td>GpuAcc 1663 <td> 1664 <ul> 1665 <li>All 1666 </ul> 1667 <td> 1668 <table> 1669 <tr><th> 1670 <tr><td>BOOLEAN 1671 </table> 1672<tr> 1673 <td rowspan="3">LstmLayer 1674 <td rowspan="3" style="width:200px;"> Layer to perform a single time step in a Long Short-Term Memory (LSTM) operation. 1675 <td rowspan="3"> 1676 <ul> 1677 <li>ANEURALNETWORKS_LSTM 1678 </ul> 1679 <td>CpuRef 1680 <td> 1681 <ul> 1682 <li>All 1683 </ul> 1684 <td> 1685 <table> 1686 <tr><th> 1687 <tr><td>BFLOAT16 1688 <tr><td>FLOAT16 1689 <tr><td>QSYMMS16 1690 </table> 1691<tr> 1692 <td>CpuAcc 1693 <td> 1694 <ul> 1695 <li>All 1696 </ul> 1697 <td> 1698 <table> 1699 <tr><th> 1700 <tr><td>FLOAT16 1701 <tr><td>FLOAT32 1702 </table> 1703<tr> 1704 <td>GpuAcc 1705 <td> 1706 <ul> 1707 <li>All 1708 </ul> 1709 <td> 1710 <table> 1711 <tr><th> 1712 <tr><td>FLOAT16 1713 <tr><td>FLOAT32 1714 </table> 1715<tr> 1716 <td rowspan="3">MapLayer 1717 <td rowspan="3" style="width:200px;"> Layer to perform map operation on tensor. 1718 <td rowspan="3"> 1719 <ul> 1720 <li>N/A 1721 </ul> 1722 <td>CpuRef 1723 <td> 1724 <ul> 1725 <li>All 1726 </ul> 1727 <td> 1728 <table> 1729 <tr><th> 1730 <tr><td>All 1731 </table> 1732<tr> 1733 <td>CpuAcc 1734 <td> 1735 <ul> 1736 <li>All 1737 </ul> 1738 <td> 1739 <table> 1740 <tr><th> 1741 <tr><td>All 1742 </table> 1743<tr> 1744 <td>GpuAcc 1745 <td> 1746 <ul> 1747 <li>All 1748 </ul> 1749 <td> 1750 <table> 1751 <tr><th> 1752 <tr><td>All 1753 </table> 1754<tr> 1755 <td rowspan="3">MaximumLayer 1756 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise maximum of two tensors. 1757 <td rowspan="3"> 1758 <ul> 1759 <li>N/A 1760 </ul> 1761 <td>CpuRef 1762 <td> 1763 <ul> 1764 <li>All 1765 </ul> 1766 <td> 1767 <table> 1768 <tr><th> 1769 <tr><td>BFLOAT16 1770 <tr><td>FLOAT16 1771 <tr><td>FLOAT32 1772 <tr><td>QASYMMS8 1773 <tr><td>QASYMMU8 1774 <tr><td>QSYMMS16 1775 <tr><td>SIGNED32 1776 </table> 1777<tr> 1778 <td>CpuAcc 1779 <td> 1780 <ul> 1781 <li>All 1782 </ul> 1783 <td> 1784 <table> 1785 <tr><th> 1786 <tr><td>QASYMMU8 1787 <tr><td>QASYMMS8 1788 <tr><td>FLOAT16 1789 <tr><td>FLOAT32 1790 <tr><td>SIGNED32 1791 </table> 1792<tr> 1793 <td>GpuAcc 1794 <td> 1795 <ul> 1796 <li>All 1797 </ul> 1798 <td> 1799 <table> 1800 <tr><th> 1801 <tr><td>QASYMMU8 1802 <tr><td>QASYMMS8 1803 <tr><td>QSYMMS16 1804 <tr><td>FLOAT16 1805 <tr><td>FLOAT32 1806 <tr><td>SIGNED32 1807 </table> 1808<tr> 1809 <td rowspan="3">MeanLayer 1810 <td rowspan="3" style="width:200px;"> Layer to perform reduce mean operation. 1811 <td rowspan="3"> 1812 <ul> 1813 <li>ANEURALNETWORKS_MEAN 1814 </ul> 1815 <td>CpuRef 1816 <td> 1817 <ul> 1818 <li>All 1819 </ul> 1820 <td> 1821 <table> 1822 <tr><th> 1823 <tr><td>BFLOAT16 1824 <tr><td>FLOAT16 1825 <tr><td>FLOAT32 1826 <tr><td>QASYMMS8 1827 <tr><td>QASYMMU8 1828 <tr><td>QSYMMS16 1829 </table> 1830<tr> 1831 <td>CpuAcc 1832 <td> 1833 <ul> 1834 <li>All 1835 </ul> 1836 <td> 1837 <table> 1838 <tr><th> 1839 <tr><td>QASYMMU8 1840 <tr><td>QASYMMS8 1841 <tr><td>FLOAT16 1842 <tr><td>FLOAT32 1843 </table> 1844<tr> 1845 <td>GpuAcc 1846 <td> 1847 <ul> 1848 <li>All 1849 </ul> 1850 <td> 1851 <table> 1852 <tr><th> 1853 <tr><td>QASYMMU8 1854 <tr><td>QASYMMS8 1855 <tr><td>FLOAT16 1856 <tr><td>FLOAT32 1857 </table> 1858<tr> 1859 <td rowspan="3">MemCopyLayer 1860 <td rowspan="3" style="width:200px;"> Layer to perform memory copy operation. 1861 <td rowspan="3"> 1862 <ul> 1863 <li>N/A 1864 </ul> 1865 <td>CpuRef 1866 <td> 1867 <ul> 1868 <li>All 1869 </ul> 1870 <td> 1871 <table> 1872 <tr><th> 1873 <tr><td>BFLOAT16 1874 <tr><td>FLOAT16 1875 <tr><td>FLOAT32 1876 <tr><td>QASYMMS8 1877 <tr><td>QASYMMU8 1878 <tr><td>QSYMMS16 1879 <tr><td>BOOLEAN 1880 </table> 1881<tr> 1882 <td>CpuAcc 1883 <td> 1884 <ul> 1885 <li>All 1886 </ul> 1887 <td> 1888 <table> 1889 <tr><th> 1890 <tr><td>All 1891 </table> 1892<tr> 1893 <td>GpuAcc 1894 <td> 1895 <ul> 1896 <li>All 1897 </ul> 1898 <td> 1899 <table> 1900 <tr><th> 1901 <tr><td>All 1902 </table> 1903<tr> 1904 <td rowspan="3">MemImportLayer 1905 <td rowspan="3" style="width:200px;"> Layer to perform memory import operation. 1906 <td rowspan="3"> 1907 <ul> 1908 <li>N/A 1909 </ul> 1910 <td>CpuRef 1911 <td> 1912 <ul> 1913 <li>All 1914 </ul> 1915 <td> 1916 <table> 1917 <tr><th> 1918 <tr><td>All 1919 </table> 1920<tr> 1921 <td>CpuAcc 1922 <td> 1923 <ul> 1924 <li>All 1925 </ul> 1926 <td> 1927 <table> 1928 <tr><th> 1929 <tr><td>All 1930 </table> 1931<tr> 1932 <td>GpuAcc 1933 <td> 1934 <ul> 1935 <li>All 1936 </ul> 1937 <td> 1938 <table> 1939 <tr><th> 1940 <tr><td>All 1941 </table> 1942<tr> 1943 <td rowspan="3">MergeLayer 1944 <td rowspan="3" style="width:200px;"> Layer to concatenate tensors along a given axis. 1945 <td rowspan="3"> 1946 <ul> 1947 <li>ANEURALNETWORKS_CONCATENATION 1948 </ul> 1949 <td>CpuRef 1950 <td> 1951 <ul> 1952 <li>All 1953 </ul> 1954 <td> 1955 <table> 1956 <tr><th> 1957 <tr><td>BFLOAT16 1958 <tr><td>FLOAT16 1959 <tr><td>FLOAT32 1960 <tr><td>QASYMMS8 1961 <tr><td>QASYMMU8 1962 <tr><td>QSYMMS16 1963 </table> 1964<tr> 1965 <td>CpuAcc 1966 <td> 1967 <ul> 1968 <li>All 1969 </ul> 1970 <td> 1971 <table> 1972 <tr><th> 1973 <tr><td>QASYMMU8 1974 <tr><td>QASYMMS8 1975 <tr><td>FLOAT16 1976 <tr><td>FLOAT32 1977 </table> 1978<tr> 1979 <td>GpuAcc 1980 <td> 1981 <ul> 1982 <li>All 1983 </ul> 1984 <td> 1985 <table> 1986 <tr><th> 1987 <tr><td>QASYMMU8 1988 <tr><td>QASYMMS8 1989 <tr><td>FLOAT16 1990 <tr><td>FLOAT32 1991 </table> 1992<tr> 1993 <td rowspan="3">MinimumLayer 1994 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise minimum of two tensors. 1995 <td rowspan="3"> 1996 <ul> 1997 <li>ANEURALNETWORKS_MINIMUM 1998 </ul> 1999 <td>CpuRef 2000 <td> 2001 <ul> 2002 <li>All 2003 </ul> 2004 <td> 2005 <table> 2006 <tr><th> 2007 <tr><td>BFLOAT16 2008 <tr><td>FLOAT16 2009 <tr><td>FLOAT32 2010 <tr><td>QASYMMS8 2011 <tr><td>QASYMMU8 2012 <tr><td>QSYMMS16 2013 <tr><td>SIGNED32 2014 </table> 2015<tr> 2016 <td>CpuAcc 2017 <td> 2018 <ul> 2019 <li>All 2020 </ul> 2021 <td> 2022 <table> 2023 <tr><th> 2024 <tr><td>QASYMMU8 2025 <tr><td>QASYMMS8 2026 <tr><td>QSYMMS16 2027 <tr><td>FLOAT16 2028 <tr><td>FLOAT32 2029 </table> 2030<tr> 2031 <td>GpuAcc 2032 <td> 2033 <ul> 2034 <li>All 2035 </ul> 2036 <td> 2037 <table> 2038 <tr><th> 2039 <tr><td>QASYMMU8 2040 <tr><td>QASYMMS8 2041 <tr><td>QSYMMS16 2042 <tr><td>FLOAT16 2043 <tr><td>FLOAT32 2044 <tr><td>SIGNED32 2045 </table> 2046<tr> 2047 <td rowspan="3">MultiplicationLayer 2048 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise multiplication of two tensors. 2049 <td rowspan="3"> 2050 <ul> 2051 <li>ANEURALNETWORKS_MUL 2052 </ul> 2053 <td>CpuRef 2054 <td> 2055 <ul> 2056 <li>All 2057 </ul> 2058 <td> 2059 <table> 2060 <tr><th> 2061 <tr><td>BFLOAT16 2062 <tr><td>FLOAT16 2063 <tr><td>FLOAT32 2064 <tr><td>QASYMMS8 2065 <tr><td>QASYMMU8 2066 <tr><td>QSYMMS16 2067 <tr><td>SIGNED32 2068 </table> 2069<tr> 2070 <td>CpuAcc 2071 <td> 2072 <ul> 2073 <li>All 2074 </ul> 2075 <td> 2076 <table> 2077 <tr><th> 2078 <tr><td>QASYMMU8 2079 <tr><td>QASYMMS8 2080 <tr><td>QSYMMS16 2081 <tr><td>SIGNED32 2082 <tr><td>FLOAT16 2083 <tr><td>FLOAT32 2084 </table> 2085<tr> 2086 <td>GpuAcc 2087 <td> 2088 <ul> 2089 <li>All 2090 </ul> 2091 <td> 2092 <table> 2093 <tr><th> 2094 <tr><td>QASYMMU8 2095 <tr><td>QASYMMS8 2096 <tr><td>QSYMMS16 2097 <tr><td>SIGNED32 2098 <tr><td>FLOAT16 2099 <tr><td>FLOAT32 2100 <tr><td>SIGNED32 2101 </table> 2102<tr> 2103 <td rowspan="3">NormalizationLayer 2104 <td rowspan="3" style="width:200px;"> Layer to compute normalization operation. 2105 <td rowspan="3"> 2106 <ul> 2107 <li>ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION 2108 </ul> 2109 <td>CpuRef 2110 <td> 2111 <ul> 2112 <li>All 2113 </ul> 2114 <td> 2115 <table> 2116 <tr><th> 2117 <tr><td>BFLOAT16 2118 <tr><td>FLOAT16 2119 <tr><td>FLOAT32 2120 <tr><td>QASYMMS8 2121 <tr><td>QASYMMU8 2122 <tr><td>QSYMMS16 2123 </table> 2124<tr> 2125 <td>CpuAcc 2126 <td> 2127 <ul> 2128 <li>NHWC 2129 <li>NCHW 2130 </ul> 2131 <td> 2132 <table> 2133 <tr><th> 2134 <tr><td>FLOAT32 2135 <tr><td>FLOAT16 2136 </table> 2137<tr> 2138 <td>GpuAcc 2139 <td> 2140 <ul> 2141 <li>NHWC 2142 <li>NCHW 2143 </ul> 2144 <td> 2145 <table> 2146 <tr><th> 2147 <tr><td>FLOAT32 2148 <tr><td>FLOAT16 2149 </table> 2150<tr> 2151 <td rowspan="1">OutputLayer 2152 <td rowspan="1" style="width:200px;"> A special layer providing access to a user supplied buffer into which the output of a network can be written. 2153 <td rowspan="1"> 2154 <ul> 2155 <li>N/A 2156 </ul> 2157 <td>All 2158 <td> 2159 <ul> 2160 <li>All 2161 </ul> 2162 <td> 2163 <table> 2164 <tr><th> 2165 <tr><td>All 2166 </table> 2167<tr> 2168 <td rowspan="3">PadLayer 2169 <td rowspan="3" style="width:200px;"> Layer to pad a tensor. 2170 <td rowspan="3"> 2171 <ul> 2172 <li>ANEURALNETWORKS_PAD 2173 <li>ANEURALNETWORKS_PAD_V2 2174 </ul> 2175 <td>CpuRef 2176 <td> 2177 <ul> 2178 <li>All 2179 </ul> 2180 <td> 2181 <table> 2182 <tr><th> 2183 <tr><td>BFLOAT16 2184 <tr><td>FLOAT16 2185 <tr><td>FLOAT32 2186 <tr><td>QASYMMS8 2187 <tr><td>QASYMMU8 2188 <tr><td>QSYMMS16 2189 </table> 2190<tr> 2191 <td>CpuAcc 2192 <td> 2193 <ul> 2194 <li>NHWC 2195 <li>NCHW 2196 </ul> 2197 <td> 2198 <table> 2199 <tr><th> 2200 <tr><td>All 2201 </table> 2202<tr> 2203 <td>GpuAcc 2204 <td> 2205 <ul> 2206 <li>NHWC 2207 <li>NCHW 2208 </ul> 2209 <td> 2210 <table> 2211 <tr><th> 2212 <tr><td>All 2213 </table> 2214<tr> 2215 <td rowspan="3">PermuteLayer 2216 <td rowspan="3" style="width:200px;"> Layer to transpose an ND tensor. 2217 <td rowspan="3"> 2218 <ul> 2219 <li>ANEURALNETWORKS_TRANSPOSE 2220 </ul> 2221 <td>CpuRef 2222 <td> 2223 <ul> 2224 <li>All 2225 </ul> 2226 <td> 2227 <table> 2228 <tr><th> 2229 <tr><td>BFLOAT16 2230 <tr><td>FLOAT16 2231 <tr><td>FLOAT32 2232 <tr><td>QASYMMS8 2233 <tr><td>QASYMMU8 2234 <tr><td>QSYMMS16 2235 </table> 2236<tr> 2237 <td>CpuAcc 2238 <td> 2239 <ul> 2240 <li>NHWC 2241 <li>NCHW 2242 </ul> 2243 <td> 2244 <table> 2245 <tr><th> 2246 <tr><td>All 2247 </table> 2248<tr> 2249 <td>GpuAcc 2250 <td> 2251 <ul> 2252 <li>NHWC 2253 <li>NCHW 2254 </ul> 2255 <td> 2256 <table> 2257 <tr><th> 2258 <tr><td>All 2259 </table> 2260<tr> 2261 <td rowspan="3">Pooling2dLayer 2262 <td rowspan="3" style="width:200px;"> Layer to perform 2D pooling with the specified pooling operation. 2263 <td rowspan="3"> 2264 <ul> 2265 <li>ANEURALNETWORKS_AVERAGE_POOL_2D 2266 <li>ANEURALNETWORKS_L2_POOL_2D 2267 <li>ANEURALNETWORKS_MAX_POOL_2D 2268 </ul> 2269 <td>CpuRef 2270 <td> 2271 <ul> 2272 <li>All 2273 </ul> 2274 <td> 2275 <table> 2276 <tr><th> 2277 <tr><td>BFLOAT16 2278 <tr><td>FLOAT16 2279 <tr><td>FLOAT32 2280 <tr><td>QASYMMS8 2281 <tr><td>QASYMMU8 2282 <tr><td>QSYMMS16 2283 </table> 2284<tr> 2285 <td>CpuAcc 2286 <td> 2287 <ul> 2288 <li>NHWC 2289 <li>NCHW 2290 </ul> 2291 <td> 2292 <table> 2293 <tr><th> 2294 <tr><td>QASYMMU8 2295 <tr><td>QASYMMS8 2296 <tr><td>FLOAT16 2297 <tr><td>FLOAT32 2298 </table> 2299<tr> 2300 <td>GpuAcc 2301 <td> 2302 <ul> 2303 <li>NHWC 2304 <li>NCHW 2305 </ul> 2306 <td> 2307 <table> 2308 <tr><th> 2309 <tr><td>QASYMMU8 2310 <tr><td>QASYMMS8 2311 <tr><td>FLOAT16 2312 <tr><td>FLOAT32 2313 </table> 2314<tr> 2315 <td rowspan="3">Pooling3dLayer 2316 <td rowspan="3" style="width:200px;"> Layer to perform 3D pooling with the specified pooling operation. 2317 <td rowspan="3"> 2318 <ul> 2319 <li>ANEURALNETWORKS_AVERAGE_POOL_3D 2320 <li>ANEURALNETWORKS_L2_POOL_3D 2321 <li>ANEURALNETWORKS_MAX_POOL_3D 2322 </ul> 2323 <td>CpuRef 2324 <td> 2325 <ul> 2326 <li>NDHWC 2327 </ul> 2328 <td> 2329 <table> 2330 <tr><th> 2331 <tr><td>BFLOAT16 2332 <tr><td>FLOAT16 2333 <tr><td>FLOAT32 2334 <tr><td>QASYMMS8 2335 <tr><td>QASYMMU8 2336 <tr><td>QSYMMS16 2337 </table> 2338<tr> 2339 <td>CpuAcc 2340 <td> 2341 <ul> 2342 <li>NA 2343 </ul> 2344 <td> 2345<tr> 2346 <td>GpuAcc 2347 <td> 2348 <ul> 2349 <li>NDHWC 2350 </ul> 2351<tr> 2352 <td rowspan="1">PreCompiledLayer 2353 <td rowspan="1" style="width:200px;"> Opaque layer provided by a backend which provides an executable representation of a subgraph from the original network. 2354 <td rowspan="1"> 2355 <ul> 2356 <li>N/A 2357 </ul> 2358 <td>N/A 2359 <td>N/A 2360 <td>N/A 2361<tr> 2362 <td rowspan="3">PreluLayer 2363 <td rowspan="3" style="width:200px;"> Layer to compute the activation layer with the PRELU activation function. 2364 <td rowspan="3"> 2365 <ul> 2366 <li>ANEURALNETWORKS_PRELU 2367 </ul> 2368 <td>CpuRef 2369 <td> 2370 <ul> 2371 <li>All 2372 </ul> 2373 <td> 2374 <table> 2375 <tr><th> 2376 <tr><td>BFLOAT16 2377 <tr><td>FLOAT16 2378 <tr><td>FLOAT32 2379 <tr><td>QASYMMS8 2380 <tr><td>QASYMMU8 2381 <tr><td>QSYMMS16 2382 </table> 2383<tr> 2384 <td>CpuAcc 2385 <td> 2386 <ul> 2387 <li>All 2388 </ul> 2389 <td> 2390 <table> 2391 <tr><th> 2392 <tr><td>QASYMMU8 2393 <tr><td>QASYMMS8 2394 <tr><td>FLOAT16 2395 <tr><td>FLOAT32 2396 </table> 2397<tr> 2398 <td>GpuAcc 2399 <td> 2400 <ul> 2401 <li>All 2402 </ul> 2403 <td> 2404 <table> 2405 <tr><th> 2406 <tr><td>QASYMMU8 2407 <tr><td>QASYMMS8 2408 <tr><td>FLOAT16 2409 <tr><td>FLOAT32 2410 </table> 2411<tr> 2412 <td rowspan="3">QLstmLayer 2413 <td rowspan="3" style="width:200px;"> Layer to perform quantized LSTM (Long Short-Term Memory) operation. 2414 <td rowspan="3"> 2415 <ul> 2416 <li>ANEURALNETWORKS_QUANTIZED_LSTM 2417 <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM 2418 </ul> 2419 <td>CpuRef 2420 <td> 2421 <ul> 2422 <li>All 2423 </ul> 2424 <td> 2425 <table> 2426 <tr><th> 2427 <tr><td>All 2428 </table> 2429<tr> 2430 <td>CpuAcc 2431 <td> 2432 <ul> 2433 <li>All 2434 </ul> 2435 <td> 2436 <table> 2437 <tr><th> 2438 <tr><td>QASYMMS8 2439 <tr><td>QASYMMU8 2440 <tr><td>SIGNED32 2441 <tr><td>QSYMMS16 2442 </table> 2443<tr> 2444 <td>GpuAcc 2445 <td> 2446 <ul> 2447 <li>All 2448 </ul> 2449 <td> 2450 <table> 2451 <tr><th> 2452 <tr><td>QASYMMS8 2453 <tr><td>QASYMMU8 2454 <tr><td>SIGNED32 2455 <tr><td>QSYMMS16 2456 </table> 2457<tr> 2458 <td rowspan="3">QuantizeLayer 2459 <td rowspan="3" style="width:200px;"> Layer to perform quantization operation. 2460 <td rowspan="3"> 2461 <ul> 2462 <li>ANEURALNETWORKS_QUANTIZE 2463 </ul> 2464 <td>CpuRef 2465 <td> 2466 <ul> 2467 <li>All 2468 </ul> 2469 <td> 2470 <table> 2471 <tr><th> 2472 <tr><td>BFLOAT16 2473 <tr><td>FLOAT16 2474 <tr><td>FLOAT32 2475 <tr><td>QASYMMS8 2476 <tr><td>QASYMMU8 2477 <tr><td>QSYMMS8 2478 <tr><td>QSYMMS16 2479 </table> 2480<tr> 2481 <td>CpuAcc 2482 <td> 2483 <ul> 2484 <li>All 2485 </ul> 2486 <td> 2487 <table> 2488 <tr><th> 2489 <tr><td>QASYMMU8 2490 <tr><td>QASYMMS8 2491 <tr><td>QASYMM16 2492 <tr><td>FLOAT16 2493 <tr><td>FLOAT32 2494 </table> 2495<tr> 2496 <td>GpuAcc 2497 <td> 2498 <ul> 2499 <li>All 2500 </ul> 2501 <td> 2502 <table> 2503 <tr><th> 2504 <tr><td>QASYMMU8 2505 <tr><td>QASYMMS8 2506 <tr><td>QASYMM16 2507 <tr><td>FLOAT16 2508 <tr><td>FLOAT32 2509 </table> 2510<tr> 2511 <td rowspan="3">QuantizedLstmLayer 2512 <td rowspan="3" style="width:200px;"> Layer to perform quantized LSTM (Long Short-Term Memory) operation. 2513 <td rowspan="3"> 2514 <ul> 2515 <li>ANEURALNETWORKS_QUANTIZED_LSTM 2516 <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM 2517 </ul> 2518 <td>CpuRef 2519 <td> 2520 <ul> 2521 <li>All 2522 </ul> 2523 <td> 2524 <table> 2525 <tr><th> 2526 <tr><td>All 2527 </table> 2528<tr> 2529 <td>CpuAcc 2530 <td> 2531 <ul> 2532 <li>All 2533 </ul> 2534 <td> 2535 <table> 2536 <tr><th> 2537 <tr><td>SIGNED32 2538 <tr><td>QASYMMU8 2539 <tr><td>QSYMMS16 2540 </table> 2541<tr> 2542 <td>GpuAcc 2543 <td> 2544 <ul> 2545 <li>All 2546 </ul> 2547 <td> 2548 <table> 2549 <tr><th> 2550 <tr><td>SIGNED32 2551 <tr><td>QASYMMU8 2552 <tr><td>QSYMMS16 2553 </table> 2554<tr> 2555 <td rowspan="3">RankLayer 2556 <td rowspan="3" style="width:200px;"> Layer to perform a rank operation. 2557 <td rowspan="3"> 2558 <ul> 2559 <li>ANEURALNETWORKS_RANK 2560 </ul> 2561 <td>CpuRef 2562 <td> 2563 <ul> 2564 <li>All 2565 </ul> 2566 <td> 2567 <table> 2568 <tr><th> 2569 <tr><td>All 2570 </table> 2571<tr> 2572 <td>CpuAcc 2573 <td> 2574 <ul> 2575 <li>All 2576 </ul> 2577 <td> 2578 <table> 2579 <tr><th> 2580 <tr><td>All 2581 </table> 2582<tr> 2583 <td>GpuAcc 2584 <td> 2585 <ul> 2586 <li>All 2587 </ul> 2588 <td> 2589 <table> 2590 <tr><th> 2591 <tr><td>All 2592 </table> 2593<tr> 2594 <td rowspan="3">ReduceLayer 2595 <td rowspan="3" style="width:200px;"> Layer to perform reduce with the following operations - ARG_IDX_MAX: Index of the max value - ARG_IDX_MIN: Index of the min value - MEAN_SUM: Mean of sum - PROD: Product - SUM_SQUARE: Sum of squares - SUM: Sum - MIN: Min - MAX: Max 2596 <td rowspan="3"> 2597 <ul> 2598 <li>ANEURALNETWORKS_REDUCE_MAX 2599 <li>ANEURALNETWORKS_REDUCE_MIN 2600 <li>ANEURALNETWORKS_REDUCE_SUM 2601 <li>ANEURALNETWORKS_REDUCE_PROD 2602 </ul> 2603 <td>CpuRef 2604 <td> 2605 <ul> 2606 <li>All 2607 </ul> 2608 <td> 2609 <table> 2610 <tr><th> 2611 <tr><td>BFLOAT16 2612 <tr><td>FLOAT16 2613 <tr><td>FLOAT32 2614 <tr><td>QASYMMS8 2615 <tr><td>QASYMMU8 2616 <tr><td>QSYMMS16 2617 <tr><td>SIGNED32 2618 </table> 2619<tr> 2620 <td>CpuAcc 2621 <td> 2622 <ul> 2623 <li>All 2624 </ul> 2625 <td> 2626 <table> 2627 <tr><th> 2628 <tr><td>QASYMMU8 2629 <tr><td>QASYMMS8 2630 <tr><td>FLOAT16 2631 <tr><td>FLOAT32 2632 <tr><td>SIGNED32 2633 </table> 2634<tr> 2635 <td>GpuAcc 2636 <td> 2637 <ul> 2638 <li>All 2639 </ul> 2640 <td> 2641 <table> 2642 <tr><th> 2643 <tr><td>QASYMMU8 2644 <tr><td>QASYMMS8 2645 <tr><td>FLOAT16 2646 <tr><td>FLOAT32 2647 <tr><td>SIGNED32 2648 </table> 2649<tr> 2650 <td rowspan="3">ReshapeLayer 2651 <td rowspan="3" style="width:200px;"> Layer to reshape a tensor. 2652 <td rowspan="3"> 2653 <ul> 2654 <li>ANEURALNETWORKS_RESHAPE 2655 <li>ANEURALNETWORKS_SQUEEZE 2656 <li>ANEURALNETWORKS_EXPAND_DIMS 2657 </ul> 2658 <td>CpuRef 2659 <td> 2660 <ul> 2661 <li>All 2662 </ul> 2663 <td> 2664 <table> 2665 <tr><th> 2666 <tr><td>BFLOAT16 2667 <tr><td>FLOAT16 2668 <tr><td>FLOAT32 2669 <tr><td>QASYMMS8 2670 <tr><td>QASYMMU8 2671 <tr><td>QSYMMS16 2672 <tr><td>SIGNED32 2673 <tr><td>BOOLEAN 2674 </table> 2675<tr> 2676 <td>CpuAcc 2677 <td> 2678 <ul> 2679 <li>All 2680 </ul> 2681 <td> 2682 <table> 2683 <tr><th> 2684 <tr><td>All 2685 </table> 2686<tr> 2687 <td>GpuAcc 2688 <td> 2689 <ul> 2690 <li>All 2691 </ul> 2692 <td> 2693 <table> 2694 <tr><th> 2695 <tr><td>All 2696 </table> 2697<tr> 2698 <td rowspan="3">ResizeLayer 2699 <td rowspan="3" style="width:200px;"> Layer to perform resize of a tensor using one of the interpolation methods: - Bilinear - Nearest Neighbor. 2700 <td rowspan="3"> 2701 <ul> 2702 <li>ANEURALNETWORKS_RESIZE_BILINEAR 2703 <li>ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR 2704 </ul> 2705 <td>CpuRef 2706 <td> 2707 <ul> 2708 <li>All 2709 </ul> 2710 <td> 2711 <table> 2712 <tr><th> 2713 <tr><td>BFLOAT16 2714 <tr><td>FLOAT16 2715 <tr><td>FLOAT32 2716 <tr><td>QASYMMS8 2717 <tr><td>QASYMMU8 2718 <tr><td>QSYMMS16 2719 </table> 2720<tr> 2721 <td>CpuAcc 2722 <td> 2723 <ul> 2724 <li>NHWC 2725 <li>NCHW 2726 </ul> 2727 <td> 2728 <table> 2729 <tr><th> 2730 <tr><td>QASYMMU8 2731 <tr><td>QASYMMS8 2732 <tr><td>FLOAT16 2733 <tr><td>FLOAT32 2734 </table> 2735<tr> 2736 <td>GpuAcc 2737 <td> 2738 <ul> 2739 <li>NHWC 2740 <li>NCHW 2741 </ul> 2742 <td> 2743 <table> 2744 <tr><th> 2745 <tr><td>QASYMMU8 2746 <tr><td>QASYMMS8 2747 <tr><td>FLOAT16 2748 <tr><td>FLOAT32 2749 </table> 2750<tr> 2751 <td rowspan="3">RsqrtLayer 2752 <td rowspan="3" style="width:200px;"> Layer to perform Rsqrt operation. 2753 <td rowspan="3"> 2754 <ul> 2755 <li>ANEURALNETWORKS_RSQRT 2756 </ul> 2757 <td>CpuRef 2758 <td> 2759 <ul> 2760 <li>All 2761 </ul> 2762 <td> 2763 <table> 2764 <tr><th> 2765 <tr><td>BFLOAT16 2766 <tr><td>FLOAT16 2767 <tr><td>FLOAT32 2768 <tr><td>QASYMMS8 2769 <tr><td>QASYMMU8 2770 <tr><td>QSYMMS16 2771 <tr><td>SIGNED32 2772 </table> 2773<tr> 2774 <td>CpuAcc 2775 <td> 2776 <ul> 2777 <li>All 2778 </ul> 2779 <td> 2780 <table> 2781 <tr><th> 2782 <tr><td>FLOAT16 2783 <tr><td>FLOAT32 2784 <tr><td>SIGNED32 2785 </table> 2786<tr> 2787 <td>GpuAcc 2788 <td> 2789 <ul> 2790 <li>All 2791 </ul> 2792 <td> 2793 <table> 2794 <tr><th> 2795 <tr><td>FLOAT16 2796 <tr><td>FLOAT32 2797 </table> 2798<tr> 2799 <td rowspan="3">ShapeLayer 2800 <td rowspan="3" style="width:200px;"> Layer to return the shape of the input tensor. 2801 <td rowspan="3"> 2802 <ul> 2803 <li>N/A 2804 </ul> 2805 <td>CpuRef 2806 <td> 2807 <ul> 2808 <li>All 2809 </ul> 2810 <td> 2811 <table> 2812 <tr><th> 2813 <tr><td>All 2814 </table> 2815<tr> 2816 <td>CpuAcc 2817 <td> 2818 <ul> 2819 <li>All 2820 </ul> 2821 <td> 2822 <table> 2823 <tr><th> 2824 <tr><td>All 2825 </table> 2826<tr> 2827 <td>GpuAcc 2828 <td> 2829 <ul> 2830 <li>All 2831 </ul> 2832 <td> 2833 <table> 2834 <tr><th> 2835 <tr><td>All 2836 </table> 2837<tr> 2838 <td rowspan="3">SliceLayer 2839 <td rowspan="3" style="width:200px;"> Layer to perform tensor slicing. 2840 <td rowspan="3"> 2841 <ul> 2842 <li>ANEURALNETWORKS_SLICE 2843 </ul> 2844 <td>CpuRef 2845 <td> 2846 <ul> 2847 <li>All 2848 </ul> 2849 <td> 2850 <table> 2851 <tr><th> 2852 <tr><td>BFLOAT16 2853 <tr><td>FLOAT32 2854 <tr><td>QASYMMS8 2855 <tr><td>QASYMMU8 2856 <tr><td>QSYMMS16 2857 </table> 2858<tr> 2859 <td>CpuAcc 2860 <td> 2861 <ul> 2862 <li>All 2863 </ul> 2864 <td> 2865 <table> 2866 <tr><th> 2867 <tr><td>All 2868 </table> 2869<tr> 2870 <td>GpuAcc 2871 <td> 2872 <ul> 2873 <li>All 2874 </ul> 2875 <td> 2876 <table> 2877 <tr><th> 2878 <tr><td>All 2879 </table> 2880<tr> 2881 <td rowspan="3">SoftmaxLayer 2882 <td rowspan="3" style="width:200px;"> Layer to perform softmax, log-softmax operation over the specified axis. 2883 <td rowspan="3"> 2884 <ul> 2885 <li>ANEURALNETWORKS_LOG_SOFTMAX 2886 <li>ANEURALNETWORKS_SOFTMAX 2887 </ul> 2888 <td>CpuRef 2889 <td> 2890 <ul> 2891 <li>All 2892 </ul> 2893 <td> 2894 <table> 2895 <tr><th> 2896 <tr><td>BFLOAT16 2897 <tr><td>FLOAT16 2898 <tr><td>FLOAT32 2899 <tr><td>QASYMMS8 2900 <tr><td>QASYMMU8 2901 <tr><td>QSYMMS8 2902 <tr><td>QSYMMS16 2903 </table> 2904<tr> 2905 <td>CpuAcc 2906 <td> 2907 <ul> 2908 <li>All 2909 </ul> 2910 <td> 2911 <table> 2912 <tr><th> 2913 <tr><td>QASYMMU8 2914 <tr><td>QASYMMS8 2915 <tr><td>FLOAT16 2916 <tr><td>FLOAT32 2917 </table> 2918<tr> 2919 <td>GpuAcc 2920 <td> 2921 <ul> 2922 <li>All 2923 </ul> 2924 <td> 2925 <table> 2926 <tr><th> 2927 <tr><td>QASYMMU8 2928 <tr><td>QASYMMS8 2929 <tr><td>FLOAT16 2930 <tr><td>FLOAT32 2931 </table> 2932<tr> 2933 <td rowspan="3">SpaceToBatchNdLayer 2934 <td rowspan="3" style="width:200px;"> Layer to divide spatial dimensions of the tensor into a grid of blocks and interleaves these blocks with the batch dimension. 2935 <td rowspan="3"> 2936 <ul> 2937 <li>ANEURALNETWORKS_SPACE_TO_BATCH_ND 2938 </ul> 2939 <td>CpuRef 2940 <td> 2941 <ul> 2942 <li>All 2943 </ul> 2944 <td> 2945 <table> 2946 <tr><th> 2947 <tr><td>BFLOAT16 2948 <tr><td>FLOAT16 2949 <tr><td>FLOAT32 2950 <tr><td>QASYMMS8 2951 <tr><td>QASYMMU8 2952 <tr><td>QSYMMS16 2953 </table> 2954<tr> 2955 <td>CpuAcc 2956 <td> 2957 <ul> 2958 <li>NHWC 2959 <li>NCHW 2960 </ul> 2961 <td> 2962 <table> 2963 <tr><th> 2964 <tr><td>All 2965 </table> 2966<tr> 2967 <td>GpuAcc 2968 <td> 2969 <ul> 2970 <li>NHWC 2971 <li>NCHW 2972 </ul> 2973 <td> 2974 <table> 2975 <tr><th> 2976 <tr><td>All 2977 </table> 2978<tr> 2979 <td rowspan="3">SpaceToDepthLayer 2980 <td rowspan="3" style="width:200px;"> Layer to rearrange blocks of spatial data into depth. 2981 <td rowspan="3"> 2982 <ul> 2983 <li>ANEURALNETWORKS_SPACE_TO_DEPTH 2984 </ul> 2985 <td>CpuRef 2986 <td> 2987 <ul> 2988 <li>All 2989 </ul> 2990 <td> 2991 <table> 2992 <tr><th> 2993 <tr><td>BFLOAT16 2994 <tr><td>FLOAT16 2995 <tr><td>FLOAT32 2996 <tr><td>QASYMMS8 2997 <tr><td>QASYMMU8 2998 <tr><td>QSYMMS16 2999 </table> 3000<tr> 3001 <td>CpuAcc 3002 <td> 3003 <ul> 3004 <li>NHWC 3005 <li>NCHW 3006 </ul> 3007 <td> 3008 <table> 3009 <tr><th> 3010 <tr><td>All 3011 </table> 3012<tr> 3013 <td>GpuAcc 3014 <td> 3015 <ul> 3016 <li>NHWC 3017 <li>NCHW 3018 </ul> 3019 <td> 3020 <table> 3021 <tr><th> 3022 <tr><td>All 3023 </table> 3024<tr> 3025 <td rowspan="3">SplitterLayer 3026 <td rowspan="3" style="width:200px;"> Layer to split a tensor along a given axis. 3027 <td rowspan="3"> 3028 <ul> 3029 <li>ANEURALNETWORKS_SPLIT 3030 </ul> 3031 <td>CpuRef 3032 <td> 3033 <ul> 3034 <li>All 3035 </ul> 3036 <td> 3037 <table> 3038 <tr><th> 3039 <tr><td>BFLOAT16 3040 <tr><td>FLOAT16 3041 <tr><td>FLOAT32 3042 <tr><td>QASYMMS8 3043 <tr><td>QASYMMU8 3044 <tr><td>QSYMMS16 3045 </table> 3046<tr> 3047 <td>CpuAcc 3048 <td> 3049 <ul> 3050 <li>All 3051 </ul> 3052 <td> 3053 <table> 3054 <tr><th> 3055 <tr><td>All 3056 </table> 3057<tr> 3058 <td>GpuAcc 3059 <td> 3060 <ul> 3061 <li>All 3062 </ul> 3063 <td> 3064 <table> 3065 <tr><th> 3066 <tr><td>All 3067 </table> 3068<tr> 3069 <td rowspan="3">StackLayer 3070 <td rowspan="3" style="width:200px;"> Layer to stack tensors along an axis. 3071 <td rowspan="3"> 3072 <ul> 3073 <li>N/A 3074 </ul> 3075 <td>CpuRef 3076 <td> 3077 <ul> 3078 <li>All 3079 </ul> 3080 <td> 3081 <table> 3082 <tr><th> 3083 <tr><td>BFLOAT16 3084 <tr><td>FLOAT16 3085 <tr><td>FLOAT32 3086 <tr><td>QASYMMS8 3087 <tr><td>QASYMMU8 3088 <tr><td>QSYMMS16 3089 </table> 3090<tr> 3091 <td>CpuAcc 3092 <td> 3093 <ul> 3094 <li>All 3095 </ul> 3096 <td> 3097 <table> 3098 <tr><th> 3099 <tr><td>All 3100 </table> 3101<tr> 3102 <td>GpuAcc 3103 <td> 3104 <ul> 3105 <li>All 3106 </ul> 3107 <td> 3108 <table> 3109 <tr><th> 3110 <tr><td>All 3111 </table> 3112<tr> 3113 <td rowspan="1">StandInLayer 3114 <td rowspan="1" style="width:200px;"> A layer to represent "unknown" or "unsupported" operations in the input graph. It has a configurable number of input and output slots and an optional name. 3115 <td rowspan="1"> 3116 <ul> 3117 <li>N/A 3118 </ul> 3119 <td>N/A 3120 <td>N/A 3121 <td>N/A 3122<tr> 3123 <td rowspan="3">StridedSliceLayer 3124 <td rowspan="3" style="width:200px;"> Layer to extract a strided slice of a tensor. 3125 <td rowspan="3"> 3126 <ul> 3127 <li>ANEURALNETWORKS_STRIDED_SLICE 3128 </ul> 3129 <td>CpuRef 3130 <td> 3131 <ul> 3132 <li>All 3133 </ul> 3134 <td> 3135 <table> 3136 <tr><th> 3137 <tr><td>BFLOAT16 3138 <tr><td>FLOAT32 3139 <tr><td>QASYMMS8 3140 <tr><td>QASYMMU8 3141 <tr><td>QSYMMS16 3142 </table> 3143<tr> 3144 <td>CpuAcc 3145 <td> 3146 <ul> 3147 <li>All 3148 </ul> 3149 <td> 3150 <table> 3151 <tr><th> 3152 <tr><td>All 3153 </table> 3154<tr> 3155 <td>GpuAcc 3156 <td> 3157 <ul> 3158 <li>All 3159 </ul> 3160 <td> 3161 <table> 3162 <tr><th> 3163 <tr><td>All 3164 </table> 3165<tr> 3166 <td rowspan="3">SubtractionLayer 3167 <td rowspan="3" style="width:200px;"> Layer to perform an elementwise subtract of 2 tensors. 3168 <td rowspan="3"> 3169 <ul> 3170 <li>ANEURALNETWORKS_SUB 3171 </ul> 3172 <td>CpuRef 3173 <td> 3174 <ul> 3175 <li>All 3176 </ul> 3177 <td> 3178 <table> 3179 <tr><th> 3180 <tr><td>BFLOAT16 3181 <tr><td>FLOAT16 3182 <tr><td>FLOAT32 3183 <tr><td>QASYMMS8 3184 <tr><td>QASYMMU8 3185 <tr><td>QSYMMS16 3186 <tr><td>SIGNED32 3187 </table> 3188<tr> 3189 <td>CpuAcc 3190 <td> 3191 <ul> 3192 <li>All 3193 </ul> 3194 <td> 3195 <table> 3196 <tr><th> 3197 <tr><td>QASYMMU8 3198 <tr><td>QASYMMS8 3199 <tr><td>QSYMMS16 3200 <tr><td>SIGNED32 3201 <tr><td>FLOAT16 3202 <tr><td>FLOAT32 3203 </table> 3204<tr> 3205 <td>GpuAcc 3206 <td> 3207 <ul> 3208 <li>All 3209 </ul> 3210 <td> 3211 <table> 3212 <tr><th> 3213 <tr><td>QASYMMU8 3214 <tr><td>QASYMMS8 3215 <tr><td>QSYMMS16 3216 <tr><td>SIGNED32 3217 <tr><td>FLOAT16 3218 <tr><td>FLOAT32 3219 </table> 3220<tr> 3221 <td rowspan="3">TransposeConvolution2dLayer 3222 <td rowspan="3" style="width:200px;"> Layer to perform 2D transpose convolution (deconvolution) operation. 3223 <td rowspan="3"> 3224 <ul> 3225 <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D 3226 </ul> 3227 <td>CpuRef 3228 <td> 3229 <ul> 3230 <li>All 3231 </ul> 3232 <td> 3233 <table> 3234 <tr><th> 3235 <tr><td>BFLOAT16 3236 <tr><td>FLOAT16 3237 <tr><td>FLOAT32 3238 <tr><td>QASYMMS8 3239 <tr><td>QASYMMU8 3240 <tr><td>QSYMMS8 3241 <tr><td>QSYMMS16 3242 </table> 3243<tr> 3244 <td>CpuAcc 3245 <td> 3246 <ul> 3247 <li>NHWC 3248 <li>NCHW 3249 </ul> 3250 <td> 3251 <table> 3252 <tr><th> 3253 <tr><td>SIGNED32 3254 <tr><td>FLOAT16 3255 <tr><td>FLOAT32 3256 <tr><td>QASYMMU8 3257 <tr><td>QASYMMS8 3258 <tr><td>QUANTIZEDSYMM8PERAXIS 3259 </table> 3260<tr> 3261 <td>GpuAcc 3262 <td> 3263 <ul> 3264 <li>NHWC 3265 <li>NCHW 3266 </ul> 3267 <td> 3268 <table> 3269 <tr><th> 3270 <tr><td>SIGNED32 3271 <tr><td>FLOAT16 3272 <tr><td>FLOAT32 3273 <tr><td>QASYMMU8 3274 <tr><td>QASYMMS8 3275 <tr><td>QUANTIZEDSYMM8PERAXIS 3276 </table> 3277<tr> 3278 <td rowspan="3">TransposeLayer 3279 <td rowspan="3" style="width:200px;"> Layer to transpose a tensor. 3280 <td rowspan="3"> 3281 <ul> 3282 <li>ANEURALNETWORKS_TRANSPOSE 3283 </ul> 3284 <td>CpuRef 3285 <td> 3286 <ul> 3287 <li>All 3288 </ul> 3289 <td> 3290 <table> 3291 <tr><th> 3292 <tr><td>BFLOAT16 3293 <tr><td>FLOAT16 3294 <tr><td>FLOAT32 3295 <tr><td>QASYMMS8 3296 <tr><td>QASYMMU8 3297 <tr><td>QSYMMS16 3298 </table> 3299<tr> 3300 <td>CpuAcc 3301 <td> 3302 <ul> 3303 <li>All 3304 </ul> 3305 <td> 3306 <table> 3307 <tr><th> 3308 <tr><td>All 3309 </table> 3310<tr> 3311 <td>GpuAcc 3312 <td> 3313 <ul> 3314 <li>All 3315 </ul> 3316 <td> 3317 <table> 3318 <tr><th> 3319 <tr><td>All 3320 </table> 3321<tr> 3322 <td rowspan="3">UnidirectionalSquenceLstmLayer 3323 <td rowspan="3" style="width:200px;"> Layer to perform unidirectional sequence LSTM operation. 3324 <td rowspan="3"> 3325 <ul> 3326 <li>ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_LSTM 3327 </ul> 3328 <td>CpuRef 3329 <td> 3330 <ul> 3331 <li>All 3332 </ul> 3333 <td> 3334 <table> 3335 <tr><th>Input Types 3336 <tr><td>FLOAT32 3337 </table> 3338 <table> 3339 <tr><th>Weight Types 3340 <tr><td>FLOAT32 3341 <tr><td>QASYMMS8 3342 </table> 3343 <td>CpuAcc 3344 <td> 3345 <ul> 3346 <li>All 3347 </ul> 3348 <td> 3349 <table> 3350 <tr><th>Input Types 3351 <tr><td>FLOAT32 3352 </table> 3353 <table> 3354 <tr><th>Weight Types 3355 <tr><td>FLOAT32 3356 </table> 3357 <td>GpuAcc 3358 <td> 3359 <ul> 3360 <li>All 3361 </ul> 3362 <td> 3363 <table> 3364 <tr><th>Input Types 3365 <tr><td>FLOAT32 3366 </table> 3367 <table> 3368 <tr><th>Weight Types 3369 <tr><td>FLOAT32 3370 </table> 3371<tr> 3372 <td rowspan="3">UnmapLayer 3373 <td rowspan="3" style="width:200px;"> Layer to perform unmap operation on tensor. 3374 <td rowspan="3"> 3375 <ul> 3376 <li>N/A 3377 </ul> 3378 <td>CpuRef 3379 <td> 3380 <ul> 3381 <li>All 3382 </ul> 3383 <td> 3384 <table> 3385 <tr><th> 3386 <tr><td>All 3387 </table> 3388<tr> 3389 <td>CpuAcc 3390 <td> 3391 <ul> 3392 <li>NHWC 3393 <li>NCHW 3394 </ul> 3395 <td> 3396 <table> 3397 <tr><th> 3398 <tr><td>All 3399 </table> 3400<tr> 3401 <td>GpuAcc 3402 <td> 3403 <ul> 3404 <li>NHWC 3405 <li>NCHW 3406 </ul> 3407 <td> 3408 <table> 3409 <tr><th> 3410 <tr><td>All 3411 </table> 3412</table> 3413 3414*/ 3415} // namespace