1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/bitfield.h>
8 #include <linux/netdevice.h>
9 #include <linux/if_vlan.h>
10 #include <linux/phylink.h>
11 #include <net/ip.h>
12
13 #define WX_NCSI_SUP 0x8000
14 #define WX_NCSI_MASK 0x8000
15 #define WX_WOL_SUP 0x4000
16 #define WX_WOL_MASK 0x4000
17
18 /* MSI-X capability fields masks */
19 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
20 #define WX_PCI_LINK_STATUS 0xB2
21
22 /**************** Global Registers ****************************/
23 /* chip control Registers */
24 #define WX_MIS_PWR 0x10000
25 #define WX_MIS_RST 0x1000C
26 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
27 #define WX_MIS_RST_SW_RST BIT(0)
28 #define WX_MIS_ST 0x10028
29 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
30 #define WX_MIS_SWSM 0x1002C
31 #define WX_MIS_SWSM_SMBI BIT(0)
32 #define WX_MIS_RST_ST 0x10030
33 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
34 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
35
36 /* FMGR Registers */
37 #define WX_SPI_CMD 0x10104
38 #define WX_SPI_CMD_READ_DWORD 0x1
39 #define WX_SPI_CLK_DIV 0x3
40 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
41 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
42 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
43 #define WX_SPI_DATA 0x10108
44 #define WX_SPI_DATA_BYPASS BIT(31)
45 #define WX_SPI_DATA_OP_DONE BIT(0)
46 #define WX_SPI_STATUS 0x1010C
47 #define WX_SPI_STATUS_OPDONE BIT(0)
48 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
49 #define WX_SPI_ILDR_STATUS 0x10120
50
51 /* Sensors for PVT(Process Voltage Temperature) */
52 #define WX_TS_EN 0x10304
53 #define WX_TS_EN_ENA BIT(0)
54 #define WX_TS_ALARM_THRE 0x1030C
55 #define WX_TS_DALARM_THRE 0x10310
56 #define WX_TS_INT_EN 0x10314
57 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
58 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
59 #define WX_TS_ALARM_ST 0x10318
60 #define WX_TS_ALARM_ST_DALARM BIT(1)
61 #define WX_TS_ALARM_ST_ALARM BIT(0)
62
63 /* statistic */
64 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
65 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
66 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
67 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
68 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
69 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
70 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
71 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
72 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
73 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
74 #define WX_MAC_LXONOFFRXC 0x11E0C
75
76 /*********************** Receive DMA registers **************************/
77 #define WX_RDM_DRP_PKT 0x12500
78 #define WX_RDM_PKT_CNT 0x12504
79 #define WX_RDM_BYTE_CNT_LSB 0x12508
80 #define WX_RDM_BMC2OS_CNT 0x12510
81
82 /************************* Port Registers ************************************/
83 /* port cfg Registers */
84 #define WX_CFG_PORT_CTL 0x14400
85 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
86 #define WX_CFG_PORT_CTL_QINQ BIT(2)
87 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
88 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
89 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
90
91
92 /* GPIO Registers */
93 #define WX_GPIO_DR 0x14800
94 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
95 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
96 #define WX_GPIO_DDR 0x14804
97 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
98 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
99 #define WX_GPIO_CTL 0x14808
100 #define WX_GPIO_INTEN 0x14830
101 #define WX_GPIO_INTEN_0 BIT(0)
102 #define WX_GPIO_INTEN_1 BIT(1)
103 #define WX_GPIO_INTMASK 0x14834
104 #define WX_GPIO_INTTYPE_LEVEL 0x14838
105 #define WX_GPIO_POLARITY 0x1483C
106 #define WX_GPIO_INTSTATUS 0x14844
107 #define WX_GPIO_EOI 0x1484C
108 #define WX_GPIO_EXT 0x14850
109
110 /*********************** Transmit DMA registers **************************/
111 /* transmit global control */
112 #define WX_TDM_CTL 0x18000
113 /* TDM CTL BIT */
114 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
115 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
116 #define WX_TDM_RP_IDX 0x1820C
117 #define WX_TDM_PKT_CNT 0x18308
118 #define WX_TDM_BYTE_CNT_LSB 0x1830C
119 #define WX_TDM_OS2BMC_CNT 0x18314
120 #define WX_TDM_RP_RATE 0x18404
121
122 /***************************** RDB registers *********************************/
123 /* receive packet buffer */
124 #define WX_RDB_PB_CTL 0x19000
125 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
126 #define WX_RDB_PB_CTL_DISABLED BIT(0)
127 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
128 #define WX_RDB_PB_SZ_SHIFT 10
129 /* statistic */
130 #define WX_RDB_PFCMACDAL 0x19210
131 #define WX_RDB_PFCMACDAH 0x19214
132 #define WX_RDB_LXOFFTXC 0x19218
133 #define WX_RDB_LXONTXC 0x1921C
134 /* Flow Control Registers */
135 #define WX_RDB_RFCV 0x19200
136 #define WX_RDB_RFCL 0x19220
137 #define WX_RDB_RFCL_XONE BIT(31)
138 #define WX_RDB_RFCH 0x19260
139 #define WX_RDB_RFCH_XOFFE BIT(31)
140 #define WX_RDB_RFCRT 0x192A0
141 #define WX_RDB_RFCC 0x192A4
142 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
143 /* ring assignment */
144 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
145 #define WX_RDB_PL_CFG_L4HDR BIT(1)
146 #define WX_RDB_PL_CFG_L3HDR BIT(2)
147 #define WX_RDB_PL_CFG_L2HDR BIT(3)
148 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
149 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
150 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
151 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
152 #define WX_RDB_RA_CTL 0x194F4
153 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
154 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
155 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
156 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
157 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
158 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
159 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
160 #define WX_RDB_FDIR_MATCH 0x19558
161 #define WX_RDB_FDIR_MISS 0x1955C
162
163 /******************************* PSR Registers *******************************/
164 /* psr control */
165 #define WX_PSR_CTL 0x15000
166 /* Header split receive */
167 #define WX_PSR_CTL_SW_EN BIT(18)
168 #define WX_PSR_CTL_RSC_ACK BIT(17)
169 #define WX_PSR_CTL_RSC_DIS BIT(16)
170 #define WX_PSR_CTL_PCSD BIT(13)
171 #define WX_PSR_CTL_IPPCSE BIT(12)
172 #define WX_PSR_CTL_BAM BIT(10)
173 #define WX_PSR_CTL_UPE BIT(9)
174 #define WX_PSR_CTL_MPE BIT(8)
175 #define WX_PSR_CTL_MFE BIT(7)
176 #define WX_PSR_CTL_MO_SHIFT 5
177 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
178 #define WX_PSR_CTL_TPE BIT(4)
179 #define WX_PSR_MAX_SZ 0x15020
180 #define WX_PSR_VLAN_CTL 0x15088
181 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
182 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
183 /* mcasst/ucast overflow tbl */
184 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
185 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
186
187 /* VM L2 contorl */
188 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
189 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
190 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
191 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
192 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
193 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
194 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
195 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
196
197 /* Management */
198 #define WX_PSR_MNG_FLEX_SEL 0x1582C
199 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
200 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
201 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
202 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
203 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
204 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
205 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
206
207 #define WX_PSR_WKUP_CTL 0x15B80
208 /* Wake Up Filter Control Bit */
209 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
210
211 /* vlan tbl */
212 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
213
214 /* mac switcher */
215 #define WX_PSR_MAC_SWC_AD_L 0x16200
216 #define WX_PSR_MAC_SWC_AD_H 0x16204
217 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
218 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
219 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
220 #define WX_PSR_MAC_SWC_VM_L 0x16208
221 #define WX_PSR_MAC_SWC_VM_H 0x1620C
222 #define WX_PSR_MAC_SWC_IDX 0x16210
223 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
224
225 /* vlan switch */
226 #define WX_PSR_VLAN_SWC 0x16220
227 #define WX_PSR_VLAN_SWC_VM_L 0x16224
228 #define WX_PSR_VLAN_SWC_VM_H 0x16228
229 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
230 /* VLAN pool filtering masks */
231 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
232 #define WX_PSR_VLAN_SWC_ENTRIES 64
233
234 /********************************* RSEC **************************************/
235 /* general rsec */
236 #define WX_RSC_CTL 0x17000
237 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
238 #define WX_RSC_CTL_CRC_STRIP BIT(2)
239 #define WX_RSC_CTL_RX_DIS BIT(1)
240 #define WX_RSC_ST 0x17004
241 #define WX_RSC_ST_RSEC_RDY BIT(0)
242
243 /****************************** TDB ******************************************/
244 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
245 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
246
247 /****************************** TSEC *****************************************/
248 /* Security Control Registers */
249 #define WX_TSC_CTL 0x1D000
250 #define WX_TSC_CTL_TX_DIS BIT(1)
251 #define WX_TSC_CTL_TSEC_DIS BIT(0)
252 #define WX_TSC_ST 0x1D004
253 #define WX_TSC_ST_SECTX_RDY BIT(0)
254 #define WX_TSC_BUF_AE 0x1D00C
255 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
256
257 /************************************** MNG ********************************/
258 #define WX_MNG_SWFW_SYNC 0x1E008
259 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
260 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
261 #define WX_MNG_MBOX 0x1E100
262 #define WX_MNG_MBOX_CTL 0x1E044
263 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
264 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
265 #define WX_MNG_BMC2OS_CNT 0x1E090
266 #define WX_MNG_OS2BMC_CNT 0x1E094
267
268 /************************************* ETH MAC *****************************/
269 #define WX_MAC_TX_CFG 0x11000
270 #define WX_MAC_TX_CFG_TE BIT(0)
271 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
272 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
273 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
274 #define WX_MAC_RX_CFG 0x11004
275 #define WX_MAC_RX_CFG_RE BIT(0)
276 #define WX_MAC_RX_CFG_JE BIT(8)
277 #define WX_MAC_PKT_FLT 0x11008
278 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
279 #define WX_MAC_WDG_TIMEOUT 0x1100C
280 #define WX_MAC_RX_FLOW_CTRL 0x11090
281 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
282 /* MDIO Registers */
283 #define WX_MSCA 0x11200
284 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
285 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
286 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
287 #define WX_MSCC 0x11204
288 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
289
290 enum WX_MSCA_CMD_value {
291 WX_MSCA_CMD_RSV = 0,
292 WX_MSCA_CMD_WRITE,
293 WX_MSCA_CMD_POST_READ,
294 WX_MSCA_CMD_READ,
295 };
296
297 #define WX_MSCC_SADDR BIT(18)
298 #define WX_MSCC_BUSY BIT(22)
299 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
300 #define WX_MDIO_CLAUSE_SELECT 0x11220
301 #define WX_MMC_CONTROL 0x11800
302 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
303
304 /********************************* BAR registers ***************************/
305 /* Interrupt Registers */
306 #define WX_BME_CTL 0x12020
307 #define WX_PX_MISC_IC 0x100
308 #define WX_PX_MISC_ICS 0x104
309 #define WX_PX_MISC_IEN 0x108
310 #define WX_PX_INTA 0x110
311 #define WX_PX_GPIE 0x118
312 #define WX_PX_GPIE_MODEL BIT(0)
313 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
314 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
315 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
316 #define WX_PX_ISB_ADDR_L 0x160
317 #define WX_PX_ISB_ADDR_H 0x164
318 #define WX_PX_TRANSACTION_PENDING 0x168
319 #define WX_PX_ITRSEL 0x180
320 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
321 #define WX_PX_ITR_CNT_WDIS BIT(31)
322 #define WX_PX_MISC_IVAR 0x4FC
323 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
324
325 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
326 #define WX_7K_ITR 595
327 #define WX_12K_ITR 336
328 #define WX_20K_ITR 200
329 #define WX_SP_MAX_EITR 0x00000FF8U
330 #define WX_EM_MAX_EITR 0x00007FFCU
331
332 /* transmit DMA Registers */
333 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
334 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
335 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
336 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
337 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
338 /* Transmit Config masks */
339 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
340 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
341 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
342 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
343 #define WX_PX_TR_CFG_THRE_SHIFT 8
344
345 /* Receive DMA Registers */
346 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
347 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
348 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
349 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
350 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
351 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
352 /* PX_RR_CFG bit definitions */
353 #define WX_PX_RR_CFG_VLAN BIT(31)
354 #define WX_PX_RR_CFG_DROP_EN BIT(30)
355 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
356 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
357 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
358 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
359 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
360 * + at bit 8 offset (<< 12)
361 * = (<< 6)
362 */
363 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
364 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
365 #define WX_PX_RR_CFG_RR_EN BIT(0)
366
367 /* Number of 80 microseconds we wait for PCI Express master disable */
368 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
369
370 /****************** Manageablility Host Interface defines ********************/
371 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
372 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
373
374 #define FW_READ_SHADOW_RAM_CMD 0x31
375 #define FW_READ_SHADOW_RAM_LEN 0x6
376 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
377 #define FW_NVM_DATA_OFFSET 3
378 #define FW_MAX_READ_BUFFER_SIZE 244
379 #define FW_RESET_CMD 0xDF
380 #define FW_RESET_LEN 0x2
381 #define FW_CEM_HDR_LEN 0x4
382 #define FW_CEM_CMD_RESERVED 0X0
383 #define FW_CEM_MAX_RETRIES 3
384 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
385
386 #define WX_SW_REGION_PTR 0x1C
387
388 #define WX_MAC_STATE_DEFAULT 0x1
389 #define WX_MAC_STATE_MODIFIED 0x2
390 #define WX_MAC_STATE_IN_USE 0x4
391
392 /* BitTimes (BT) conversion */
393 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
394 #define WX_B2BT(BT) ((BT) * 8)
395
396 /* Calculate Delay to respond to PFC */
397 #define WX_PFC_D 672
398 /* Calculate Cable Delay */
399 #define WX_CABLE_DC 5556 /* Delay Copper */
400 /* Calculate Delay incurred from higher layer */
401 #define WX_HD 6144
402
403 /* Calculate Interface Delay */
404 #define WX_PHY_D 12800
405 #define WX_MAC_D 4096
406 #define WX_XAUI_D (2 * 1024)
407 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
408 /* Calculate PCI Bus delay for low thresholds */
409 #define WX_PCI_DELAY 10000
410
411 /* Calculate delay value in bit times */
412 #define WX_DV(_max_frame_link, _max_frame_tc) \
413 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
414 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
415 2 * WX_B2BT(_max_frame_tc))
416
417 /* Calculate low threshold delay values */
418 #define WX_LOW_DV(_max_frame_tc) \
419 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
420
421 /* flow control */
422 #define WX_DEFAULT_FCPAUSE 0xFFFF
423
424 #define WX_MAX_RXD 8192
425 #define WX_MAX_TXD 8192
426 #define WX_MIN_RXD 128
427 #define WX_MIN_TXD 128
428
429 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
430 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
431 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
432
433 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
434 #define VMDQ_P(p) p
435
436 /* Supported Rx Buffer Sizes */
437 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
438 #define WX_RXBUFFER_2K 2048
439 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
440
441 #if MAX_SKB_FRAGS < 8
442 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
443 #else
444 #define WX_RX_BUFSZ WX_RXBUFFER_2K
445 #endif
446
447 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
448
449 #define WX_MAX_DATA_PER_TXD BIT(14)
450 /* Tx Descriptors needed, worst case */
451 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
452 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
453
454 #define WX_CFG_PORT_ST 0x14404
455
456 /******************* Receive Descriptor bit definitions **********************/
457 #define WX_RXD_STAT_DD BIT(0) /* Done */
458 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
459 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
460 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
461 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
462 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
463 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
464
465 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
466 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
467 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
468 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
469
470 /* RSS Hash results */
471 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
472 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
473 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
474 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
475 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
476 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
477 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
478
479 #define WX_RSS_L4_TYPES_MASK \
480 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
481 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
482 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
483 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
484 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
485 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
486 /* TUN */
487 #define WX_PTYPE_TUN_IPV4 0x80
488 #define WX_PTYPE_TUN_IPV6 0xC0
489
490 /* PKT for TUN */
491 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
492 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
493 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
494 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
495 /* PKT for !TUN */
496 #define WX_PTYPE_PKT_MAC 0x10
497 #define WX_PTYPE_PKT_IP 0x20
498
499 /* TYP for PKT=mac */
500 #define WX_PTYPE_TYP_MAC 0x01
501 /* TYP for PKT=ip */
502 #define WX_PTYPE_PKT_IPV6 0x08
503 #define WX_PTYPE_TYP_IPFRAG 0x01
504 #define WX_PTYPE_TYP_IP 0x02
505 #define WX_PTYPE_TYP_UDP 0x03
506 #define WX_PTYPE_TYP_TCP 0x04
507 #define WX_PTYPE_TYP_SCTP 0x05
508
509 /* Packet type non-ip values */
510 enum wx_l2_ptypes {
511 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
512 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
513
514 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
515 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
516 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
517 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
518 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
519 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
520 WX_PTYPE_TYP_IPFRAG),
521 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
522 WX_PTYPE_TYP_IP),
523 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
524 WX_PTYPE_TYP_UDP),
525 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
526 WX_PTYPE_TYP_TCP),
527 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
528 WX_PTYPE_TYP_SCTP),
529
530 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
531 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
532 };
533
534 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
535 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
536
537 #define WX_RXD_PKTTYPE(_rxd) \
538 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
539 /*********************** Transmit Descriptor Config Masks ****************/
540 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
541 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
542 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
543 #define WX_TXD_EOP BIT(24) /* End of Packet */
544 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
545 #define WX_TXD_RS BIT(27) /* Report Status */
546
547 /*********************** Adv Transmit Descriptor Config Masks ****************/
548 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
549 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
550 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
551 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
552 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
553 #define WX_TXD_CC BIT(7) /* Check Context */
554 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
555 #define WX_TXD_L4CS BIT(9)
556 #define WX_TXD_IIPCS BIT(10)
557 #define WX_TXD_EIPCS BIT(11)
558 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
559 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
560 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
561
562 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
563 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
564
565 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
566 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
567 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
568 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
569 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
570
571 enum wx_tx_flags {
572 /* cmd_type flags */
573 WX_TX_FLAGS_HW_VLAN = 0x01,
574 WX_TX_FLAGS_TSO = 0x02,
575 WX_TX_FLAGS_TSTAMP = 0x04,
576
577 /* olinfo flags */
578 WX_TX_FLAGS_CC = 0x08,
579 WX_TX_FLAGS_IPV4 = 0x10,
580 WX_TX_FLAGS_CSUM = 0x20,
581 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
582 WX_TX_FLAGS_LINKSEC = 0x200,
583 WX_TX_FLAGS_IPSEC = 0x400,
584
585 /* software defined flags */
586 WX_TX_FLAGS_SW_VLAN = 0x40,
587 };
588
589 /* VLAN info */
590 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
591 #define WX_TX_FLAGS_VLAN_SHIFT 16
592
593 /* wx_dec_ptype.mac: outer mac */
594 enum wx_dec_ptype_mac {
595 WX_DEC_PTYPE_MAC_IP = 0,
596 WX_DEC_PTYPE_MAC_L2 = 2,
597 WX_DEC_PTYPE_MAC_FCOE = 3,
598 };
599
600 /* wx_dec_ptype.[e]ip: outer&encaped ip */
601 #define WX_DEC_PTYPE_IP_FRAG 0x4
602 enum wx_dec_ptype_ip {
603 WX_DEC_PTYPE_IP_NONE = 0,
604 WX_DEC_PTYPE_IP_IPV4 = 1,
605 WX_DEC_PTYPE_IP_IPV6 = 2,
606 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
607 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
608 };
609
610 /* wx_dec_ptype.etype: encaped type */
611 enum wx_dec_ptype_etype {
612 WX_DEC_PTYPE_ETYPE_NONE = 0,
613 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
614 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
615 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
616 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
617 };
618
619 /* wx_dec_ptype.proto: payload proto */
620 enum wx_dec_ptype_prot {
621 WX_DEC_PTYPE_PROT_NONE = 0,
622 WX_DEC_PTYPE_PROT_UDP = 1,
623 WX_DEC_PTYPE_PROT_TCP = 2,
624 WX_DEC_PTYPE_PROT_SCTP = 3,
625 WX_DEC_PTYPE_PROT_ICMP = 4,
626 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
627 };
628
629 /* wx_dec_ptype.layer: payload layer */
630 enum wx_dec_ptype_layer {
631 WX_DEC_PTYPE_LAYER_NONE = 0,
632 WX_DEC_PTYPE_LAYER_PAY2 = 1,
633 WX_DEC_PTYPE_LAYER_PAY3 = 2,
634 WX_DEC_PTYPE_LAYER_PAY4 = 3,
635 };
636
637 struct wx_dec_ptype {
638 u32 known:1;
639 u32 mac:2; /* outer mac */
640 u32 ip:3; /* outer ip*/
641 u32 etype:3; /* encaped type */
642 u32 eip:3; /* encaped ip */
643 u32 prot:4; /* payload proto */
644 u32 layer:3; /* payload layer */
645 };
646
647 /* macro to make the table lines short */
648 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
649 {1, \
650 WX_DEC_PTYPE_MAC_##mac, /* mac */\
651 WX_DEC_PTYPE_IP_##ip, /* ip */ \
652 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
653 WX_DEC_PTYPE_IP_##eip, /* eip */\
654 WX_DEC_PTYPE_PROT_##proto, /* proto */\
655 WX_DEC_PTYPE_LAYER_##layer /* layer */}
656
657 /* Host Interface Command Structures */
658 struct wx_hic_hdr {
659 u8 cmd;
660 u8 buf_len;
661 union {
662 u8 cmd_resv;
663 u8 ret_status;
664 } cmd_or_resp;
665 u8 checksum;
666 };
667
668 struct wx_hic_hdr2_req {
669 u8 cmd;
670 u8 buf_lenh;
671 u8 buf_lenl;
672 u8 checksum;
673 };
674
675 struct wx_hic_hdr2_rsp {
676 u8 cmd;
677 u8 buf_lenl;
678 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
679 u8 checksum;
680 };
681
682 union wx_hic_hdr2 {
683 struct wx_hic_hdr2_req req;
684 struct wx_hic_hdr2_rsp rsp;
685 };
686
687 /* These need to be dword aligned */
688 struct wx_hic_read_shadow_ram {
689 union wx_hic_hdr2 hdr;
690 u32 address;
691 u16 length;
692 u16 pad2;
693 u16 data;
694 u16 pad3;
695 };
696
697 struct wx_hic_reset {
698 struct wx_hic_hdr hdr;
699 u16 lan_id;
700 u16 reset_type;
701 };
702
703 /* Bus parameters */
704 struct wx_bus_info {
705 u8 func;
706 u16 device;
707 };
708
709 struct wx_thermal_sensor_data {
710 s16 temp;
711 s16 alarm_thresh;
712 s16 dalarm_thresh;
713 };
714
715 enum wx_mac_type {
716 wx_mac_unknown = 0,
717 wx_mac_sp,
718 wx_mac_em
719 };
720
721 enum sp_media_type {
722 sp_media_unknown = 0,
723 sp_media_fiber,
724 sp_media_copper,
725 sp_media_backplane
726 };
727
728 enum em_mac_type {
729 em_mac_type_unknown = 0,
730 em_mac_type_mdi,
731 em_mac_type_rgmii
732 };
733
734 struct wx_mac_info {
735 enum wx_mac_type type;
736 bool set_lben;
737 u8 addr[ETH_ALEN];
738 u8 perm_addr[ETH_ALEN];
739 u32 mta_shadow[128];
740 s32 mc_filter_type;
741 u32 mcft_size;
742 u32 vft_shadow[128];
743 u32 vft_size;
744 u32 num_rar_entries;
745 u32 rx_pb_size;
746 u32 tx_pb_size;
747 u32 max_tx_queues;
748 u32 max_rx_queues;
749
750 u16 max_msix_vectors;
751 struct wx_thermal_sensor_data sensor;
752 };
753
754 enum wx_eeprom_type {
755 wx_eeprom_uninitialized = 0,
756 wx_eeprom_spi,
757 wx_flash,
758 wx_eeprom_none /* No NVM support */
759 };
760
761 struct wx_eeprom_info {
762 enum wx_eeprom_type type;
763 u32 semaphore_delay;
764 u16 word_size;
765 u16 sw_region_offset;
766 };
767
768 struct wx_addr_filter_info {
769 u32 num_mc_addrs;
770 u32 mta_in_use;
771 bool user_set_promisc;
772 };
773
774 struct wx_mac_addr {
775 u8 addr[ETH_ALEN];
776 u16 state; /* bitmask */
777 u64 pools;
778 };
779
780 enum wx_reset_type {
781 WX_LAN_RESET = 0,
782 WX_SW_RESET,
783 WX_GLOBAL_RESET
784 };
785
786 struct wx_cb {
787 dma_addr_t dma;
788 u16 append_cnt; /* number of skb's appended */
789 bool page_released;
790 bool dma_released;
791 };
792
793 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
794
795 /* Transmit Descriptor */
796 union wx_tx_desc {
797 struct {
798 __le64 buffer_addr; /* Address of descriptor's data buf */
799 __le32 cmd_type_len;
800 __le32 olinfo_status;
801 } read;
802 struct {
803 __le64 rsvd; /* Reserved */
804 __le32 nxtseq_seed;
805 __le32 status;
806 } wb;
807 };
808
809 /* Receive Descriptor */
810 union wx_rx_desc {
811 struct {
812 __le64 pkt_addr; /* Packet buffer address */
813 __le64 hdr_addr; /* Header buffer address */
814 } read;
815 struct {
816 struct {
817 union {
818 __le32 data;
819 struct {
820 __le16 pkt_info; /* RSS, Pkt type */
821 __le16 hdr_info; /* Splithdr, hdrlen */
822 } hs_rss;
823 } lo_dword;
824 union {
825 __le32 rss; /* RSS Hash */
826 struct {
827 __le16 ip_id; /* IP id */
828 __le16 csum; /* Packet Checksum */
829 } csum_ip;
830 } hi_dword;
831 } lower;
832 struct {
833 __le32 status_error; /* ext status/error */
834 __le16 length; /* Packet length */
835 __le16 vlan; /* VLAN tag */
836 } upper;
837 } wb; /* writeback */
838 };
839
840 struct wx_tx_context_desc {
841 __le32 vlan_macip_lens;
842 __le32 seqnum_seed;
843 __le32 type_tucmd_mlhl;
844 __le32 mss_l4len_idx;
845 };
846
847 /* if _flag is in _input, return _result */
848 #define WX_SET_FLAG(_input, _flag, _result) \
849 (((_flag) <= (_result)) ? \
850 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
851 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
852
853 #define WX_RX_DESC(R, i) \
854 (&(((union wx_rx_desc *)((R)->desc))[i]))
855 #define WX_TX_DESC(R, i) \
856 (&(((union wx_tx_desc *)((R)->desc))[i]))
857 #define WX_TX_CTXTDESC(R, i) \
858 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
859
860 /* wrapper around a pointer to a socket buffer,
861 * so a DMA handle can be stored along with the buffer
862 */
863 struct wx_tx_buffer {
864 union wx_tx_desc *next_to_watch;
865 struct sk_buff *skb;
866 unsigned int bytecount;
867 unsigned short gso_segs;
868 DEFINE_DMA_UNMAP_ADDR(dma);
869 DEFINE_DMA_UNMAP_LEN(len);
870 __be16 protocol;
871 u32 tx_flags;
872 };
873
874 struct wx_rx_buffer {
875 struct sk_buff *skb;
876 dma_addr_t dma;
877 dma_addr_t page_dma;
878 struct page *page;
879 unsigned int page_offset;
880 };
881
882 struct wx_queue_stats {
883 u64 packets;
884 u64 bytes;
885 };
886
887 struct wx_tx_queue_stats {
888 u64 restart_queue;
889 u64 tx_busy;
890 };
891
892 struct wx_rx_queue_stats {
893 u64 non_eop_descs;
894 u64 csum_good_cnt;
895 u64 csum_err;
896 u64 alloc_rx_buff_failed;
897 };
898
899 /* iterator for handling rings in ring container */
900 #define wx_for_each_ring(posm, headm) \
901 for (posm = (headm).ring; posm; posm = posm->next)
902
903 struct wx_ring_container {
904 struct wx_ring *ring; /* pointer to linked list of rings */
905 unsigned int total_bytes; /* total bytes processed this int */
906 unsigned int total_packets; /* total packets processed this int */
907 u8 count; /* total number of rings in vector */
908 u8 itr; /* current ITR setting for ring */
909 };
910 struct wx_ring {
911 struct wx_ring *next; /* pointer to next ring in q_vector */
912 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
913 struct net_device *netdev; /* netdev ring belongs to */
914 struct device *dev; /* device for DMA mapping */
915 struct page_pool *page_pool;
916 void *desc; /* descriptor ring memory */
917 union {
918 struct wx_tx_buffer *tx_buffer_info;
919 struct wx_rx_buffer *rx_buffer_info;
920 };
921 u8 __iomem *tail;
922 dma_addr_t dma; /* phys. address of descriptor ring */
923 unsigned int size; /* length in bytes */
924
925 u16 count; /* amount of descriptors */
926
927 u8 queue_index; /* needed for multiqueue queue management */
928 u8 reg_idx; /* holds the special value that gets
929 * the hardware register offset
930 * associated with this ring, which is
931 * different for DCB and RSS modes
932 */
933 u16 next_to_use;
934 u16 next_to_clean;
935 union {
936 u16 next_to_alloc;
937 struct {
938 u8 atr_sample_rate;
939 u8 atr_count;
940 };
941 };
942
943 struct wx_queue_stats stats;
944 struct u64_stats_sync syncp;
945 union {
946 struct wx_tx_queue_stats tx_stats;
947 struct wx_rx_queue_stats rx_stats;
948 };
949 } ____cacheline_internodealigned_in_smp;
950
951 struct wx_q_vector {
952 struct wx *wx;
953 int cpu; /* CPU for DCA */
954 int numa_node;
955 u16 v_idx; /* index of q_vector within array, also used for
956 * finding the bit in EICR and friends that
957 * represents the vector for this ring
958 */
959 u16 itr; /* Interrupt throttle rate written to EITR */
960 struct wx_ring_container rx, tx;
961 struct napi_struct napi;
962 struct rcu_head rcu; /* to avoid race with update stats on free */
963
964 char name[IFNAMSIZ + 17];
965
966 /* for dynamic allocation of rings associated with this q_vector */
967 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
968 };
969
970 struct wx_ring_feature {
971 u16 limit; /* upper limit on feature indices */
972 u16 indices; /* current value of indices */
973 u16 mask; /* Mask used for feature to ring mapping */
974 u16 offset; /* offset to start of feature */
975 };
976
977 enum wx_ring_f_enum {
978 RING_F_NONE = 0,
979 RING_F_RSS,
980 RING_F_FDIR,
981 RING_F_ARRAY_SIZE /* must be last in enum set */
982 };
983
984 enum wx_isb_idx {
985 WX_ISB_HEADER,
986 WX_ISB_MISC,
987 WX_ISB_VEC0,
988 WX_ISB_VEC1,
989 WX_ISB_MAX
990 };
991
992 struct wx_fc_info {
993 u32 high_water; /* Flow Ctrl High-water */
994 u32 low_water; /* Flow Ctrl Low-water */
995 };
996
997 /* Statistics counters collected by the MAC */
998 struct wx_hw_stats {
999 u64 gprc;
1000 u64 gptc;
1001 u64 gorc;
1002 u64 gotc;
1003 u64 tpr;
1004 u64 tpt;
1005 u64 bprc;
1006 u64 bptc;
1007 u64 mprc;
1008 u64 mptc;
1009 u64 roc;
1010 u64 ruc;
1011 u64 lxonoffrxc;
1012 u64 lxontxc;
1013 u64 lxofftxc;
1014 u64 o2bgptc;
1015 u64 b2ospc;
1016 u64 o2bspc;
1017 u64 b2ogprc;
1018 u64 rdmdrop;
1019 u64 crcerrs;
1020 u64 rlec;
1021 u64 qmprc;
1022 u64 fdirmatch;
1023 u64 fdirmiss;
1024 };
1025
1026 enum wx_state {
1027 WX_STATE_RESETTING,
1028 WX_STATE_NBITS, /* must be last */
1029 };
1030
1031 enum wx_pf_flags {
1032 WX_FLAG_FDIR_CAPABLE,
1033 WX_FLAG_FDIR_HASH,
1034 WX_FLAG_FDIR_PERFECT,
1035 WX_PF_FLAGS_NBITS /* must be last */
1036 };
1037
1038 struct wx {
1039 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1040 DECLARE_BITMAP(state, WX_STATE_NBITS);
1041 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1042
1043 void *priv;
1044 u8 __iomem *hw_addr;
1045 struct pci_dev *pdev;
1046 struct net_device *netdev;
1047 struct wx_bus_info bus;
1048 struct wx_mac_info mac;
1049 enum em_mac_type mac_type;
1050 enum sp_media_type media_type;
1051 struct wx_eeprom_info eeprom;
1052 struct wx_addr_filter_info addr_ctrl;
1053 struct wx_fc_info fc;
1054 struct wx_mac_addr *mac_table;
1055 u16 device_id;
1056 u16 vendor_id;
1057 u16 subsystem_device_id;
1058 u16 subsystem_vendor_id;
1059 u8 revision_id;
1060 u16 oem_ssid;
1061 u16 oem_svid;
1062 u16 msg_enable;
1063 bool adapter_stopped;
1064 u16 tpid[8];
1065 char eeprom_id[32];
1066 char *driver_name;
1067 enum wx_reset_type reset_type;
1068
1069 /* PHY stuff */
1070 unsigned int link;
1071 int speed;
1072 int duplex;
1073 struct phy_device *phydev;
1074 struct phylink *phylink;
1075 struct phylink_config phylink_config;
1076
1077 bool wol_hw_supported;
1078 bool ncsi_enabled;
1079 bool gpio_ctrl;
1080 raw_spinlock_t gpio_lock;
1081
1082 /* Tx fast path data */
1083 int num_tx_queues;
1084 u16 tx_itr_setting;
1085 u16 tx_work_limit;
1086
1087 /* Rx fast path data */
1088 int num_rx_queues;
1089 u16 rx_itr_setting;
1090 u16 rx_work_limit;
1091
1092 int num_q_vectors; /* current number of q_vectors for device */
1093 int max_q_vectors; /* upper limit of q_vectors for device */
1094
1095 u32 tx_ring_count;
1096 u32 rx_ring_count;
1097
1098 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1099 struct wx_ring *rx_ring[64];
1100 struct wx_q_vector *q_vector[64];
1101
1102 unsigned int queues_per_pool;
1103 struct msix_entry *msix_q_entries;
1104 struct msix_entry *msix_entry;
1105 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1106
1107 /* misc interrupt status block */
1108 dma_addr_t isb_dma;
1109 u32 *isb_mem;
1110 u32 isb_tag[WX_ISB_MAX];
1111 bool misc_irq_domain;
1112
1113 #define WX_MAX_RETA_ENTRIES 128
1114 #define WX_RSS_INDIR_TBL_MAX 64
1115 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1116 bool rss_enabled;
1117 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1118 u32 *rss_key;
1119 u32 wol;
1120
1121 u16 bd_number;
1122
1123 struct wx_hw_stats stats;
1124 u64 tx_busy;
1125 u64 non_eop_descs;
1126 u64 restart_queue;
1127 u64 hw_csum_rx_good;
1128 u64 hw_csum_rx_error;
1129 u64 alloc_rx_buff_failed;
1130
1131 u32 atr_sample_rate;
1132 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1133 void (*configure_fdir)(struct wx *wx);
1134 void (*do_reset)(struct net_device *netdev);
1135 };
1136
1137 #define WX_INTR_ALL (~0ULL)
1138 #define WX_INTR_Q(i) BIT((i) + 1)
1139
1140 /* register operations */
1141 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1142 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1143 #define rd32a(a, reg, offset) ( \
1144 rd32((a), (reg) + ((offset) << 2)))
1145 #define wr32a(a, reg, off, val) \
1146 wr32((a), (reg) + ((off) << 2), (val))
1147
1148 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1149 rd32m(struct wx *wx, u32 reg, u32 mask)
1150 {
1151 u32 val;
1152
1153 val = rd32(wx, reg);
1154 return val & mask;
1155 }
1156
1157 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1158 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1159 {
1160 u32 val;
1161
1162 val = rd32(wx, reg);
1163 val = ((val & ~mask) | (field & mask));
1164
1165 wr32(wx, reg, val);
1166 }
1167
1168 static inline u64
rd64(struct wx * wx,u32 reg)1169 rd64(struct wx *wx, u32 reg)
1170 {
1171 u64 lsb, msb;
1172
1173 lsb = rd32(wx, reg);
1174 msb = rd32(wx, reg + 4);
1175
1176 return (lsb | msb << 32);
1177 }
1178
1179 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1180 * flushing memory, here use readl() to flush PCI read and write.
1181 */
1182 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1183
1184 #define wx_err(wx, fmt, arg...) \
1185 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1186
1187 #define wx_dbg(wx, fmt, arg...) \
1188 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1189
phylink_to_wx(struct phylink_config * config)1190 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1191 {
1192 return container_of(config, struct wx, phylink_config);
1193 }
1194
wx_set_state_reset(struct wx * wx)1195 static inline int wx_set_state_reset(struct wx *wx)
1196 {
1197 u8 timeout = 50;
1198
1199 while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1200 timeout--;
1201 if (!timeout)
1202 return -EBUSY;
1203
1204 usleep_range(1000, 2000);
1205 }
1206
1207 return 0;
1208 }
1209
1210 #endif /* _WX_TYPE_H_ */
1211