1 /*============================================================================== 2 Copyright(c) 2017 Intel Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files(the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and / or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included 12 in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 OTHER DEALINGS IN THE SOFTWARE. 21 ============================================================================*/ 22 #pragma once 23 24 typedef enum GMM_FLATCCS_FORMAT_ENUM 25 { 26 GMM_FLATCCS_FORMAT_R16S = 0, 27 GMM_FLATCCS_FORMAT_R16U = GMM_FLATCCS_FORMAT_R16S, 28 GMM_FLATCCS_FORMAT_RG16F = GMM_FLATCCS_FORMAT_R16S, 29 GMM_FLATCCS_FORMAT_RG16U = GMM_FLATCCS_FORMAT_R16S, 30 GMM_FLATCCS_FORMAT_RG16S = GMM_FLATCCS_FORMAT_R16S, 31 GMM_FLATCCS_FORMAT_RGBA16S = GMM_FLATCCS_FORMAT_R16S, 32 GMM_FLATCCS_FORMAT_RGBA16U = GMM_FLATCCS_FORMAT_R16S, 33 GMM_FLATCCS_FORMAT_RGBA16F = GMM_FLATCCS_FORMAT_R16S, 34 35 GMM_FLATCCS_MIN_RC_FORMAT = GMM_FLATCCS_FORMAT_R16S, 36 37 GMM_FLATCCS_FORMAT_R32F, 38 GMM_FLATCCS_FORMAT_R32S = GMM_FLATCCS_FORMAT_R32F, 39 GMM_FLATCCS_FORMAT_R32U = GMM_FLATCCS_FORMAT_R32F, 40 GMM_FLATCCS_FORMAT_RG32F = GMM_FLATCCS_FORMAT_R32F, 41 GMM_FLATCCS_FORMAT_RG32S = GMM_FLATCCS_FORMAT_R32F, 42 GMM_FLATCCS_FORMAT_RG32U = GMM_FLATCCS_FORMAT_R32F, 43 GMM_FLATCCS_FORMAT_RGBA32F = GMM_FLATCCS_FORMAT_R32F, 44 GMM_FLATCCS_FORMAT_RGBA32S = GMM_FLATCCS_FORMAT_R32F, 45 GMM_FLATCCS_FORMAT_RGBA32U = GMM_FLATCCS_FORMAT_R32F, 46 47 GMM_FLATCCS_FORMAT_RGB5A1, 48 GMM_FLATCCS_FORMAT_RGBA4 = GMM_FLATCCS_FORMAT_RGB5A1, 49 GMM_FLATCCS_FORMAT_B5G6R5 = GMM_FLATCCS_FORMAT_RGB5A1, 50 GMM_FLATCCS_FORMAT_R8S = GMM_FLATCCS_FORMAT_RGB5A1, 51 GMM_FLATCCS_FORMAT_R8U = GMM_FLATCCS_FORMAT_RGB5A1, 52 GMM_FLATCCS_FORMAT_RG8S = GMM_FLATCCS_FORMAT_RGB5A1, 53 GMM_FLATCCS_FORMAT_RG8U = GMM_FLATCCS_FORMAT_RGB5A1, 54 GMM_FLATCCS_FORMAT_RGBA8S = GMM_FLATCCS_FORMAT_RGB5A1, 55 GMM_FLATCCS_FORMAT_RGBA8U = GMM_FLATCCS_FORMAT_RGB5A1, 56 GMM_FLATCCS_FORMAT_ML8 = GMM_FLATCCS_FORMAT_RGB5A1, 57 58 GMM_FLATCCS_FORMAT_RGB10A2, 59 GMM_FLATCCS_FORMAT_RG11B10, 60 61 GMM_FLATCCS_FORMAT_R32F1, 62 GMM_FLATCCS_FORMAT_R32S1 = GMM_FLATCCS_FORMAT_R32F1, 63 GMM_FLATCCS_FORMAT_R32U1 = GMM_FLATCCS_FORMAT_R32F1, 64 GMM_FLATCCS_FORMAT_D32U = GMM_FLATCCS_FORMAT_R32F1, 65 66 GMM_FLATCCS_FORMAT_R16F1, 67 GMM_FLATCCS_FORMAT_R16S1 = GMM_FLATCCS_FORMAT_R16F1, 68 GMM_FLATCCS_FORMAT_R16U1 = GMM_FLATCCS_FORMAT_R16F1, 69 70 GMM_FLATCCS_FORMAT_R8S1, 71 GMM_FLATCCS_FORMAT_R8U1 = GMM_FLATCCS_FORMAT_R8S1, 72 73 GMM_FLATCCS_MAX_RC_FORMAT = GMM_FLATCCS_FORMAT_R8U1, 74 75 GMM_FLATCCS_MIN_MC_FORMAT = 0x21, //(0x1 <<5) ie Msb-5th bit turned on to identify MC encoding, to drop before SurfaceState usage 76 GMM_FLATCCS_FORMAT_RGBA16_MEDIA = GMM_FLATCCS_MIN_MC_FORMAT, 77 GMM_FLATCCS_FORMAT_Y210, 78 GMM_FLATCCS_FORMAT_YUY2, 79 GMM_FLATCCS_FORMAT_Y410, 80 GMM_FLATCCS_FORMAT_Y216, 81 GMM_FLATCCS_FORMAT_Y416, 82 GMM_FLATCCS_FORMAT_P010, 83 GMM_FLATCCS_FORMAT_P010_L = GMM_FLATCCS_FORMAT_P010, //MC 7h 84 GMM_FLATCCS_FORMAT_P010_C = GMM_FLATCCS_FORMAT_P010, //MC 7h 85 GMM_FLATCCS_FORMAT_P016, 86 GMM_FLATCCS_FORMAT_P016_L = GMM_FLATCCS_FORMAT_P016, //MC 8h 87 GMM_FLATCCS_FORMAT_P016_C = GMM_FLATCCS_FORMAT_P016, //MC 8h 88 GMM_FLATCCS_FORMAT_AYUV, 89 GMM_FLATCCS_FORMAT_ARGB8b, 90 GMM_FLATCCS_FORMAT_SWAPY, 91 GMM_FLATCCS_FORMAT_SWAPUV, 92 GMM_FLATCCS_FORMAT_SWAPUVY, 93 GMM_FLATCCS_FORMAT_RGB10b, 94 GMM_FLATCCS_FORMAT_NV12, 95 GMM_FLATCCS_FORMAT_NV12_L = GMM_FLATCCS_FORMAT_NV12, 96 GMM_FLATCCS_FORMAT_NV12_C = GMM_FLATCCS_FORMAT_NV12, 97 98 GMM_FLATCCS_FORMAT_YCRCB_SWAPUV = GMM_FLATCCS_FORMAT_SWAPUV, 99 GMM_FLATCCS_FORMAT_YCRCB_SWAPUVY = GMM_FLATCCS_FORMAT_SWAPUVY, 100 GMM_FLATCCS_FORMAT_YCRCB_SWAPY = GMM_FLATCCS_FORMAT_SWAPY, 101 102 GMM_FLATCCS_MAX_MC_FORMAT = GMM_FLATCCS_FORMAT_NV12, //should always be equal to last format encoding 103 104 GMM_FLATCCS_FORMAT_INVALID, //equal to last valid encoding plus one 105 } GMM_FLATCCS_FORMAT; 106 107 typedef enum GMM_XE2_UNIFIED_COMP_FORMAT_ENUM 108 { 109 GMM_XE2_UNIFIED_COMP_FORMAT_R8 = 0, //0h � bpc8 �R� 110 GMM_XE2_UNIFIED_COMP_MIN_FORMAT = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 111 GMM_XE2_UNIFIED_COMP_FORMAT_NV12_L = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 112 GMM_XE2_UNIFIED_COMP_FORMAT_D32U = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 113 GMM_XE2_UNIFIED_COMP_FORMAT_R8U = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 114 GMM_XE2_UNIFIED_COMP_FORMAT_R8S = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 115 GMM_XE2_UNIFIED_COMP_FORMAT_R8U1 = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 116 GMM_XE2_UNIFIED_COMP_FORMAT_R8S1 = GMM_XE2_UNIFIED_COMP_FORMAT_R8, 117 118 GMM_XE2_UNIFIED_COMP_FORMAT_RG8, //1h � bpc8 �RG� 119 GMM_XE2_UNIFIED_COMP_FORMAT_RGB5A1 = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 120 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA4 = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 121 GMM_XE2_UNIFIED_COMP_FORMAT_B5G6R5 = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 122 GMM_XE2_UNIFIED_COMP_FORMAT_NV12_C = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 123 GMM_XE2_UNIFIED_COMP_FORMAT_RG8U = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 124 GMM_XE2_UNIFIED_COMP_FORMAT_RG8S = GMM_XE2_UNIFIED_COMP_FORMAT_RG8, 125 126 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, // 2h � bpc8 �RGBA� 127 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8U = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, 128 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8S = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, 129 GMM_XE2_UNIFIED_COMP_FORMAT_YUY2 = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, 130 GMM_XE2_UNIFIED_COMP_FORMAT_AYUV = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, 131 GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA8, 132 GMM_XE2_UNIFIED_COMP_FORMAT_SWAPY = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 133 GMM_XE2_UNIFIED_COMP_FORMAT_SWAPUV = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 134 GMM_XE2_UNIFIED_COMP_FORMAT_SWAPUVY = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 135 GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB_SWAPUV = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 136 GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB_SWAPUVY = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 137 GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB_SWAPY = GMM_XE2_UNIFIED_COMP_FORMAT_YCRCB, 138 139 GMM_XE2_UNIFIED_COMP_FORMAT_RGB10A2, // 3h � 3bpc10_1bpc2 �RGBA10A2� 140 GMM_XE2_UNIFIED_COMP_FORMAT_Y410 = GMM_XE2_UNIFIED_COMP_FORMAT_RGB10A2, 141 142 GMM_XE2_UNIFIED_COMP_FORMAT_RG11B10, // 4h - 2bpc11_1bpc10 �RG11B10� 143 144 GMM_XE2_UNIFIED_COMP_FORMAT_R16, // 5h - bpc16 �R� 145 GMM_XE2_UNIFIED_COMP_FORMAT_R16U = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 146 GMM_XE2_UNIFIED_COMP_FORMAT_R16S = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 147 GMM_XE2_UNIFIED_COMP_FORMAT_R16F1 = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 148 GMM_XE2_UNIFIED_COMP_FORMAT_R16U1 = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 149 GMM_XE2_UNIFIED_COMP_FORMAT_R16S1 = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 150 GMM_XE2_UNIFIED_COMP_FORMAT_P010_L = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 151 GMM_XE2_UNIFIED_COMP_FORMAT_P016_L = GMM_XE2_UNIFIED_COMP_FORMAT_R16, 152 153 GMM_XE2_UNIFIED_COMP_FORMAT_RG16, // 6h � bpc16 �RG� 154 GMM_XE2_UNIFIED_COMP_FORMAT_RG16U = GMM_XE2_UNIFIED_COMP_FORMAT_RG16, 155 GMM_XE2_UNIFIED_COMP_FORMAT_RG16F = GMM_XE2_UNIFIED_COMP_FORMAT_RG16, 156 GMM_XE2_UNIFIED_COMP_FORMAT_RG16S = GMM_XE2_UNIFIED_COMP_FORMAT_RG16, 157 GMM_XE2_UNIFIED_COMP_FORMAT_P010_C = GMM_XE2_UNIFIED_COMP_FORMAT_RG16, 158 GMM_XE2_UNIFIED_COMP_FORMAT_P016_C = GMM_XE2_UNIFIED_COMP_FORMAT_RG16, 159 160 161 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16, // 7h - bpc16 �RGBA� 162 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16U = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16, 163 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16F = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16, 164 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16S = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA16, 165 166 GMM_XE2_UNIFIED_COMP_FORMAT_R32, // 8h - bpc32 �R� 167 GMM_XE2_UNIFIED_COMP_FORMAT_R32U = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 168 GMM_XE2_UNIFIED_COMP_FORMAT_R32F = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 169 GMM_XE2_UNIFIED_COMP_FORMAT_R32S = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 170 GMM_XE2_UNIFIED_COMP_FORMAT_R32U1 = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 171 GMM_XE2_UNIFIED_COMP_FORMAT_R32F1 = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 172 GMM_XE2_UNIFIED_COMP_FORMAT_R32S1 = GMM_XE2_UNIFIED_COMP_FORMAT_R32, 173 174 GMM_XE2_UNIFIED_COMP_FORMAT_RG32, // 9h - bpc32 �RG� 175 GMM_XE2_UNIFIED_COMP_FORMAT_RG32U = GMM_XE2_UNIFIED_COMP_FORMAT_RG32, 176 GMM_XE2_UNIFIED_COMP_FORMAT_RG32F = GMM_XE2_UNIFIED_COMP_FORMAT_RG32, 177 GMM_XE2_UNIFIED_COMP_FORMAT_RG32S = GMM_XE2_UNIFIED_COMP_FORMAT_RG32, 178 179 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32, // 10h - bpc32 �RGBA� 180 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32U = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32, 181 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32F = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32, 182 GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32S = GMM_XE2_UNIFIED_COMP_FORMAT_RGBA32, 183 184 GMM_XE2_UNIFIED_COMP_FORMAT_Y210, // 11h � packed YUV (Y210, Y416, Y216) 185 GMM_XE2_UNIFIED_COMP_FORMAT_Y216 = GMM_XE2_UNIFIED_COMP_FORMAT_Y210, 186 GMM_XE2_UNIFIED_COMP_FORMAT_Y416 = GMM_XE2_UNIFIED_COMP_FORMAT_Y210, 187 188 GMM_XE2_UNIFIED_COMP_FORMAT_RSVD1, // 12h � Unused 189 190 GMM_XE2_UNIFIED_COMP_FORMAT_HW_RSVD, // 13h � HW Stateless from MMIO or Uncompressed 191 192 GMM_XE2_UNIFIED_COMP_FORMAT_RSVD2_, // 13h � Stateless MMIO CMF? 193 194 GMM_XE2_UNIFIED_COMP_FORMAT_ML8 = 0xF, // 15h � ML and Lossy-Compressed textures 195 GMM_XE2_UNIFIED_COMP_MAX_FORMAT = GMM_XE2_UNIFIED_COMP_FORMAT_ML8, 196 GMM_XE2_UNIFIED_COMP_FORMAT_INVALID, //equal to last valid encoding plus one 197 } GMM_XE2_UNIFIED_COMP_FORMAT; 198 199 200 typedef enum GMM_UNIFIED_COMP_FORMAT_ENUM 201 { 202 GMM_UNIFIED_COMP_FORMAT_RGBA32F = 0, //0h - bpc32 RGBA F/S 203 GMM_UNIFIED_COMP_FORMAT_RGBA32S = GMM_UNIFIED_COMP_FORMAT_RGBA32F, 204 205 GMM_UNIFIED_COMP_MIN_RC_FORMAT = GMM_UNIFIED_COMP_FORMAT_RGBA32F, 206 207 GMM_UNIFIED_COMP_FORMAT_RGBA32U, //1h - bpc32 RGBA U 208 209 GMM_UNIFIED_COMP_FORMAT_RG32F, // 2h - bpc32 RG F/S 210 GMM_UNIFIED_COMP_FORMAT_RG32S = GMM_UNIFIED_COMP_FORMAT_RG32F, 211 212 GMM_UNIFIED_COMP_FORMAT_RG32U, // 3h - bpc32 RG U 213 214 GMM_UNIFIED_COMP_FORMAT_RGBA16U, // 4h - bpc16 RGBA U 215 216 GMM_UNIFIED_COMP_FORMAT_RGBA16F, // 5h - bpc16 RGBA F/S 217 GMM_UNIFIED_COMP_FORMAT_RGBA16S = GMM_UNIFIED_COMP_FORMAT_RGBA16F, 218 219 GMM_UNIFIED_COMP_FORMAT_RG16U, // 6h - bpc16 RG U 220 221 GMM_UNIFIED_COMP_FORMAT_RG16F, // 7h - bpc16 RG F/S 222 GMM_UNIFIED_COMP_FORMAT_RG16S = GMM_UNIFIED_COMP_FORMAT_RG16F, 223 224 GMM_UNIFIED_COMP_FORMAT_RGBA8U, // 8h - bpc8 RGBA U 225 GMM_UNIFIED_COMP_FORMAT_RGBA8S, // 9h - bpc8 RGBA S 226 227 GMM_UNIFIED_COMP_FORMAT_RGB5A1, // Ah - bpc8 228 GMM_UNIFIED_COMP_FORMAT_RGBA4 = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 229 GMM_UNIFIED_COMP_FORMAT_B5G6R5 = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 230 GMM_UNIFIED_COMP_FORMAT_RG8U = GMM_UNIFIED_COMP_FORMAT_RGB5A1, 231 232 GMM_UNIFIED_COMP_FORMAT_RG8S, // Bh - bpc8 233 GMM_UNIFIED_COMP_FORMAT_RGB10A2, // Ch - bpc8 234 GMM_UNIFIED_COMP_FORMAT_RG11B10, // Dh - bpc8 235 236 GMM_UNIFIED_COMP_FORMAT_R32F = 0x10, // 10h - bpc32 R F/S 237 GMM_UNIFIED_COMP_FORMAT_R32F1 = GMM_UNIFIED_COMP_FORMAT_R32F, 238 GMM_UNIFIED_COMP_FORMAT_R32S = GMM_UNIFIED_COMP_FORMAT_R32F, 239 GMM_UNIFIED_COMP_FORMAT_R32S1 = GMM_UNIFIED_COMP_FORMAT_R32F, 240 241 GMM_UNIFIED_COMP_FORMAT_R32U, // 11h - bpc32 R U 242 GMM_UNIFIED_COMP_FORMAT_R32U1 = GMM_UNIFIED_COMP_FORMAT_R32U, 243 GMM_UNIFIED_COMP_FORMAT_D32U = GMM_UNIFIED_COMP_FORMAT_R32U, 244 245 GMM_UNIFIED_COMP_FORMAT_R16U = 0x14, // 14h - bpc16 R U 246 GMM_UNIFIED_COMP_FORMAT_R16U1 = GMM_UNIFIED_COMP_FORMAT_R16U, // 14h - bpc16 R U 247 248 GMM_UNIFIED_COMP_FORMAT_R16F, // 15h - bpc16 R F/S 249 GMM_UNIFIED_COMP_FORMAT_R16F1 = GMM_UNIFIED_COMP_FORMAT_R16F, 250 GMM_UNIFIED_COMP_FORMAT_R16S = GMM_UNIFIED_COMP_FORMAT_R16F, 251 GMM_UNIFIED_COMP_FORMAT_R16S1 = GMM_UNIFIED_COMP_FORMAT_R16F, 252 253 GMM_UNIFIED_COMP_FORMAT_R8U = 0x18, // 18h - bpc8 R U 254 GMM_UNIFIED_COMP_FORMAT_R8U1 = GMM_UNIFIED_COMP_FORMAT_R8U, 255 256 GMM_UNIFIED_COMP_FORMAT_R8S, // 19h - bpc8 R S 257 GMM_UNIFIED_COMP_FORMAT_R8S1 = GMM_UNIFIED_COMP_FORMAT_R8S, 258 GMM_UNIFIED_COMP_FORMAT_ML8 = 0x1F, 259 260 GMM_UNIFIED_COMP_MAX_RC_FORMAT = GMM_UNIFIED_COMP_FORMAT_ML8, 261 262 GMM_UNIFIED_COMP_MIN_MC_FORMAT = 0x21, //(0x1 <<5) ie Msb-5th bit turned on to identify MC encoding, to drop before SurfaceState usage 263 GMM_UNIFIED_COMP_FORMAT_RGBA16_MEDIA = GMM_UNIFIED_COMP_MIN_MC_FORMAT, //MC 1h 264 GMM_UNIFIED_COMP_FORMAT_Y210, //MC 2h 265 GMM_UNIFIED_COMP_FORMAT_YUY2, //MC 3h 266 GMM_UNIFIED_COMP_FORMAT_Y410, //MC 4h 267 GMM_UNIFIED_COMP_FORMAT_Y216, //MC 5h 268 GMM_UNIFIED_COMP_FORMAT_Y416, //MC 6h 269 GMM_UNIFIED_COMP_FORMAT_P010, //MC 7h 270 GMM_UNIFIED_COMP_FORMAT_P010_L = GMM_UNIFIED_COMP_FORMAT_P010, 271 GMM_UNIFIED_COMP_FORMAT_P010_C = GMM_UNIFIED_COMP_FORMAT_P010, 272 GMM_UNIFIED_COMP_FORMAT_P016, //MC 8h 273 GMM_UNIFIED_COMP_FORMAT_P016_L = GMM_UNIFIED_COMP_FORMAT_P016, 274 GMM_UNIFIED_COMP_FORMAT_P016_C = GMM_UNIFIED_COMP_FORMAT_P016, 275 GMM_UNIFIED_COMP_FORMAT_AYUV, //MC 9h 276 GMM_UNIFIED_COMP_FORMAT_ARGB8b, //MC Ah 277 GMM_UNIFIED_COMP_FORMAT_SWAPY, //MC Bh 278 GMM_UNIFIED_COMP_FORMAT_SWAPUV, //MC Ch 279 GMM_UNIFIED_COMP_FORMAT_SWAPUVY, //MC Dh 280 GMM_UNIFIED_COMP_FORMAT_RGB10b, //MC Eh --Which media format is it? 281 GMM_UNIFIED_COMP_FORMAT_NV12, //MC Fh 282 GMM_UNIFIED_COMP_FORMAT_NV12_L = GMM_UNIFIED_COMP_FORMAT_NV12, 283 GMM_UNIFIED_COMP_FORMAT_NV12_C = GMM_UNIFIED_COMP_FORMAT_NV12, 284 285 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPUV = GMM_UNIFIED_COMP_FORMAT_SWAPUV, 286 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPUVY = GMM_UNIFIED_COMP_FORMAT_SWAPUVY, 287 GMM_UNIFIED_COMP_FORMAT_YCRCB_SWAPY = GMM_UNIFIED_COMP_FORMAT_SWAPY, 288 289 GMM_UNIFIED_COMP_MAX_MC_FORMAT = GMM_UNIFIED_COMP_FORMAT_NV12, //should always be equal to last format encoding 290 291 GMM_UNIFIED_COMP_FORMAT_INVALID, //equal to last valid encoding plus one 292 } GMM_UNIFIED_COMP_FORMAT; 293 294 #ifdef __cplusplus 295 extern "C" { 296 #endif /*__cplusplus*/ 297 298 // Set packing alignment 299 #pragma pack(push, 8) 300 301 #ifndef __GMM_KMD__ 302 #ifdef _WIN32 303 #ifndef PHYSICAL_ADDRESS 304 #define PHYSICAL_ADDRESS LARGE_INTEGER 305 #endif 306 #endif 307 #ifndef PAGE_SIZE 308 #define PAGE_SIZE 4096 309 #endif 310 #endif /*__GMM_KMD__*/ 311 312 //=========================================================================== 313 // typedef: 314 // GMM_FORMAT_ENTRY 315 // 316 // Description: 317 // This struct is used to describe each surface format in the 318 // GMM_RESOURCE_FORMAT enum. Each surface format is desginated as a 319 // supported format on the running platform, as well as if the format is 320 // renderable. 321 // 322 //--------------------------------------------------------------------------- 323 typedef struct GMM_FORMAT_ENTRY_REC 324 { 325 struct 326 { 327 uint32_t ASTC : 1; 328 uint32_t Compressed : 1; 329 uint32_t RenderTarget : 1; 330 uint32_t Supported : 1; 331 }; 332 struct 333 { 334 uint16_t BitsPer; 335 uint8_t Depth; 336 uint8_t Height; 337 uint8_t Width; 338 } Element; 339 GMM_SURFACESTATE_FORMAT SurfaceStateFormat; 340 union { 341 GMM_E2ECOMP_FORMAT AuxL1eFormat; 342 uint8_t CompressionFormat; 343 } CompressionFormat; 344 }GMM_FORMAT_ENTRY; 345 346 //=========================================================================== 347 // typedef: 348 // GMM_TILE_MODE_ENUM 349 // 350 // Description: 351 // Enumeration of supported tile modes. 352 // 353 //-------------------------------------------------------------------------- 354 #define DEFINE_TILE_BPEs(TileName) \ 355 TILE_##TileName##_8bpe, \ 356 TILE_##TileName##_16bpe, \ 357 TILE_##TileName##_32bpe, \ 358 TILE_##TileName##_64bpe, \ 359 TILE_##TileName##_128bpe \ 360 361 typedef enum GMM_TILE_MODE_ENUM 362 { 363 TILE_NONE, 364 // Legacy Tile Modes 365 LEGACY_TILE_X, 366 LEGACY_TILE_Y, 367 // Tile-W is a 64x64 tile swizzled 368 // onto a 128x32 Tile-Y. 369 // For allocation purposes Tile-W 370 // can be treated like Tile-Y 371 // TILE_W 372 373 // Tiled Resource Modes (SKL+) 374 DEFINE_TILE_BPEs( YF_1D ), 375 DEFINE_TILE_BPEs( YS_1D ), 376 DEFINE_TILE_BPEs( YF_2D ), 377 DEFINE_TILE_BPEs( YF_2D_2X ), 378 DEFINE_TILE_BPEs( YF_2D_4X ), 379 DEFINE_TILE_BPEs( YF_2D_8X ), 380 DEFINE_TILE_BPEs( YF_2D_16X ), 381 DEFINE_TILE_BPEs( YF_3D ), 382 DEFINE_TILE_BPEs( YS_2D ), 383 DEFINE_TILE_BPEs( YS_2D_2X ), 384 DEFINE_TILE_BPEs( YS_2D_4X ), 385 DEFINE_TILE_BPEs( YS_2D_8X ), 386 DEFINE_TILE_BPEs( YS_2D_16X ), 387 DEFINE_TILE_BPEs( YS_3D ), 388 389 // XE_HP/Xe2_LPG 390 TILE4, 391 DEFINE_TILE_BPEs( _64_1D ), 392 DEFINE_TILE_BPEs( _64_2D ), 393 DEFINE_TILE_BPEs( _64_2D_2X), 394 DEFINE_TILE_BPEs( _64_2D_4X), 395 DEFINE_TILE_BPEs( _64_3D), 396 // Xe2 above 397 DEFINE_TILE_BPEs(_64_2D_8X), 398 DEFINE_TILE_BPEs(_64_2D_16X), 399 GMM_TILE_MODES 400 }GMM_TILE_MODE; 401 402 #undef DEFINE_TILE_BPEs 403 404 typedef struct __TEX_ALIGNMENT 405 { 406 uint32_t Width; // pixels 407 uint32_t Height; // scanlines 408 uint32_t Depth; // pixels 409 } ALIGNMENT; 410 411 //=========================================================================== 412 // typedef: 413 // GMM_TEXTURE_ALIGN 414 // 415 // Description: 416 // The following struct describes the texture mip map unit alignment 417 // required for each map format. The alignment values are platform 418 // dependent. 419 // 420 //--------------------------------------------------------------------------- 421 typedef struct GMM_TEXTURE_ALIGN_REC 422 { 423 ALIGNMENT Compressed, Depth, Depth_D16_UNORM_1x_4x_16x, Depth_D16_UNORM_2x_8x, SeparateStencil, YUV422, XAdapter, AllOther; 424 425 struct 426 { 427 ALIGNMENT Align; 428 uint32_t MaxPitchinTiles; 429 } CCS; 430 }GMM_TEXTURE_ALIGN; 431 432 //=========================================================================== 433 // typedef: 434 // __GMM_BUFFER_TYPE_REC 435 // 436 // Description: 437 // This structure represents a buffer type. Common buffer types are 438 // Display buffers, Color buffers, Linear buffers and ring buffers. 439 // Each buffer type has platform specific size, dimension and alignment 440 // restricions that are stored here. 441 // 442 //--------------------------------------------------------------------------- 443 typedef struct __GMM_BUFFER_TYPE_REC 444 { 445 uint32_t Alignment; // Base Address Alignment 446 uint32_t PitchAlignment; // Pitch Alignment restriction. 447 uint32_t RenderPitchAlignment; // Pitch Alignment for render surface 448 uint32_t LockPitchAlignment; // Pitch Alignment for locked surface 449 uint32_t MinPitch; // Minimum pitch 450 GMM_GFX_SIZE_T MaxPitch; // Maximum pitch 451 GMM_GFX_SIZE_T MinAllocationSize; // Minimum Allocation size requirement 452 453 uint32_t MinHeight; // Mininum height in bytes 454 GMM_GFX_SIZE_T MinWidth; // Minimum width in bytes 455 uint32_t MinDepth; // Minimum depth (only for volume) 456 GMM_GFX_SIZE_T MaxHeight; // Maximum height in bytes 457 GMM_GFX_SIZE_T MaxWidth; // Maximum Width in bytes 458 uint32_t MaxDepth; // Maximum depth (only for volume) 459 uint32_t MaxArraySize; 460 uint8_t NeedPow2LockAlignment; // Locking surface need to be power of 2 aligned 461 } __GMM_BUFFER_TYPE; 462 463 //=========================================================================== 464 // typedef: 465 // __GMM_PLATFORM_RESOURCE 466 // 467 // Description: 468 // This structure represents various platform specific restrictions for 469 // - buffer types 470 // - tile dimensions 471 // - # of fences regisers platform supports 472 // - # of addressable bits 473 // - aperture size 474 // 475 //---------------------------------------------------------------------------- 476 typedef struct __GMM_PLATFORM_RESOURCE_REC 477 { 478 PLATFORM Platform; 479 // 480 // Define memory type req., alignment, min allocation size; 481 // 482 __GMM_BUFFER_TYPE Vertex; // Vertex Buffer restrictions 483 __GMM_BUFFER_TYPE Index; // Index Buffer restrictions 484 __GMM_BUFFER_TYPE Constant; // 485 __GMM_BUFFER_TYPE StateDx9ConstantBuffer; // Dx9 Constant Buffer pool restrictions 486 487 __GMM_BUFFER_TYPE Texture2DSurface; // 2D texture surface 488 __GMM_BUFFER_TYPE Texture2DLinearSurface; // 2D Linear media surface 489 __GMM_BUFFER_TYPE Texture3DSurface; // 3D texture surface 490 __GMM_BUFFER_TYPE CubeSurface; // cube texture surface 491 __GMM_BUFFER_TYPE BufferType; // Buffer type surface 492 493 __GMM_BUFFER_TYPE Color; // Color (Render Target) Buffer 494 __GMM_BUFFER_TYPE Depth; // Depth Buffer Restriction 495 __GMM_BUFFER_TYPE Stencil; // Stencil Buffer Restrictions 496 __GMM_BUFFER_TYPE HiZ; // Hierarchical Depth Buffer Resrictions 497 __GMM_BUFFER_TYPE Stream; // 498 499 __GMM_BUFFER_TYPE Video; // Video Planar surface restrictions 500 __GMM_BUFFER_TYPE MotionComp; // Motion Compensation buffer 501 502 __GMM_BUFFER_TYPE Overlay; // Overlay Buffer 503 __GMM_BUFFER_TYPE Nndi; // Non native display buffer restrictions 504 __GMM_BUFFER_TYPE ASyncFlipSurface; // ASync flip chain Buffers 505 506 __GMM_BUFFER_TYPE HardwareMBM; // Buffer Restrictions 507 508 __GMM_BUFFER_TYPE InterlacedScan; // 509 __GMM_BUFFER_TYPE TextApi; // 510 511 __GMM_BUFFER_TYPE Linear; // Linear(Generic) Buffer restrictions 512 __GMM_BUFFER_TYPE Cursor; // Cursor surface restrictions 513 __GMM_BUFFER_TYPE NoRestriction; // Motion Comp Buffer 514 515 __GMM_BUFFER_TYPE XAdapter; // Cross adapter linear buffer restrictions 516 517 GMM_TEXTURE_ALIGN TexAlign; // Alignment Units for Texture Maps 518 519 // 520 // various tile dimension based on platform 521 // 522 GMM_TILE_INFO TileInfo[GMM_TILE_MODES]; 523 524 // 525 // General platform Restriction 526 // 527 uint32_t NumberFenceRegisters; 528 uint32_t MinFenceSize; // 1 MB for Napa, 512 KB for Almador 529 530 uint32_t FenceLowBoundShift; 531 uint32_t FenceLowBoundMask; 532 533 uint32_t PageTableSteer; // Default for page table steer register 534 535 uint32_t PagingBufferPrivateDataSize; 536 uint32_t MaxLod; 537 uint32_t FBCRequiredStolenMemorySize; // Stolen Memory size required for FBC 538 539 GMM_FORMAT_ENTRY FormatTable[GMM_RESOURCE_FORMATS]; 540 541 uint32_t ResAllocTag[GMM_MAX_HW_RESOURCE_TYPE]; // uint32_t = 4 8-bit ASCII characters 542 543 uint32_t SurfaceStateYOffsetGranularity; 544 uint32_t SamplerFetchGranularityWidth; 545 uint32_t SamplerFetchGranularityHeight; 546 547 int64_t SurfaceMaxSize; // int64_t - Surface size is 64 bit for all configurations 548 uint32_t MaxGpuVirtualAddressBitsPerResource; 549 uint32_t MaxSLMSize; 550 551 uint8_t HiZPixelsPerByte; //HiZ-Bpp is < 1, keep inverse 552 uint64_t ReconMaxHeight; 553 uint64_t ReconMaxWidth; 554 uint8_t NoOfBitsSupported; // No of bits supported for System physcial address on GPU 555 uint64_t HighestAcceptablePhysicalAddress; // Highest acceptable System physical Address 556 }__GMM_PLATFORM_RESOURCE, GMM_PLATFORM_INFO; 557 558 //*************************************************************************** 559 // 560 // GMM_PLATFORM_INFO API 561 // 562 //*************************************************************************** 563 uint32_t GMM_STDCALL GmmPlatformGetBppFromGmmResourceFormat(void *pLibContext, GMM_RESOURCE_FORMAT Format); 564 565 // Reset packing alignment to project default 566 #pragma pack(pop) 567 568 #ifdef __cplusplus 569 } 570 #endif /*__cplusplus*/ 571