1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef COMMONLIB_COREBOOT_TABLES_H 4 #define COMMONLIB_COREBOOT_TABLES_H 5 6 #include <stdint.h> 7 8 /* The coreboot table information is for conveying information 9 * from the firmware to the loaded OS image. Primarily this 10 * is expected to be information that cannot be discovered by 11 * other means, such as querying the hardware directly. 12 * 13 * All of the information should be Position Independent Data. 14 * That is it should be safe to relocated any of the information 15 * without it's meaning/correctness changing. For table that 16 * can reasonably be used on multiple architectures the data 17 * size should be fixed. This should ease the transition between 18 * 32 bit and 64 bit architectures etc. 19 * 20 * The completeness test for the information in this table is: 21 * - Can all of the hardware be detected? 22 * - Are the per motherboard constants available? 23 * - Is there enough to allow a kernel to run that was written before 24 * a particular motherboard is constructed? (Assuming the kernel 25 * has drivers for all of the hardware but it does not have 26 * assumptions on how the hardware is connected together). 27 * 28 * With this test it should be straight forward to determine if a 29 * table entry is required or not. This should remove much of the 30 * long term compatibility burden as table entries which are 31 * irrelevant or have been replaced by better alternatives may be 32 * dropped. Of course it is polite and expedite to include extra 33 * table entries and be backwards compatible, but it is not required. 34 */ 35 36 enum { 37 LB_TAG_UNUSED = 0x0000, 38 LB_TAG_MEMORY = 0x0001, 39 LB_TAG_HWRPB = 0x0002, 40 LB_TAG_MAINBOARD = 0x0003, 41 LB_TAG_VERSION = 0x0004, 42 LB_TAG_EXTRA_VERSION = 0x0005, 43 LB_TAG_BUILD = 0x0006, 44 LB_TAG_COMPILE_TIME = 0x0007, 45 LB_TAG_COMPILE_BY = 0x0008, 46 LB_TAG_COMPILE_HOST = 0x0009, 47 LB_TAG_COMPILE_DOMAIN = 0x000a, 48 LB_TAG_COMPILER = 0x000b, 49 LB_TAG_LINKER = 0x000c, 50 LB_TAG_ASSEMBLER = 0x000d, 51 LB_TAG_SERIAL = 0x000f, 52 LB_TAG_CONSOLE = 0x0010, 53 LB_TAG_FORWARD = 0x0011, 54 LB_TAG_FRAMEBUFFER = 0x0012, 55 LB_TAG_GPIO = 0x0013, 56 LB_TAG_TIMESTAMPS = 0x0016, 57 LB_TAG_CBMEM_CONSOLE = 0x0017, 58 LB_TAG_MRC_CACHE = 0x0018, 59 LB_TAG_VBNV = 0x0019, 60 LB_TAG_VBOOT_HANDOFF = 0x0020, /* deprecated */ 61 LB_TAG_X86_ROM_MTRR = 0x0021, 62 LB_TAG_DMA = 0x0022, 63 LB_TAG_RAM_OOPS = 0x0023, 64 LB_TAG_ACPI_GNVS = 0x0024, 65 LB_TAG_BOARD_ID = 0x0025, /* deprecated */ 66 LB_TAG_VERSION_TIMESTAMP = 0x0026, 67 LB_TAG_WIFI_CALIBRATION = 0x0027, 68 LB_TAG_RAM_CODE = 0x0028, /* deprecated */ 69 LB_TAG_SPI_FLASH = 0x0029, 70 LB_TAG_SERIALNO = 0x002a, 71 LB_TAG_MTC = 0x002b, 72 LB_TAG_VPD = 0x002c, 73 LB_TAG_SKU_ID = 0x002d, /* deprecated */ 74 LB_TAG_BOOT_MEDIA_PARAMS = 0x0030, 75 LB_TAG_CBMEM_ENTRY = 0x0031, 76 LB_TAG_TSC_INFO = 0x0032, 77 LB_TAG_MAC_ADDRS = 0x0033, 78 LB_TAG_VBOOT_WORKBUF = 0x0034, 79 LB_TAG_MMC_INFO = 0x0035, 80 LB_TAG_TPM_CB_LOG = 0x0036, 81 LB_TAG_FMAP = 0x0037, 82 LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, 83 LB_TAG_SMMSTOREV2 = 0x0039, 84 LB_TAG_TPM_PPI_HANDOFF = 0x003a, 85 LB_TAG_BOARD_CONFIG = 0x0040, 86 LB_TAG_ACPI_CNVS = 0x0041, 87 LB_TAG_TYPE_C_INFO = 0x0042, 88 LB_TAG_ACPI_RSDP = 0x0043, 89 LB_TAG_PCIE = 0x0044, 90 /* The following options are CMOS-related */ 91 LB_TAG_CMOS_OPTION_TABLE = 0x00c8, 92 LB_TAG_OPTION = 0x00c9, 93 LB_TAG_OPTION_ENUM = 0x00ca, 94 LB_TAG_OPTION_DEFAULTS = 0x00cb, 95 LB_TAG_OPTION_CHECKSUM = 0x00cc, 96 }; 97 98 /* All table entry base addresses and sizes must be 4-byte aligned. */ 99 #define LB_ENTRY_ALIGN 4 100 101 /* Since coreboot is usually compiled 32bit, gcc will align 64bit 102 * types to 32bit boundaries. If the coreboot table is dumped on a 103 * 64bit system, a uint64_t would be aligned to 64bit boundaries, 104 * breaking the table format. 105 * 106 * lb_uint64_t will keep 64bit coreboot table values aligned to 32bit 107 * to ensure compatibility. 108 */ 109 110 typedef __aligned(LB_ENTRY_ALIGN) uint64_t lb_uint64_t; 111 112 struct lb_header { 113 uint8_t signature[4]; /* LBIO */ 114 uint32_t header_bytes; 115 uint32_t header_checksum; 116 uint32_t table_bytes; 117 uint32_t table_checksum; 118 uint32_t table_entries; 119 }; 120 121 /* Every entry in the boot environment list will correspond to a boot 122 * info record. Encoding both type and size. The type is obviously 123 * so you can tell what it is. The size allows you to skip that 124 * boot environment record if you don't know what it is. This allows 125 * forward compatibility with records not yet defined. 126 */ 127 struct lb_record { 128 uint32_t tag; /* tag ID */ 129 uint32_t size; /* size of record (in bytes) */ 130 }; 131 132 struct lb_memory_range { 133 lb_uint64_t start; 134 lb_uint64_t size; 135 uint32_t type; 136 #define LB_MEM_RAM 1 /* Memory anyone can use */ 137 #define LB_MEM_RESERVED 2 /* Don't use this memory region */ 138 #define LB_MEM_ACPI 3 /* ACPI Tables */ 139 #define LB_MEM_NVS 4 /* ACPI NVS Memory */ 140 #define LB_MEM_UNUSABLE 5 /* Unusable address space */ 141 #define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */ 142 #define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */ 143 #define LB_MEM_SOFT_RESERVED 0xefffffff /* Specific purpose memory */ 144 }; 145 146 struct lb_memory { 147 uint32_t tag; 148 uint32_t size; 149 struct lb_memory_range map[]; 150 }; 151 152 struct lb_pcie { 153 uint32_t tag; 154 uint32_t size; 155 lb_uint64_t ctrl_base; /* Base address of PCIe controller */ 156 }; 157 _Static_assert(_Alignof(struct lb_pcie) == 4, 158 "lb_uint64_t alignment doesn't work as expected for struct lb_pcie!"); 159 160 struct lb_hwrpb { 161 uint32_t tag; 162 uint32_t size; 163 lb_uint64_t hwrpb; 164 }; 165 166 struct lb_mainboard { 167 uint32_t tag; 168 uint32_t size; 169 uint8_t vendor_idx; 170 uint8_t part_number_idx; 171 uint8_t strings[]; 172 }; 173 174 struct lb_string { 175 uint32_t tag; 176 uint32_t size; 177 uint8_t string[]; 178 }; 179 180 struct lb_timestamp { 181 uint32_t tag; 182 uint32_t size; 183 uint32_t timestamp; 184 }; 185 186 /* 0xe is taken by v3 */ 187 188 struct lb_serial { 189 uint32_t tag; 190 uint32_t size; 191 #define LB_SERIAL_TYPE_IO_MAPPED 1 192 #define LB_SERIAL_TYPE_MEMORY_MAPPED 2 193 uint32_t type; 194 uint32_t baseaddr; 195 uint32_t baud; 196 uint32_t regwidth; 197 198 /* Crystal or input frequency to the chip containing the UART. 199 * Provide the board specific details to allow the payload to 200 * initialize the chip containing the UART and make independent 201 * decisions as to which dividers to select and their values 202 * to eventually arrive at the desired console baud-rate. */ 203 uint32_t input_hertz; 204 }; 205 206 struct lb_console { 207 uint32_t tag; 208 uint32_t size; 209 uint16_t type; 210 uint8_t pad[2]; 211 }; 212 213 #define LB_TAG_CONSOLE_SERIAL8250 0 214 #define LB_TAG_CONSOLE_VGA 1 // OBSOLETE 215 #define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE 216 #define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE 217 #define LB_TAG_CONSOLE_SROM 4 // OBSOLETE 218 #define LB_TAG_CONSOLE_EHCI 5 219 #define LB_TAG_CONSOLE_SERIAL8250MEM 6 220 221 struct lb_forward { 222 uint32_t tag; 223 uint32_t size; 224 lb_uint64_t forward; 225 }; 226 227 /** 228 * coreboot framebuffer 229 * 230 * The coreboot framebuffer uses a very common format usually referred 231 * to as "linear framebuffer": 232 * 233 * The first pixel of the framebuffer is the upper left corner, its 234 * address is given by `physical_address`. 235 * 236 * Each pixel is represented by exactly `bits_per_pixel` bits. If a 237 * pixel (or a color component therein) doesn't fill a whole byte or 238 * doesn't start on a byte boundary, it starts at the least signifi- 239 * cant bit not occupied by the previous pixel (or color component). 240 * Pixels (or color components) that span multiple bytes always start 241 * in the byte with the lowest address. 242 * 243 * The framebuffer provides a visible rectangle of `x_resolution` * 244 * `y_resolution` pixels. However, the lines always start at a byte 245 * boundary given by `bytes_per_line`, which may leave a gap after 246 * each line of pixels. Thus, the data for a pixel with the coordi- 247 * nates (x, y) from the upper left corner always starts at 248 * 249 * physical_address + y * bytes_per_line + x * bits_per_pixel / 8 250 * 251 * `bytes_per_line` is always big enough to hold `x_resolution` 252 * pixels. It can, however, be arbitrarily higher (e.g. to fulfill 253 * hardware constraints or for optimization purposes). The size of 254 * the framebuffer is always `y_resolution * bytes_per_line`. 255 * 256 * The coreboot framebuffer only supports RGB color formats. The 257 * position and size of each color component are specified indivi- 258 * dually by <color>_mask_pos and <color>_mask_size. To allow byte 259 * or word aligned pixels, a fourth (padding) component may be 260 * specified by `reserved_mask_pos` and `reserved_mask_size`. 261 * 262 * Software utilizing the coreboot framebuffer shall consider all 263 * fields described above. It may, however, only implement a subset 264 * of the possible color formats. 265 */ 266 267 /* 268 * Framebuffer orientation, matches drm_connector.h drm_panel_orientation in the 269 * Linux kernel. 270 */ 271 enum lb_fb_orientation { 272 LB_FB_ORIENTATION_NORMAL = 0, 273 LB_FB_ORIENTATION_BOTTOM_UP = 1, 274 LB_FB_ORIENTATION_LEFT_UP = 2, 275 LB_FB_ORIENTATION_RIGHT_UP = 3, 276 }; 277 278 struct lb_framebuffer_flags { 279 uint8_t has_external_display : 1; 280 uint8_t reserved : 7; 281 }; 282 283 struct lb_framebuffer { 284 uint32_t tag; 285 uint32_t size; 286 287 lb_uint64_t physical_address; 288 uint32_t x_resolution; 289 uint32_t y_resolution; 290 uint32_t bytes_per_line; 291 uint8_t bits_per_pixel; 292 uint8_t red_mask_pos; 293 uint8_t red_mask_size; 294 uint8_t green_mask_pos; 295 uint8_t green_mask_size; 296 uint8_t blue_mask_pos; 297 uint8_t blue_mask_size; 298 uint8_t reserved_mask_pos; 299 uint8_t reserved_mask_size; 300 uint8_t orientation; 301 struct lb_framebuffer_flags flags; 302 uint8_t pad; 303 }; 304 305 struct lb_gpio { 306 uint32_t port; 307 uint32_t polarity; 308 #define ACTIVE_LOW 0 309 #define ACTIVE_HIGH 1 310 uint32_t value; 311 #define GPIO_MAX_NAME_LENGTH 16 312 uint8_t name[GPIO_MAX_NAME_LENGTH]; 313 }; 314 315 struct lb_gpios { 316 uint32_t tag; 317 uint32_t size; 318 319 uint32_t count; 320 struct lb_gpio gpios[]; 321 }; 322 323 struct lb_range { 324 uint32_t tag; 325 uint32_t size; 326 327 lb_uint64_t range_start; 328 uint32_t range_size; 329 }; 330 331 void lb_ramoops(struct lb_header *header); 332 333 struct lb_cbmem_ref { 334 uint32_t tag; 335 uint32_t size; 336 337 lb_uint64_t cbmem_addr; 338 }; 339 340 struct lb_x86_rom_mtrr { 341 uint32_t tag; 342 uint32_t size; 343 /* The variable range MTRR index covering the ROM. */ 344 uint32_t index; 345 }; 346 347 /* Memory map windows to translate addresses between SPI flash space and host address space. */ 348 struct flash_mmap_window { 349 uint32_t flash_base; 350 uint32_t host_base; 351 uint32_t size; 352 }; 353 354 struct lb_spi_flash { 355 uint32_t tag; 356 uint32_t size; 357 uint32_t flash_size; 358 uint32_t sector_size; 359 uint32_t erase_cmd; 360 /* 361 * Number of mmap windows used by the platform to decode addresses between SPI flash 362 * space and host address space. This determines the number of entries in mmap_table. 363 */ 364 365 uint32_t mmap_count; 366 struct flash_mmap_window mmap_table[]; 367 }; 368 369 struct lb_boot_media_params { 370 uint32_t tag; 371 uint32_t size; 372 /* offsets are relative to start of boot media */ 373 lb_uint64_t fmap_offset; 374 lb_uint64_t cbfs_offset; 375 lb_uint64_t cbfs_size; 376 lb_uint64_t boot_media_size; 377 }; 378 379 /* 380 * There can be more than one of these records as there is one per cbmem entry. 381 */ 382 struct lb_cbmem_entry { 383 uint32_t tag; 384 uint32_t size; 385 386 lb_uint64_t address; 387 uint32_t entry_size; 388 uint32_t id; 389 }; 390 391 struct lb_tsc_info { 392 uint32_t tag; 393 uint32_t size; 394 395 uint32_t freq_khz; 396 }; 397 398 struct mac_address { 399 uint8_t mac_addr[6]; 400 uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ 401 }; 402 403 struct lb_mmc_info { 404 uint32_t tag; 405 uint32_t size; 406 /* 407 * Passes the early mmc status to payload to indicate if firmware 408 * successfully sent CMD0, CMD1 to the card or not. In case of 409 * success, the payload can skip the first step of the initialization 410 * sequence which is to send CMD0, and instead start by sending CMD1 411 * as described in Jedec Standard JESD83-B1 section 6.4.3. 412 * passes 1 on success 413 */ 414 int32_t early_cmd1_status; 415 }; 416 417 /* 418 * USB Type-C Port Information 419 * This record contains board-specific type-c port information. 420 * There will be one record per type-C port. 421 * Orientation fields should be of type enum type_c_orientation. 422 */ 423 enum type_c_orientation { 424 /* The orientation of the signal follows the orientation of the CC lines. */ 425 TYPEC_ORIENTATION_NONE, 426 /* The orientation of the signal is fixed to follow CC1 */ 427 TYPEC_ORIENTATION_NORMAL, 428 /* The orientation of the signal is fixed to follow CC2 */ 429 TYPEC_ORIENTATION_REVERSE, 430 }; 431 432 struct type_c_port_info { 433 uint8_t usb2_port_number; 434 uint8_t usb3_port_number; 435 uint8_t sbu_orientation; 436 uint8_t data_orientation; 437 }; 438 439 struct type_c_info { 440 uint32_t port_count; 441 struct type_c_port_info port_info[]; 442 }; 443 444 struct lb_macs { 445 uint32_t tag; 446 uint32_t size; 447 uint32_t count; 448 struct mac_address mac_addrs[]; 449 }; 450 451 struct lb_board_config { 452 uint32_t tag; 453 uint32_t size; 454 455 lb_uint64_t fw_config; 456 uint32_t board_id; 457 uint32_t ram_code; 458 uint32_t sku_id; 459 }; 460 461 #define MAX_SERIALNO_LENGTH 32 462 463 /* The following structures are for the CMOS definitions table */ 464 /* CMOS header record */ 465 struct cmos_option_table { 466 uint32_t tag; /* CMOS definitions table type */ 467 uint32_t size; /* size of the entire table */ 468 uint32_t header_length; /* length of header */ 469 }; 470 471 /* CMOS entry record 472 * This record is variable length. The name field may be 473 * shorter than CMOS_MAX_NAME_LENGTH. The entry may start 474 * anywhere in the byte, but can not span bytes unless it 475 * starts at the beginning of the byte and the length is 476 * fills complete bytes. 477 */ 478 struct cmos_entries { 479 uint32_t tag; /* entry type */ 480 uint32_t size; /* length of this record */ 481 uint32_t bit; /* starting bit from start of image */ 482 uint32_t length; /* length of field in bits */ 483 uint32_t config; /* e=enumeration, h=hex, r=reserved */ 484 uint32_t config_id; /* a number linking to an enumeration record */ 485 #define CMOS_MAX_NAME_LENGTH 32 486 uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, 487 variable length int aligned */ 488 }; 489 490 /* CMOS enumerations record 491 * This record is variable length. The text field may be 492 * shorter than CMOS_MAX_TEXT_LENGTH. 493 */ 494 struct cmos_enums { 495 uint32_t tag; /* enumeration type */ 496 uint32_t size; /* length of this record */ 497 uint32_t config_id; /* a number identifying the config id */ 498 uint32_t value; /* the value associated with the text */ 499 #define CMOS_MAX_TEXT_LENGTH 32 500 uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, 501 variable length int aligned */ 502 }; 503 504 /* CMOS defaults record 505 * This record contains default settings for the CMOS ram. 506 */ 507 struct cmos_defaults { 508 uint32_t tag; /* default type */ 509 uint32_t size; /* length of this record */ 510 uint32_t name_length; /* length of the following name field */ 511 uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */ 512 #define CMOS_IMAGE_BUFFER_SIZE 256 513 uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */ 514 }; 515 516 struct cmos_checksum { 517 uint32_t tag; 518 uint32_t size; 519 /* In practice everything is byte aligned, but things are measured 520 * in bits to be consistent. 521 */ 522 uint32_t range_start; /* First bit that is checksummed (byte aligned) */ 523 uint32_t range_end; /* Last bit that is checksummed (byte aligned) */ 524 uint32_t location; /* First bit of the checksum (byte aligned) */ 525 uint32_t type; /* Checksum algorithm that is used */ 526 #define CHECKSUM_NONE 0 527 #define CHECKSUM_PCBIOS 1 528 }; 529 530 /* SMMSTOREv2 record 531 * This record contains information to use SMMSTOREv2. 532 */ 533 534 struct lb_smmstorev2 { 535 uint32_t tag; 536 uint32_t size; 537 uint32_t num_blocks; /* Number of writable blocks in SMM */ 538 uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ 539 uint32_t mmap_addr; /* MMIO address of the store for read only access */ 540 uint32_t com_buffer; /* Physical address of the communication buffer */ 541 uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ 542 uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ 543 uint8_t unused[3]; /* Set to zero */ 544 }; 545 546 enum lb_tpm_ppi_tpm_version { 547 LB_TPM_VERSION_UNSPEC = 0, 548 LB_TPM_VERSION_TPM_VERSION_1_2, 549 LB_TPM_VERSION_TPM_VERSION_2, 550 }; 551 552 /* 553 * Handoff buffer for TPM Physical Presence Interface. 554 * * ppi_address Pointer to PPI buffer shared with ACPI 555 * The layout of the buffer matches the QEMU virtual memory device 556 * that is generated by QEMU. 557 * See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' 558 * for details. 559 * * tpm_version TPM version: 1 for TPM1.2, 2 for TPM2.0 560 * * ppi_version BCD encoded version of TPM PPI interface 561 */ 562 struct lb_tpm_physical_presence { 563 uint32_t tag; 564 uint32_t size; 565 uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ 566 uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ 567 uint8_t ppi_version; /* BCD encoded */ 568 uint8_t pad[2]; 569 }; 570 571 572 /* 573 * Handoff the ACPI RSDP 574 */ 575 struct lb_acpi_rsdp { 576 uint32_t tag; 577 uint32_t size; 578 lb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ 579 }; 580 581 #endif 582