1 /* 2 * Copyright (C) 2022 Google LLC 3 */ 4 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 7 // Undefine macros conflicting with our definitions. 8 #ifdef linux 9 #undef linux 10 #endif 11 12 #define PLACEHOLDER 0xffffffff 13 #define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER 14 #define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2 15 16 #define PLACEHOLDER_CPU_MAP_CORE(n) core##n { cpu = <PLACEHOLDER>; }; 17 #define PLACEHOLDER_CPU_MAP_CLUSTER \ 18 PLACEHOLDER_CPU_MAP_CORE(0) \ 19 PLACEHOLDER_CPU_MAP_CORE(1) \ 20 PLACEHOLDER_CPU_MAP_CORE(2) \ 21 PLACEHOLDER_CPU_MAP_CORE(3) \ 22 PLACEHOLDER_CPU_MAP_CORE(4) \ 23 PLACEHOLDER_CPU_MAP_CORE(5) \ 24 PLACEHOLDER_CPU_MAP_CORE(6) \ 25 PLACEHOLDER_CPU_MAP_CORE(7) \ 26 PLACEHOLDER_CPU_MAP_CORE(8) \ 27 PLACEHOLDER_CPU_MAP_CORE(9) 28 29 #define PLACEHOLDER_OPP_TABLE_ENTRY(n) opp##n { opp-hz = <PLACEHOLDER2>; }; 30 #define PLACEHOLDER_OPP_TABLE \ 31 PLACEHOLDER_OPP_TABLE_ENTRY(1) \ 32 PLACEHOLDER_OPP_TABLE_ENTRY(2) \ 33 PLACEHOLDER_OPP_TABLE_ENTRY(3) \ 34 PLACEHOLDER_OPP_TABLE_ENTRY(4) \ 35 PLACEHOLDER_OPP_TABLE_ENTRY(5) \ 36 PLACEHOLDER_OPP_TABLE_ENTRY(6) \ 37 PLACEHOLDER_OPP_TABLE_ENTRY(7) \ 38 PLACEHOLDER_OPP_TABLE_ENTRY(8) \ 39 PLACEHOLDER_OPP_TABLE_ENTRY(9) \ 40 PLACEHOLDER_OPP_TABLE_ENTRY(10) \ 41 PLACEHOLDER_OPP_TABLE_ENTRY(11) \ 42 PLACEHOLDER_OPP_TABLE_ENTRY(12) \ 43 PLACEHOLDER_OPP_TABLE_ENTRY(13) \ 44 PLACEHOLDER_OPP_TABLE_ENTRY(14) \ 45 PLACEHOLDER_OPP_TABLE_ENTRY(15) \ 46 PLACEHOLDER_OPP_TABLE_ENTRY(16) \ 47 PLACEHOLDER_OPP_TABLE_ENTRY(17) \ 48 PLACEHOLDER_OPP_TABLE_ENTRY(18) \ 49 PLACEHOLDER_OPP_TABLE_ENTRY(19) \ 50 PLACEHOLDER_OPP_TABLE_ENTRY(20) 51 52 #define IRQ_BASE 4 53 54 /dts-v1/; 55 56 / { 57 interrupt-parent = <&intc>; 58 compatible = "linux,dummy-virt"; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 62 chosen { 63 stdout-path = "/uart@3f8"; 64 linux,pci-probe-only = <1>; 65 kaslr-seed = <PLACEHOLDER2>; 66 avf,strict-boot; 67 avf,new-instance; 68 }; 69 70 memory { 71 device_type = "memory"; 72 reg = <0x00 0x80000000 PLACEHOLDER2>; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 swiotlb: restricted_dma_reserved { 80 compatible = "restricted-dma-pool"; 81 reg = <PLACEHOLDER4>; 82 size = <PLACEHOLDER2>; 83 alignment = <PLACEHOLDER2>; 84 }; 85 86 dice { 87 compatible = "google,open-dice"; 88 no-map; 89 reg = <PLACEHOLDER4>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 cpu-map { 98 cluster0 { PLACEHOLDER_CPU_MAP_CLUSTER }; 99 cluster1 { PLACEHOLDER_CPU_MAP_CLUSTER }; 100 cluster2 { PLACEHOLDER_CPU_MAP_CLUSTER }; 101 }; 102 103 cpu0: cpu@0 { 104 device_type = "cpu"; 105 compatible = "arm,armv8"; 106 enable-method = "psci"; 107 reg = <0x0>; 108 capacity-dmips-mhz = <PLACEHOLDER>; 109 operating-points-v2 = <&opp_table0>; 110 opp_table0: opp-table-0 { 111 compatible = "operating-points-v2"; 112 PLACEHOLDER_OPP_TABLE 113 }; 114 }; 115 cpu1: cpu@1 { 116 device_type = "cpu"; 117 compatible = "arm,armv8"; 118 enable-method = "psci"; 119 reg = <0x1>; 120 capacity-dmips-mhz = <PLACEHOLDER>; 121 operating-points-v2 = <&opp_table1>; 122 opp_table1: opp-table-1 { 123 compatible = "operating-points-v2"; 124 PLACEHOLDER_OPP_TABLE 125 }; 126 }; 127 cpu2: cpu@2 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 enable-method = "psci"; 131 reg = <0x2>; 132 capacity-dmips-mhz = <PLACEHOLDER>; 133 operating-points-v2 = <&opp_table2>; 134 opp_table2: opp-table-2 { 135 compatible = "operating-points-v2"; 136 PLACEHOLDER_OPP_TABLE 137 }; 138 }; 139 cpu3: cpu@3 { 140 device_type = "cpu"; 141 compatible = "arm,armv8"; 142 enable-method = "psci"; 143 reg = <0x3>; 144 capacity-dmips-mhz = <PLACEHOLDER>; 145 operating-points-v2 = <&opp_table3>; 146 opp_table3: opp-table-3 { 147 compatible = "operating-points-v2"; 148 PLACEHOLDER_OPP_TABLE 149 }; 150 }; 151 cpu4: cpu@4 { 152 device_type = "cpu"; 153 compatible = "arm,armv8"; 154 enable-method = "psci"; 155 reg = <0x4>; 156 capacity-dmips-mhz = <PLACEHOLDER>; 157 operating-points-v2 = <&opp_table4>; 158 opp_table4: opp-table-4 { 159 compatible = "operating-points-v2"; 160 PLACEHOLDER_OPP_TABLE 161 }; 162 }; 163 cpu5: cpu@5 { 164 device_type = "cpu"; 165 compatible = "arm,armv8"; 166 enable-method = "psci"; 167 reg = <0x5>; 168 capacity-dmips-mhz = <PLACEHOLDER>; 169 operating-points-v2 = <&opp_table5>; 170 opp_table5: opp-table-5 { 171 compatible = "operating-points-v2"; 172 PLACEHOLDER_OPP_TABLE 173 }; 174 }; 175 cpu6: cpu@6 { 176 device_type = "cpu"; 177 compatible = "arm,armv8"; 178 enable-method = "psci"; 179 reg = <0x6>; 180 capacity-dmips-mhz = <PLACEHOLDER>; 181 operating-points-v2 = <&opp_table6>; 182 opp_table6: opp-table-6 { 183 compatible = "operating-points-v2"; 184 PLACEHOLDER_OPP_TABLE 185 }; 186 }; 187 cpu7: cpu@7 { 188 device_type = "cpu"; 189 compatible = "arm,armv8"; 190 enable-method = "psci"; 191 reg = <0x7>; 192 capacity-dmips-mhz = <PLACEHOLDER>; 193 operating-points-v2 = <&opp_table7>; 194 opp_table7: opp-table-7 { 195 compatible = "operating-points-v2"; 196 PLACEHOLDER_OPP_TABLE 197 }; 198 }; 199 cpu8: cpu@8 { 200 device_type = "cpu"; 201 compatible = "arm,armv8"; 202 enable-method = "psci"; 203 reg = <0x8>; 204 capacity-dmips-mhz = <PLACEHOLDER>; 205 operating-points-v2 = <&opp_table8>; 206 opp_table8: opp-table-8 { 207 compatible = "operating-points-v2"; 208 PLACEHOLDER_OPP_TABLE 209 }; 210 }; 211 cpu9: cpu@9 { 212 device_type = "cpu"; 213 compatible = "arm,armv8"; 214 enable-method = "psci"; 215 reg = <0x9>; 216 capacity-dmips-mhz = <PLACEHOLDER>; 217 operating-points-v2 = <&opp_table9>; 218 opp_table9: opp-table-9 { 219 compatible = "operating-points-v2"; 220 PLACEHOLDER_OPP_TABLE 221 }; 222 }; 223 cpu10: cpu@a { 224 device_type = "cpu"; 225 compatible = "arm,armv8"; 226 enable-method = "psci"; 227 reg = <0xa>; 228 capacity-dmips-mhz = <PLACEHOLDER>; 229 operating-points-v2 = <&opp_table10>; 230 opp_table10: opp-table-10 { 231 compatible = "operating-points-v2"; 232 PLACEHOLDER_OPP_TABLE 233 }; 234 }; 235 cpu11: cpu@b { 236 device_type = "cpu"; 237 compatible = "arm,armv8"; 238 enable-method = "psci"; 239 reg = <0xb>; 240 capacity-dmips-mhz = <PLACEHOLDER>; 241 operating-points-v2 = <&opp_table11>; 242 opp_table11: opp-table-11 { 243 compatible = "operating-points-v2"; 244 PLACEHOLDER_OPP_TABLE 245 }; 246 }; 247 cpu12: cpu@c { 248 device_type = "cpu"; 249 compatible = "arm,armv8"; 250 enable-method = "psci"; 251 reg = <0xc>; 252 capacity-dmips-mhz = <PLACEHOLDER>; 253 operating-points-v2 = <&opp_table12>; 254 opp_table12: opp-table-12 { 255 compatible = "operating-points-v2"; 256 PLACEHOLDER_OPP_TABLE 257 }; 258 }; 259 cpu13: cpu@d { 260 device_type = "cpu"; 261 compatible = "arm,armv8"; 262 enable-method = "psci"; 263 reg = <0xd>; 264 capacity-dmips-mhz = <PLACEHOLDER>; 265 operating-points-v2 = <&opp_table13>; 266 opp_table13: opp-table-13 { 267 compatible = "operating-points-v2"; 268 PLACEHOLDER_OPP_TABLE 269 }; 270 }; 271 cpu14: cpu@e { 272 device_type = "cpu"; 273 compatible = "arm,armv8"; 274 enable-method = "psci"; 275 reg = <0xe>; 276 capacity-dmips-mhz = <PLACEHOLDER>; 277 operating-points-v2 = <&opp_table14>; 278 opp_table14: opp-table-14 { 279 compatible = "operating-points-v2"; 280 PLACEHOLDER_OPP_TABLE 281 }; 282 }; 283 cpu15: cpu@f { 284 device_type = "cpu"; 285 compatible = "arm,armv8"; 286 enable-method = "psci"; 287 reg = <0xf>; 288 capacity-dmips-mhz = <PLACEHOLDER>; 289 operating-points-v2 = <&opp_table15>; 290 opp_table15: opp-table-15 { 291 compatible = "operating-points-v2"; 292 PLACEHOLDER_OPP_TABLE 293 }; 294 }; 295 }; 296 297 intc: intc { 298 compatible = "arm,gic-v3"; 299 #address-cells = <2>; 300 #size-cells = <2>; 301 #interrupt-cells = <3>; 302 interrupt-controller; 303 reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>; 304 }; 305 306 timer { 307 compatible = "arm,armv8-timer"; 308 always-on; 309 /* The IRQ type needs to be OR-ed with the CPU mask */ 310 interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW 311 GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW 312 GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW 313 GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>; 314 }; 315 316 uart@3f8 { 317 compatible = "ns16550a"; 318 reg = <0x00 0x3f8 0x00 0x8>; 319 clock-frequency = <0x1c2000>; 320 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 321 }; 322 323 uart@2f8 { 324 compatible = "ns16550a"; 325 reg = <0x00 0x2f8 0x00 0x8>; 326 clock-frequency = <0x1c2000>; 327 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 328 }; 329 330 uart@3e8 { 331 compatible = "ns16550a"; 332 reg = <0x00 0x3e8 0x00 0x8>; 333 clock-frequency = <0x1c2000>; 334 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 335 }; 336 337 uart@2e8 { 338 compatible = "ns16550a"; 339 reg = <0x00 0x2e8 0x00 0x8>; 340 clock-frequency = <0x1c2000>; 341 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 342 }; 343 344 psci { 345 compatible = "arm,psci-1.0"; 346 method = "hvc"; 347 }; 348 349 pci { 350 compatible = "pci-host-cam-generic"; 351 device_type = "pci"; 352 #address-cells = <3>; 353 #size-cells = <2>; 354 #interrupt-cells = <1>; 355 dma-coherent; 356 memory-region = <&swiotlb>; 357 ranges = < 358 0x3000000 0x0 0x70000000 0x0 0x70000000 0x00 0x02000000 359 0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2 360 >; 361 bus-range = <0x00 0x00>; 362 reg = <0x00 0x72000000 0x00 0x1000000>; 363 interrupt-map = < 364 0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH 365 0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH 366 0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH 367 0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH 368 0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH 369 0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH 370 0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH 371 0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH 372 0x4800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 8) IRQ_TYPE_LEVEL_HIGH 373 0x5000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 9) IRQ_TYPE_LEVEL_HIGH 374 0x5800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 10) IRQ_TYPE_LEVEL_HIGH 375 0x6000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 11) IRQ_TYPE_LEVEL_HIGH 376 0x6800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 12) IRQ_TYPE_LEVEL_HIGH 377 0x7000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 13) IRQ_TYPE_LEVEL_HIGH 378 0x7800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 14) IRQ_TYPE_LEVEL_HIGH 379 0x8000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 15) IRQ_TYPE_LEVEL_HIGH 380 >; 381 interrupt-map-mask = <0xf800 0x0 0x0 0x7 382 0xf800 0x0 0x0 0x7 383 0xf800 0x0 0x0 0x7 384 0xf800 0x0 0x0 0x7 385 0xf800 0x0 0x0 0x7 386 0xf800 0x0 0x0 0x7 387 0xf800 0x0 0x0 0x7 388 0xf800 0x0 0x0 0x7 389 0xf800 0x0 0x0 0x7 390 0xf800 0x0 0x0 0x7 391 0xf800 0x0 0x0 0x7 392 0xf800 0x0 0x0 0x7 393 0xf800 0x0 0x0 0x7 394 0xf800 0x0 0x0 0x7 395 0xf800 0x0 0x0 0x7 396 0xf800 0x0 0x0 0x7>; 397 }; 398 399 clk: pclk@3M { 400 compatible = "fixed-clock"; 401 clock-frequency = <0x2fefd8>; 402 #clock-cells = <0>; 403 }; 404 405 rtc@2000 { 406 compatible = "arm,primecell"; 407 arm,primecell-periphid = <0x41030>; 408 reg = <0x00 0x2000 0x00 0x1000>; 409 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 410 clock-names = "apb_pclk"; 411 clocks = <&clk>; 412 }; 413 414 vmwdt@3000 { 415 compatible = "qemu,vcpu-stall-detector"; 416 reg = <0x00 0x3000 0x00 0x1000>; 417 clock-frequency = <10>; 418 timeout-sec = <8>; 419 interrupts = <GIC_PPI 0xf PLACEHOLDER>; 420 }; 421 422 cpufreq { 423 compatible = "virtual,android-v-only-cpufreq"; 424 reg = <0x0 0x1040000 PLACEHOLDER2>; 425 }; 426 427 // Keep pvIOMMUs at the last for making test happy. 428 // Otherwise, phandle of other nodes are changed when unused pvIOMMU nodes 429 // are removed, so hardcoded phandles in test data would mismatch. 430 pviommu_0: pviommu0 { 431 compatible = "pkvm,pviommu"; 432 id = <PLACEHOLDER>; 433 #iommu-cells = <1>; 434 }; 435 436 pviommu_1: pviommu1 { 437 compatible = "pkvm,pviommu"; 438 id = <PLACEHOLDER>; 439 #iommu-cells = <1>; 440 }; 441 442 pviommu_2: pviommu2 { 443 compatible = "pkvm,pviommu"; 444 id = <PLACEHOLDER>; 445 #iommu-cells = <1>; 446 }; 447 448 pviommu_3: pviommu3 { 449 compatible = "pkvm,pviommu"; 450 id = <PLACEHOLDER>; 451 #iommu-cells = <1>; 452 }; 453 454 pviommu_4: pviommu4 { 455 compatible = "pkvm,pviommu"; 456 id = <PLACEHOLDER>; 457 #iommu-cells = <1>; 458 }; 459 460 pviommu_5: pviommu5 { 461 compatible = "pkvm,pviommu"; 462 id = <PLACEHOLDER>; 463 #iommu-cells = <1>; 464 }; 465 466 pviommu_6: pviommu6 { 467 compatible = "pkvm,pviommu"; 468 id = <PLACEHOLDER>; 469 #iommu-cells = <1>; 470 }; 471 472 pviommu_7: pviommu7 { 473 compatible = "pkvm,pviommu"; 474 id = <PLACEHOLDER>; 475 #iommu-cells = <1>; 476 }; 477 478 pviommu_8: pviommu8 { 479 compatible = "pkvm,pviommu"; 480 id = <PLACEHOLDER>; 481 #iommu-cells = <1>; 482 }; 483 484 pviommu_9: pviommu9 { 485 compatible = "pkvm,pviommu"; 486 id = <PLACEHOLDER>; 487 #iommu-cells = <1>; 488 }; 489 490 // Do not add new node below 491 }; 492