1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <cpu/x86/mtrr.h>
5 #include <cpu/x86/mp.h>
6 #include <cpu/intel/microcode.h>
7 #include <cpu/intel/smm_reloc.h>
8 #include <cpu/intel/common/common.h>
9 #include <device/device.h>
10 #include <types.h>
11
12 /* Parallel MP initialization support. */
pre_mp_init(void)13 static void pre_mp_init(void)
14 {
15 const void *patch = intel_microcode_find();
16 intel_microcode_load_unlocked(patch);
17
18 /* Setup MTRRs based on physical address size. */
19 x86_setup_mtrrs_with_detect();
20 x86_mtrr_check();
21 }
22
get_cpu_count(void)23 static int get_cpu_count(void)
24 {
25 const struct cpuid_result cpuid1 = cpuid(1);
26 const unsigned int cores = (cpuid1.ebx >> 16) & 0xf;
27
28 printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
29
30 return cores;
31 }
32
get_microcode_info(const void ** microcode,int * parallel)33 static void get_microcode_info(const void **microcode, int *parallel)
34 {
35 *microcode = intel_microcode_find();
36 *parallel = !intel_ht_supported();
37 }
38
39 /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL
40 to enable SMRR so configure IA32_FEATURE_CONTROL early on */
pre_mp_smm_init(void)41 static void pre_mp_smm_init(void)
42 {
43 smm_initialize();
44 }
45
46 #define SMRR_SUPPORTED (1 << 11)
47
per_cpu_smm_trigger(void)48 static void per_cpu_smm_trigger(void)
49 {
50 msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
51 if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
52 set_feature_ctrl_vmx();
53 msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
54 /* We don't care if the lock is already setting
55 as our smm relocation handler is able to handle
56 setups where SMRR is not enabled here. */
57 if (ia32_ft_ctrl.lo & (1 << 0)) {
58 /* IA32_FEATURE_CONTROL locked. If we set it again we
59 get an illegal instruction. */
60 printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
61 printk(BIOS_DEBUG, "SMRR status: %senabled\n",
62 ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
63 } else {
64 if (!CONFIG(SET_IA32_FC_LOCK_BIT))
65 printk(BIOS_INFO,
66 "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
67 ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
68 wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
69 }
70 } else {
71 set_vmx_and_lock();
72 }
73
74 /* Relocate the SMM handler. */
75 smm_relocate();
76 }
77
post_mp_init(void)78 static void post_mp_init(void)
79 {
80 /* Now that all APs have been relocated as well as the BSP let SMIs
81 * start flowing. */
82 global_smi_enable();
83
84 /* Lock down the SMRAM space. */
85 smm_lock();
86 }
87
88 static const struct mp_ops mp_ops = {
89 .pre_mp_init = pre_mp_init,
90 .get_cpu_count = get_cpu_count,
91 .get_smm_info = smm_info,
92 .get_microcode_info = get_microcode_info,
93 .pre_mp_smm_init = pre_mp_smm_init,
94 .per_cpu_smm_trigger = per_cpu_smm_trigger,
95 .relocation_handler = smm_relocation_handler,
96 .post_mp_init = post_mp_init,
97 };
98
mp_init_cpus(struct bus * cpu_bus)99 void mp_init_cpus(struct bus *cpu_bus)
100 {
101 /* TODO: Handle mp_init_with_smm failure? */
102 mp_init_with_smm(cpu_bus, &mp_ops);
103 }
104